CN101188421A - Method and apparatus for distributing charge pump current and voltage for PLL circuits - Google Patents
Method and apparatus for distributing charge pump current and voltage for PLL circuits Download PDFInfo
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- CN101188421A CN101188421A CNA2007101658757A CN200710165875A CN101188421A CN 101188421 A CN101188421 A CN 101188421A CN A2007101658757 A CNA2007101658757 A CN A2007101658757A CN 200710165875 A CN200710165875 A CN 200710165875A CN 101188421 A CN101188421 A CN 101188421A
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- 239000000872 buffer Substances 0.000 claims abstract description 23
- 238000013519 translation Methods 0.000 claims description 6
- 230000003111 delayed effect Effects 0.000 abstract 4
- 238000010586 diagram Methods 0.000 description 5
- 230000033228 biological regulation Effects 0.000 description 3
- 238000012937 correction Methods 0.000 description 3
- 230000014509 gene expression Effects 0.000 description 3
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- 239000004020 conductor Substances 0.000 description 2
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- 238000013461 design Methods 0.000 description 1
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- 230000010287 polarization Effects 0.000 description 1
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/089—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
- H03L7/0891—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses the up-down pulses controlling source and sink current generators, e.g. a charge pump
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
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Abstract
A method and apparatus for distributing charge pump current and voltage for phase-locked loop circuits includes a charge pump implemented with a plurality of charge pump stages, each providing substantially equal charge pump current. Each stage includes a respective associated buffer for receiving an incoming increment (INC) signal and an incoming decrement (DEC) signal and providing an output time delayed INC signal and an output time delayed DEC. A chain of the buffers is provided to pass the time delayed INC signals and the time delayed DEC signals to the respective charge pump stages. Each of the charge pump stages includes an enable input arranged for independently enabling each respective charge pump stage.
Description
Technical field
Present invention relates in general to data processing field, and more specifically, relate to charge pump current and the voltage method and the device of phase-locked loop (PLL) circuit that is used to distribute.
Background technology
Phase-locked loop circuit is used for frequency synthesizer, so that the output signal with selectable, accurate and stable frequency to be provided, has low frequency burr and good phase noise simultaneously.Pll output signal can be connected to recreation or the clock of processor-server chip distributes or provide clock for High-speed I interface and many other application.
When PLL was locked, simple phase-frequency detector may send out little fluctuation (glitching) pulse in every reference clock cycle.Charge pump comes this fluctuation is reacted with its same way as to any other input reaction, and it changes the control voltage and current, and this causes controlling the fluctuation of voltage and charge pump current.This causes the VCO frequency shift.
A solution is to set up the ripple disable phase-frequency detector.Yet known ripple disable phase-frequency detector is often more greatly or complicated.Known ripple disable phase-frequency detector also may be to input rising and fall time and integrated circuit (IC) tracking sensitivity.During the control voltage fluctuation that occurs when reducing locking PLL, the IC process tracking has reduced the efficient of ripple disable or zero dead band PFD.
Making PFD cause among the PLL of correction pulse, ripple disable or zero dead band PFD can not help to be controlled at the variation that takes place when causing frequency or phase error.When this takes place, proportional increment of PFD generation and frequency or phase error (INC) or decrement (DEC) pulse.This pulse causes the moment translation of control voltage, the moment translation that has brought the VCO frequency.Integration is carried out in moment change to the VCO frequency on the period that PLL multiply by, makes the average frequency of VCO be associated with reference clock.The moment change of VCO frequency also can show as shake, logic chip logic that its influence is associated and I/O (IO) performance.
Along with reference generation module on the chip and clock distribute towards more cheap and lower trend, require PLL that high multiplier is provided day by day.Along with the lot of V CO circulation between the PFD renewal, the moment translation of control voltage and VCO frequency therefore and moment shake become remarkable.
Existence is to the needs of improved phase-locked loop circuit, and this improved phase-locked loop circuit comprises and be used to cause the identical average control voltage and the effective mechanism of frequency correction, and do not have the moment control voltage and frequency translation and the shake that is associated of prior art equipment.
Summary of the invention
Main aspect of the present invention provides a kind of charge pump current and voltage method and device of the phase-locked loop circuit that is used to distribute.Other importances of the present invention provide such being used to distribute charge pump current and the voltage method and the device of phase-locked loop circuit: do not have negative interaction basically, and overcome some shortcoming of prior art equipment.
Charge pump current and the voltage method and the device of the phase-locked loop circuit that is used to distribute are provided in brief.Realize charge pump with a plurality of charge pump stage, each charge pump stage provides essentially identical charge pump current.Each grade comprises the buffer that is associated separately, is used for receiving input increment (INC) signal and input decrement (DEC) signal and provides the INC signal of output time delay and the DEC that output time postpones.The chain that buffer is provided is to be delivered to each charge pump stage with the INC signal of time delay and the DEC signal of time delay.Each charge pump stage comprise be arranged to enable independently each charge pump stage enable the input.
According to feature of the present invention, each level in the charge pump is switched on different time, the total electrical charge of adding ring wave filter to is identical, and be the 1/M that upgrades the electric charge that can produce under the situation of charge pump stage at the same time from the electric charge of mismatch (mismatch), wherein M equals the number of charge pump stage.
Description of drawings
The following detailed description of illustrative the preferred embodiments of the present invention with reference to the accompanying drawings can be understood the present invention and above-mentioned and other purposes and advantage best, in the accompanying drawing:
Fig. 1 is the block diagram illustration of diagram according to the example phase-locked loop circuit of preferred embodiment.
Fig. 2 A and Fig. 2 B are the block diagram illustration of diagram together according to the example distribution formula charge pump of the phase-locked loop circuit of Fig. 1 of preferred embodiment.
Fig. 3 A and Fig. 3 B are diagram utilizations separately according to distributed charge pump in the phase-locked loop circuit of Fig. 1 of preferred embodiment, Fig. 2 and the figure that utilizes the control voltage that the conventional charge pump in the phase-locked loop circuit obtains.
Embodiment
According to feature of the present invention, provide to be used to bring essentially identical average control voltage and frequency correction and not have moment control voltage and the method for frequency translation and the shake that is associated.
Referring now to accompanying drawing, in Fig. 1,, show the example phase-locked loop circuit of representing by Reference numeral 100 generally according to preferred embodiment.According to preferred embodiment, phase-locked loop circuit 100 comprises from the input of reference oscillator 102, phase/frequency detector (PFD) 104 and distributed charge pump 250.Phase-locked loop circuit 100 comprises low pass filter (LPF) 106, voltage controlled oscillator (VCO) 108 and feedback divider or N divider 112 by the frequency output of FOUT 110 expressions is provided.The feedback signal FB of N divider 112 equals FOUN/N, and it is applied to phase/frequency detector (PFD) 104.The frequency output FOUT 110 of VCO 108 is applied to clock trees 114.
In the operation, phase/frequency detector 104 receptions and comparison reference signal and feedback signal, and generating the output pulse, this is exported the reference signal of pulse and input and is proportional from the phase difference between the feedback signal FB of VCO 108 feedbacks via N divider 112.Then, still more backward than the phase-lead of feedback VCO output according to the distributed charge pump 250 of preferred embodiment according to the reference signal phase place, come to transmit the negative or positive charge pulse to low pass filter 106.By low pass filter 106 integration is carried out in these charge pulses, be input to regulation voltage among the VCO 108 with generation; The frequency of VCO moves up or down according to regulation voltage, with synchronous with reference signal.
Usually, move highlyer or more polarization,, and make that its frequency is higher so that the output phase of VCO is in advance from the regulation voltage of ring wave filter 106, otherwise, also be like this for downward voltage.VCO output signal FOUT and reference signal FREF have the FOUT=N*FREF of relation, and wherein N is a feedback divider.
Fig. 2 A and Fig. 2 B illustrate respectively according to preferred embodiment, by the example charge pump stage of the overall expression of reference marker 200 and the distributed charge pump 250 of phase-locked loop circuit 100.
According to feature of the present invention, utilize a plurality of charge pump stage 200 to realize charge pump, each charge pump stage provides the basic charge pump current that equates.Each grade 200 comprises the buffer that is associated separately, is used for receiving input increment (INC) signal and input decrement (DEC) signal, and the INC signal of output time delay and the DEC that output time postpones are provided.The chain that buffer is provided is to be delivered to each charge pump stage with the INC signal of time delay and the DEC signal of time delay.Each charge pump stage comprise be arranged to enable independently each charge pump stage enable the input.
According to feature of the present invention, each level 200 in the charge pump 250 is switched on different time, the total electrical charge of adding ring wave filter to is identical, and is the 1/M that upgrades the electric charge that can produce under the situation of charge pump stage at the same time from the electric charge of mismatch, and wherein M equals the number of charge pump stage.
Referring now to Fig. 2 A, comprise charge pump 202 and by the time delay buffer or the functional blocks of reference marker 204 overall expressions according to the charge pump stage 200 of preferred embodiment.Charge pump 202 receives input increment (INCi) signal and input decrement (DECi) signal and enables to import the ENABLE signal, and output OUT, VC and phase inverter output OUT N, VCN are provided.The time delay functional block comprises buffer 206,208, and they receive input increment signal INCi and input decrement signals DECi and provide the increment signal INC (i+1) that output time postpones and the decrement signals DEC (i+1) of output time delay via separately conductor or lead 214,216 via separately conductor or lead 210,212 respectively.The time delay that buffer 206,208 provides is predefined or the time value that has been provided with, as, 20 psecs (ps).
Referring now to Fig. 2 B, show the example distribution formula charge pump 250 of the parallel level 200 that comprises predetermined number M.For example, in the example shown, provide 8 parallel levels 200, all transmitted the basic charge pump current amount that equates to LPF 106 at output VC, VCN place.The chain of distributed charge pump delay buffer 250 service time 204 of the present invention is delivered to each level 200 with increment (INC) and decrement (DEC) signal from simple PFD104.Then, each grade 200 with time delay T of 20ps receives separately INC and DEC signal after following time delay:
Level #1,200, at time=0ps
Level #2,200, at time=20ps
Level #3,200, at time=40ps
Or the like.
When PLL was in stable state, basic INC and the DEC pulse that equates of PFD 104 outputs was intended to them and cancels each other.Yet, in practice, between INC and the DEC pulse some mismatches are always arranged, and typically, this can produce shake.
In distributed charge pump 250 of the present invention, each grade 200 of charge pump 250 switched on the different time, the total electrical charge of adding ring wave filter 106 to is identical, electric charge from mismatch is the 1/M that upgrades the electric charge that can produce under the situation of all charge pump stage 200 at the same time, and wherein M represents the number of charge pump stage 200.
Can enable ENABLE＜1 to 8 by any order〉select, but generally can activate by descending.Design the delay of each buffer 206,208 in each time delay functional block 204 big as far as possible, to be higher than the PLL endless belt substantially wide as long as their delay remains.Because the wide 30MHz that generally is to the maximum of PLL endless belt is not so this is a problem.The dead band of the minimum delay of buffer more than or equal to the PFD in the PLL circuit 100 104 postpones, and it approximately is 20ps in 90 nanometer CMOS technology.
According to feature of the present invention, the delay of buffer 206,208 even as big as make PLL be in stable state and during little ring is proofreaied and correct from the width of the pulse up and down of PFD 104 all less than buffer delay.For each uses this delay advantageously regulate buffer 206,208, perhaps, also can be programmable with postponing to be designed to, and use for each and to regulate this delay, perhaps also can postpone to be set to zero.
Referring now to Fig. 3 A, show the example control voltage that utilization obtains according to distributed charge pump 250 in the phase-locked loop circuit 200 of preferred embodiment, Fig. 2 A and Fig. 2 B.
Also with reference to Fig. 3 B, the example of utilizing the conventional charge pump in the phase-locked loop circuit to obtain is controlled voltage.In Fig. 3 A and Fig. 3 B, shown control voltage is corresponding to clock jitter.
By a relatively large margin fluctuation is corresponding to shaking than scale clock in the traditional charge pump in the phase-locked loop circuit of Fig. 3 B on the control voltage.
Although described the present invention with reference to the details of the embodiments of the invention shown in the accompanying drawing, these details are not intended to limit the desired scope of the present invention of claims.
Claims (10)
1. be used to the distribute charge pump current of phase-locked loop circuit and the device of voltage comprise:
Charge pump comprises a plurality of charge pump stage, and each described charge pump stage provides the basic mean charge pump electric current that equates;
Each described charge pump stage comprises time delay buffer function piece, and this time delay buffer function piece receives input increment (INC) signal and input decrement (DEC) signal and provides the INC signal of output time delay and the DEC that output time postpones;
Described each time delay buffer function piece is coupled to chain, is used for the INC signal of time delay and the DEC signal of time delay are delivered to next corresponding charge pump stage; And
Each described charge pump stage comprise independently enable the input.
2. be used to the distribute charge pump current of phase-locked loop circuit and the device of voltage as claimed in claim 1, wherein said time delay buffer function piece has preset time to postpone, for each of described a plurality of charge pump stage, described preset time postpones to be basic and equates.
3. be used to the distribute charge pump current of phase-locked loop circuit and the device of voltage as claimed in claim 1, wherein said time delay buffer function piece has the predetermined time delay of selection, and the predetermined time delay of described selection postpones greater than the dead band of the phase/frequency detector that is associated in the phase-locked loop circuit (PFD).
4. be used to the distribute charge pump current of phase-locked loop circuit and the device of voltage as claimed in claim 1, wherein said time delay buffer function piece has the predetermined time delay of the selection of about 20 psecs.
5. be used to the distribute charge pump current of phase-locked loop circuit and the device of voltage as claimed in claim 1 wherein enable each of corresponding described charge pump stage on the different time.
6. be used to the distribute charge pump current of phase-locked loop circuit and the device of voltage as claimed in claim 5, wherein M represents the number of charge pump stage, and wherein, by adding the 1/M of the total electrical charge of the ring wave filter that is associated to and represent electric charge from mismatch by upgrading all charge pump stage simultaneously.
7. be used to the distribute charge pump current of phase-locked loop circuit and the device of voltage as claimed in claim 1, wherein said a plurality of charge pump stage are arranged by parallel, and wherein, are enabled each of corresponding described charge pump stage on the different time.
8. be used to the distribute charge pump current of phase-locked loop circuit and the device of voltage as claimed in claim 1, wherein said time delay buffer function piece has the predetermined time delay by the T representative, and wherein be coupled to chain with the DEC signal with the INC signal of time delay and time delay be delivered to that described each time delay buffer function piece of next corresponding charge pump stage and described charge pump stage have respectively by 0, T, 2T, 3T, 4T ..., the distributed time delay represented of MT, wherein M equals the number of charge pump stage.
9. be used to the distribute charge pump current of phase-locked loop circuit and the device of voltage as claimed in claim 1 wherein enable each of corresponding described charge pump stage on the different time, wherein eliminate the translation of moment control voltage substantially.
10. the charge pump current and the voltage method of the phase-locked loop circuit that is used to distribute comprise step:
The charge pump that comprises a plurality of parallel charge pump stage is provided, and each charge pump stage provides the basic charge pump current that equates;
Each that utilize described a plurality of charge pump stage receives input increment (INC) signal and input decrement (DEC) signal and provides INC signal that output time postpones and DEC that output time postpones;
The INC signal of time delay and the DEC signal of time delay are delivered to next corresponding charge pump stage; And
On the different time, enable each corresponding charge pump stage independently.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US11/561,431 | 2006-11-20 | ||
| US11/561,431 US20080116947A1 (en) | 2006-11-20 | 2006-11-20 | Method and Apparatus for Distributing Charge Pump Current and Voltage for PLL Circuits |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN101188421A true CN101188421A (en) | 2008-05-28 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNA2007101658757A Pending CN101188421A (en) | 2006-11-20 | 2007-11-07 | Method and apparatus for distributing charge pump current and voltage for PLL circuits |
Country Status (2)
| Country | Link |
|---|---|
| US (2) | US20080116947A1 (en) |
| CN (1) | CN101188421A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8692597B1 (en) | 2013-03-13 | 2014-04-08 | Pmc-Sierra Us, Inc. | Phase-locked loop based clock generator and method for operating same |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6844762B2 (en) * | 2002-10-30 | 2005-01-18 | Freescale Semiconductor, Inc. | Capacitive charge pump |
| US6903585B2 (en) * | 2003-06-27 | 2005-06-07 | Analog Devices, Inc. | Pulse width modulated common mode feedback loop and method for differential charge pump |
| US7167037B2 (en) * | 2005-06-07 | 2007-01-23 | Northrop Grumman Corporation | Charge pump bias network |
-
2006
- 2006-11-20 US US11/561,431 patent/US20080116947A1/en not_active Abandoned
-
2007
- 2007-10-15 US US11/872,356 patent/US20080116959A1/en not_active Abandoned
- 2007-11-07 CN CNA2007101658757A patent/CN101188421A/en active Pending
Also Published As
| Publication number | Publication date |
|---|---|
| US20080116959A1 (en) | 2008-05-22 |
| US20080116947A1 (en) | 2008-05-22 |
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Open date: 20080528 |