CN102404001B

CN102404001B - Multi-phase clock generation and transmission circuit

Info

Publication number: CN102404001B
Application number: CN 201110440477
Authority: CN
Inventors: 宁宁; 罗文�; 吴霜毅; 李靖; 眭志凌; 胡勇; 陈华; 于奇
Original assignee: University of Electronic Science and Technology of China
Current assignee: Chengdu Ming Kesi Microelectronics Technology LLC
Priority date: 2011-12-26
Filing date: 2011-12-26
Publication date: 2013-05-29
Anticipated expiration: 2031-12-26
Also published as: CN102404001A

Abstract

The invention discloses a multi-phase clock generation and transmission circuit, which relates to the clock technology in a semiconductor integrated circuit. The circuit comprises a multi-phase clock generation circuit and a multi-phase clock transmission circuit. The multi-phase clock generation circuit comprises a frequency doubling module and a multi-phase clock generation module; and the multi-phase clock transmission circuit comprises a clock transmission module Tj_a, a clock transmission module Tj_b, a transmission line La and a clock feedback line Lb. A clock signal clk_j is produced by the clock generation module and a required clock signal CLKj is output after the clock signal clk_j passes through the clock transmission module Tj_a, the transmission line Lj_a, the clock feedback line Lj_b and the clock transmission module Tj_b. The clock transmission module Tj_a is close to the clock generation circuit, and the clock transmission module Tj_b is close to a load circuit driven by the clock. The multi-phase clock produced by the circuit provided by the invention can provide different drive capabilities and realize accurate rated phase difference and smaller vibration.

Description

A kind of multi-phase clock produces and transfer circuit

Technical field

The multi-phase clock that the present invention relates in the semiconductor integrated circuit produces and tranmission techniques

Background technology

In semiconductor integrated circuit, need proportion a plurality of clocks the same, that keep specified phase difference, so a plurality of clocks are called as multi-phase clock.Adopting under the occasion of multi-phase clock, adopting the clock generating circuit generation multi-phase clock of formations such as the phase-locked loop line output of going forward side by side in the past, and then multi-phase clock is being sent to required circuit module.Traditional multi-phase clock as shown in Figure 1 produces and transfer circuit, the generation of multi-phase clock adopts traditional phase-locked loop pll in conjunction with delay locked loop DLL technology (perhaps PLL is in conjunction with the delay cell technology), for multi-phase clock being assigned in the required circuit unit module, adopt the technology of Special wiring, adopt the multi-phase clock that this mode realizes owing to do not detect and adjust mechanism in the transport process, owing to the impact of technique, be easy to cause the deviation of phase place.And if the driving force that each multi-phase clock requires is different, in order to improve the driving force of some clock, the drive circuit that needs larger driving force, adopt as shown in Figure 2 traditional according to Special wiring mode and carry out multi-phase clock in conjunction with different buffer cells and transmit, cause easily the difference of mutual specified phase difference.And, when clock generation circuit and clock receiving circuit in the situation of chip layout apart from each other, the conveyer line that traditional multi-phase clock tranmission techniques uses is subject to the noise effect of chip internal environment, will increase certain shake.Therefore, receive the phase relation between the clock that just can't guarantee each phase in each circuit module of multi-phase clock, its structure will cause the phase place of multi-phase clock inaccurate, thereby causes the malfunction of circuit.

Summary of the invention

Theme of the present invention is for high speed integrated circuit such as microprocessor and time the interweave generation of the required multi-phase clock signal of the clock signal of each passage of ADC and transmission etc.For the multi-phase clock of realizing producing can reach specified phase difference accurately and low jitter ground is sent to required driven circuit, as shown in Figure 3, the present invention comprises multi-phase clock generation circuit 1 and multi-phase clock transfer circuit 2.Multi-phase clock produces circuit and comprises frequency multiplication module and multi-phase clock generation module, the frequency multiplication module is inputted as reference clock frequency m times signal clk_0 and with its clock as the multi-phase clock generation module take the mode generated frequency of phase-locked loop, and the multi-phase clock generation module produces multi-phase clock clk_1-clk_n in the mode of delay line or delay phase-locked loop.The multi-phase clock transfer circuit is for the clock clk_j (j=1 of arbitrary phase ... n) all provide specific drive access, its circuit comprises clock delivery module Tj_a, clock delivery module Tj_b, conveyer line Lj_a, clock feedback line Lj_b.CLKj enters clock delivery module Tj_a through oversampling clock feedback line Lj_b with clk_j as shown in Figure 3, clock delivery module Tj_a obtains both phase place comparative results, and then the homogenous frequency signal that produces suitable phase place by inter-process is sent to clock delivery module Tj_b through conveyer line Lj_a, clock delivery module Tj_b suitably regulates (such as the adjustment of driving force etc.) to the clock of input, exports to the required clock signal clk j of driven circuit.By aforesaid method, only need guarantee conveyer line L1_b-Ln_b equal in length, institute is influenced identical, and it is equal just can clocking CLK1-CLKn to guarantee that arbitrarily two corresponding with clk_1-clk_n of between the two phase difference are transmitted between clock phase difference.And method provided by the invention can be with clock delivery module Tj_a (j=1 ... n) close with multi-phase clock generation circuit layout, and separate layout with clock delivery module Tj_b.Clock delivery module Tj_b is often close with driven circuit layout in the high-speed semiconductor integrated circuit, and multi-phase clock generation circuit is many and the reference clock source layout is close, while is based on the frequency multiplication module of phase-locked loop, and based on the multi-phase clock generation module of delay phase-locked loop with based on phase-locked loop or postpone phase-locked clock delivery module Tj_a (j=1 ... n) all be the major sources of noise, these noise sources and driven circuit are separated layout, can reduce these noise sources to the impact of driven circuit.And the clock transfer circuit mainly is based on phase-locked loop or delay phase-locked loop technology, and its phase noise to input clock has certain filter action, can reduce to a certain extent the shake of required multi-phase clock.

Description of drawings

Fig. 1 is that traditional multi-phase clock produces and transfer circuit, and wherein: the 1-multi-phase clock produces circuit, 2a-multi-phase clock conveyer line;

Fig. 2 is that traditional multi-phase clock produces and transfer circuit, and wherein: the 1-multi-phase clock produces circuit, and 2b-is with the transfer circuit of driving force;

Fig. 3 is that the multi-phase clock that the present invention proposes produces and the transfer circuit principle, and wherein: the heterogeneous clock of 1-produces circuit, 2-multi-phase clock transfer circuit;

Fig. 4 is for implementing a multi-phase clock transfer circuit that adopts, wherein: 3-clock delivery module Tj_a, 4-clock delivery module Tj_b;

Fig. 5 is for implementing the two multi-phase clock transfer circuits that adopt, wherein: 3a-clock delivery module Tj_a, 4a-clock delivery module Tj_b.

Embodiment

The below describes with reference to accompanying drawing about embodiments of the present invention.

Embodiment one (in conjunction with Fig. 3, Fig. 4)

Reference clock enters multi-phase clock and produces circuit as shown in Figure 3, usually the frequency multiplication module in the multi-phase clock generation circuit adopts phase-locked loop (PLL:Phase Locked Loop) technology to realize that the generation frequency is reference clock frequency m clock signal doubly, and carry out the adjustment of driving force, enter the multi-phase clock generation module in the multi-phase clock generation circuit, usually the multi-phase clock generation module adopts the technology of delay phase-locked loop or delay line, produces multi-phase clock clk_1-clk_n.Produce the arbitrary phase clock clk_j (j=1 of circuit evolving for multi-phase clock ... n), the embodiment one of its transfer circuit as shown in Figure 4.The transfer circuit of clk_j comprises clock delivery module Tj_a, clock delivery module Tj_b, conveyer line Lj_a, clock feedback line Lj_b.Wherein clock delivery module Tj_a comprises the line of phase frequency detector PFD (perhaps phase discriminator PD), charge pump CP, low pass filter LPF, voltage controlled oscillator VCO and these intermodules.Phase frequency detector PFD (perhaps phase discriminator PD) carries out the phase bit comparison with input clock clk_j and the clock CLKj that is produced by described clock transfer circuit through the clock signal that clock feedback line Lj_b sends back, and sending comparative result to charge pump CP, charge pump CP produces corresponding electric current and enters low pass filter LPF and produce control voltage and control the oscillator signal that voltage controlled oscillator VCO produces required frequency.The oscillator signal that VCO produces flows to clock delivery module Tj_b through conveyer line Lj_a, Tj_b processes the oscillator signal of VCO generation with the form of buffer BUF and generates the requirement that required CLKj satisfies the driven circuit of postorder, CLKj sends back phase frequency detector PFD (perhaps phase discriminator PD) through clock feedback line Lj_b simultaneously, realizes feedback regulation.It is equal that the multi-phase clock signal CLK1-CLKn that adopts mode of the present invention to obtain guarantees that arbitrarily two corresponding with clk_1-clk_n of between the two phase difference are transmitted between clock phase difference, and traditional mode of wiring that directly resulting multi-phase clock clk_1-clk_n adopted transmits relative phase generation deviation between relative phase and the corresponding multi-phase clock clk_1-clk_n that is transmitted between the multi-phase clock signal that obtains, the circuit operation of generation mistake.The multi-phase clock CLK1-CLKn that adopts transfer circuit implementation as shown in Figure 4 to obtain simultaneously can have different driving forces, and shake is less.

Embodiment two (in conjunction with Fig. 3, Fig. 5)

Reference clock enters multi-phase clock and produces circuit as shown in Figure 3, usually the frequency multiplication module in the multi-phase clock generation circuit adopts phase-locked loop (PLL:Phase Locked Loop) technology to realize that the generation frequency is reference clock frequency m clock signal doubly, and carry out the adjustment of driving force, enter the multi-phase clock generation module in the multi-phase clock generation circuit, usually the multi-phase clock generation module adopts the technology of delay phase-locked loop or delay line, produces multi-phase clock clk_1-clk_n.Produce the arbitrary phase clock clk_j (j=1 of circuit evolving for multi-phase clock ... n), the embodiment two of its transfer circuit as shown in Figure 5.The transfer circuit of clk_j comprises clock delivery module Tj_a, clock delivery module Tj_b, conveyer line Lj_a, clock feedback line Lj_b.Wherein clock delivery module Tj_a comprises the line of phase frequency detector PFD (perhaps phase discriminator PD), charge pump CP, low pass filter LPF, voltage controlled delay line VCDL and these intermodules.Phase frequency detector PFD (perhaps phase discriminator PD) carries out the phase bit comparison with input clock clk_j and the clock CLKj that is produced by described clock transfer circuit through the clock signal that clock feedback line Lj_b sends back, and send comparative result to charge pump CP, charge pump CP produces corresponding electric current and enters low pass filter LPF generation control voltage Vc, this control voltage control clk_j the time-delay of transmission delay line of process, produce the same frequency clock signal of desired phase.The clock signal of VCDL output flows to clock delivery module Tj_b through conveyer line Lj_a, Tj_b processes the clock signal of input with the form of buffer BUF and generates the requirement that required CLKj satisfies the driven circuit of postorder, CLKj sends back phase frequency detector PFD (perhaps phase discriminator PD) through clock feedback line Lj_b simultaneously, realizes feedback regulation.It is equal that the multi-phase clock signal CLK1-CLKn that adopts mode of the present invention to obtain guarantees that arbitrarily two corresponding with clk_1-clk_n of between the two phase difference are transmitted between clock phase difference, and traditional mode of wiring that directly resulting multi-phase clock clk_1-clk_n adopted transmits relative phase generation deviation between relative phase and the corresponding multi-phase clock clk_1-clk_n that is transmitted between the multi-phase clock signal that obtains, the circuit operation of generation mistake.The multi-phase clock CLK1-CLKn that adopts transfer circuit implementation as shown in Figure 5 to obtain simultaneously can have different driving forces, and shake is less.

Above example only is preferred example of the present invention, and use of the present invention is not limited to this example, and is within the spirit and principles in the present invention all, any modification of doing, is equal to replacement, improvement etc., all should be included within protection scope of the present invention.

Claims

1. a multi-phase clock produces and transfer circuit, include the multi-phase clock that is formed by frequency multiplication module and multi-phase clock generation module and produce circuit and multi-phase clock transfer circuit, it is characterized in that: the multi-phase clock transfer circuit is by clock delivery module Tj_a(j=1 ... n), clock delivery module Tj_b(j=1 ... n), conveyer line Lj_a(j=1 ... n), clock feedback line Lj_b(j=1 ... n) form, the multi-phase clock generation module produces input clock clk_j(j=1 ... n), through clock delivery module Tj_a(j=1 ... n), conveyer line Lj_a(j=1 ... n), clock feedback line Lj_b(j=1 ... n) and clock delivery module Tj_b(j=1 ... n) the needed multi-phase clock signal CLKj(j=1 of output ... n); Wherein: the clock delivery module Tj_a(j=1 in the clock transfer circuit ... n) comprise phase discriminator PD or phase frequency detector PFD, charge pump CP, low pass filter LPF, the connecting line of voltage control delay line VCDL or voltage controlled oscillator VCO and intermodule, clock delivery module Tj_b(j=1 ... n) adopt buffer BUF form, this clock delivery module Tj_a(j=1 ... n) the phase discriminator PD in or phase frequency detector PFD, multi-phase clock clk_j(j=1 to the generation of multi-phase clock generation module ... n), with from clock delivery module Tj_b(j=1 ... n) output and through clock feedback line Lj_b(j=1 ... n) phase place of the clock signal of transmission compares, produce comparative result and produce control signal through charge pump CP, this control signal produces control voltage through low pass filter LPF, this control voltage can be with input clock clk_j(j=1 ... n) after phase place changes through voltage control delay line VCDL, from clock delivery module Tj_a(j=1 ... n) output; Perhaps directly control voltage controlled oscillator VCO from the control voltage of low pass filter LPF output and produce oscillator signal from clock delivery module Tj_a(j=1 ... n) output, and through conveyer line Lj_a(j=1 ... n) be sent to clock delivery module Tj_b(j=1 ... n), this clock delivery module Tj_b(j=1 ... n) can be with conveyer line Lj_a(j=1 ... n) clock signal that sends is processed, so that clock delivery module Tj_b (j=1 ... n) clock signal CLKj(j=1 ... n) can satisfy the requirement of the driving force of postorder.

2. multi-phase clock according to claim 1 produces and transfer circuit, it is characterized in that: the clock feedback line Lj_b(j=1 in the multi-phase clock transfer circuit ... n) namely for the necessary equal in length of the conveyer line L1_b-Ln_b that transmits the n phase clock, assurance is with clock delivery module Tj_b(j=1 ... n) clock signal CLKj(j=1 ... n) phase information feeds back to Tj_a(j=1 ... n), so that enter Tj_a(j=1 ... n) two clock signal phases are identical.

3. multi-phase clock according to claim 1 produces and transfer circuit, it is characterized in that: clock delivery module Tj_a(j=1 in the multi-phase clock transfer circuit ... n) produce circuit near multi-phase clock, clock delivery module Tj_b(j=1 ... n) load circuit that drives near the clock actual needs is to reduce the chip internal Environmental Noise Influence.