CN101179091A - Three-dimensional stacked WO3 resistor accidental memory structure and manufacturing method therefor - Google Patents
Three-dimensional stacked WO3 resistor accidental memory structure and manufacturing method therefor Download PDFInfo
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- CN101179091A CN101179091A CN 200710172173 CN200710172173A CN101179091A CN 101179091 A CN101179091 A CN 101179091A CN 200710172173 CN200710172173 CN 200710172173 CN 200710172173 A CN200710172173 A CN 200710172173A CN 101179091 A CN101179091 A CN 101179091A
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Abstract
The invention belongs to the field of microelectronic technology, specifically to the structure and preparation method of a three-dimensional stackable WO<SUB>x</SUB> electric resistance random access storage. The structure of the storage comprises a gate tube and a plurality of storage units, which are in parallel connection with each other and connected with the gate tube and then laminated on the gate tube, thereby achieving the structure of one gate tube controlling a plurality of storage units. The invention is capable of greatly improving the storage integration density.
Description
Technical field
The invention belongs to microelectronics technology, be specifically related to a kind of WO that can be three-dimensional stacked
xResistor accidental memory structure and manufacture method.
Background technology
Memory occupies an important position in semi-conductor market, because portable electric appts is constantly universal, the share of nonvolatile memory in whole storage market is also increasing.Nearest non-volatile resistance memory (Resistive SwitchingMemory) because its low-power consumption, low cost, the characteristics that can break through the technology generation development restriction cause is shown great attention to.But Memister utilizes the resistance of storage medium to come storage signal in the characteristic of inverse conversion under the signal of telecommunication effect, between high resistant and low-resistance, storage medium can have a variety of, comprise binary or multi-element metal oxide, even organic compound, wherein, binary metal oxide is because it is simple in structure, speed is fast, low in energy consumption, compatible strong with traditional cmos process, and shown great attention to.
WO
x(1＜x≤3) are a kind of as binary metal oxide, and are perfect compatible with the Al interconnection process, need not to introduce new material, and can form WO in tungsten autoregistration beyond the Great Wall
xStorage medium, cost advantage is obvious
[1]
Fig. 1 shows the structure chart of traditional 1T1R memory cell.A memory resistor 200 and a gating device 000 are arranged in each memory cell 401, and TE and BE represent the top electrode and the bottom electrode of memory resistor 401 respectively.Gating device 000 general MOSFET (MOS (metal-oxide-semiconductor) memory) device that adopts must be produced on the silicon chip substrate, takies silicon area.A gating device can only be controlled a memory resistor, and integration density is low, and cost is higher.
The present invention proposes a kind of WO that can be three-dimensional stacked
xResistor accidental memory structure, several memory resistor are laminated on the gate tube, realize that a plurality of memory resistor share the structure of a gate tube, improve storage density greatly.
Summary of the invention
The object of the present invention is to provide a kind of WO that can be three-dimensional stacked
xResistor accidental memory structure and manufacture method, to improve the storage integration density.
Three-dimensional stacked WO of the present invention
xMemister, comprise: a gate tube and several memory cell, link to each other with gate tube by parallel way between the memory cell and stacked and gate tube on, particularly, be that memory cell is laminated on the gate tube along the substrate vertical direction, first electrode of each memory cell and different bit lines link to each other, and second electrode links to each other with gate tube by a public electrode, realize that a gate tube controls the structure of a plurality of memory cell.
Three-dimensional stacked WO of the present invention
xThe preparation method of Memister is after front-end process finishes, the ground floor metal
Before lead-in wire formed, concrete steps comprised:
After front-end process finishes, metallization medium layer 1;
The composite bed 1 of deposition of adhesion and W on dielectric layer 1;
Metallization medium layer 2 on composite bed 1;
The composite bed 2 of deposition of adhesion and W on dielectric layer 2;
Metallization medium layer 3 on composite bed 2;
This dielectric layer/lamination layer structure can repeat stacked 2～100 layers;
Produce hole in the stepped construction of needs formation memory, the position that does not need to make memory is protected by dielectric layer;
The tungsten cross section oxidation that will be positioned on the described hole sidewall forms annular WO
xStorage medium, its method for oxidation are plasma oxidation method or thermal oxidation process, 1＜x≤3;
In described hole, fill the electrode metal material;
Adopt the worn unnecessary electrode material of cmp method, form electrode in described hole;
Perforate above each layer W is used for the memory cell bit line on each layer is drawn;
In the perforate of the source region of gate tube, form contact window;
Deposit a dielectric layer, etching forms the isolation abutment wall at bit line extraction window mouth, metal-oxide-semiconductor source region contact window sidewall;
Deposition of adhesion and W are filled in bit line and draw place's window, contact window;
Adopt worn unnecessary W of cmp method and adhesive layer material, form bit line and draw the W of place plug and metal-oxide-semiconductor source region W plug;
With the ground floor lead-in wire memory electrode and metal-oxide-semiconductor source region W plug are coupled;
Next adopt conventional aluminium interconnection process to carry out subsequent step.
Three-dimensional stacked WO of the present invention
xThe manufacture method of Memister also can be:
The hole that forms memory cell is prepared in contact window top, metal-oxide-semiconductor source region, shares with the source region contact window, when etching memory cell hole, stops at dielectric layer 1, avoids oxidation to generate WO
xThe metal silicide oxidation in metal-oxide-semiconductor source region, after oxidation step was finished, further again etching was opened contact window during storage medium; Further fill electrode material, the etching bit line place of drawing window, the etching bit line place of drawing window sidewall isolated border wall afterwards again, fill adhesion layer and W and after the bit line place of drawing window, chemico-mechanical polishing, forms bit line and draw and locate W and fill in;
Three-dimensional stacked WO of the present invention
xThe manufacture method of Memister, bit line are to be formed by the W line, because the resistivity of W is bigger, are equivalent to bigger resistance of series connection on memory cell, can improve WO
xThe low resistance state resistance value of Memister, reduction leakage current, for example, a cross-sectional area is 1 μ m
2, the W line of long 10 μ m can produce the resistance of 56k Ω.
Description of drawings
Fig. 1 is traditional WO
xThe structure chart of Memister 1T1R memory cell.
Fig. 2 is for after front-end process finishes, deposit multilayer dielectric layer/composite bed stepped construction.
Fig. 3 a is for producing hole in the stepped construction that forms memory at needs.
Fig. 3 b is for producing hole in the stepped construction that forms memory at needs, and this hole is positioned at top, metal-oxide-semiconductor source region.
Fig. 4 a, 4b forms annular WO for the tungsten cross section oxidation that will be positioned on the described hole sidewall
xStorage medium.
Fig. 5 a, 5b is for filling the electrode metal material in the memory cell hole.
Fig. 6 a, 6b form electrode after the chemico-mechanical polishing.
Fig. 7 a is that etching formation bit line is drawn place's window and metal-oxide-semiconductor source region contact window.
Fig. 7 b is that etching formation bit line is drawn place's window.
Fig. 8 a, 8b is a metallization medium layer, after the etching, draws place's window, metal-oxide-semiconductor source region contact window sidewall formation isolation abutment wall at bit line.
Fig. 9 a, 9b is deposition of adhesion and W, is filled in bit line and draws place's window, contact window.
After Figure 10 a was chemico-mechanical polishing, the formation bit line was drawn place's W plug and is contacted the W plug with the metal-oxide-semiconductor source region.
After Figure 10 b is chemico-mechanical polishing, forms bit line and draw the W of place plug.
Figure 11 is for being coupled memory electrode and metal-oxide-semiconductor source region W plug with the ground floor metal connecting line.
Number in the figure: 000MOS gate tube, 101 first dielectric layers, 102 second dielectric layers, 103 the 3rd dielectric layers, 201 first composite beds, 202 second composite beds, 301 memory cell holes, 302 memory cell holes (sharing), 401WO with MOS source region contact hole
xStorage medium, 501 electrode materials, 502 electrodes, 503 electrodes (contact the W plug shares with the MOS source region), 601 bit lines are drawn place's window 1,602 bit line and are drawn place's window 2,603MOS source region contact hole, 701 bit lines are drawn place's window 1 sidewall and are isolated abutment wall, and 702 bit lines are drawn place's window 2 sidewalls and isolated abutment wall, and 703MOS source region contact hole sidewall is isolated abutment wall, 801 bit lines are drawn the one W of place plug, 802 bit lines are drawn the 2nd W of place plug, 803MOS source region contact W plug, 901 ground floor metal lead wires.
Embodiment
Tie full graphic hereinafter and in reference example, describe the present invention more completely, the invention provides preferred embodiment, but should not be considered to only limit to embodiment set forth herein.In the drawings, for the clear thickness that has amplified layer and zone, shown in size do not represent actual size.
At this reference diagram is the schematic diagram of idealized embodiment of the present invention, and embodiment shown in the present should not be considered to only limit to the given shape in the zone shown in the figure, but comprises resulting shape, the deviation that causes such as manufacturing.For example the curve that obtains of dry etching has crooked or mellow and full characteristics usually, but in embodiment of the invention diagram, all represents with rectangle, and the expression among the figure is schematically, but this should not be considered to limit the scope of the invention.
This is for clearly describing specific embodiment of the present invention with reference to the accompanying drawings, is to be example to form two-layer memory cell such as the multiple-level stack structure in reference to the accompanying drawings, but should be considered to limit the scope of the invention.
Figure 11 is three-dimensional stacked WO according to the present invention
xThe part of the profile of one embodiment of Memister.
With reference to Figure 11, after being depicted as front-end process and finishing, deposit multilayer dielectric layer/composite bed stepped construction, first dielectric layer 101 is formed on the substrate transistor 000, and it can be silica (PSG), the SiO that mixes phosphorus
2, SiN, SiC, dielectric materials such as SiON, SiCN, first composite bed 201 of adhesion layer/W is deposited on first dielectric layer, wherein adhesion layer plays adhesive attraction and diffusion barrier effect, it can be the Ti/TiN composite bed, or other plays the electric conducting material of same purpose, and as TiSiN, WNx, WNxCy, TiZr/TiZrN etc., second dielectric layer 102 is deposited on first composite bed, second composite bed 202 is deposited on second dielectric layer, and the 3rd dielectric layer 103 is deposited on second composite bed.
WO
x Storage medium layer 401 is to be exposed in oxygen plasma or the oxygen atmosphere by the hole that needs is formed memory cell, the oxidation of tungsten cross section, forms annular WO
xStorage medium, wherein 1＜x≤3.
Electrode 803 is by forming after the chemico-mechanical polishing, can be Ti, TiN, and W, Al, AlCu perhaps comprises the composite bed of their two or more materials.
Bit line is drawn the one W of place plug the 801 and the 2nd W plug 802, is used for the bit line of memory cell is drawn, and bit line is the composite bed of adhesion layer/W herein, and adhesive layer material can be the composite bed of Ti, TiN or Ti/TiN.
Ground floor metal connecting line 901 is used for memory cell electrode 502 is coupled together with top, metal-oxide-semiconductor source region W plug 803, realize that the substrate MOS pipe is with the memory cell coupling, metal connecting line 901 is the composite beds that comprise adhesion layer/metal lead wire, adhesion layer can be the composite bed of Ti, TiN or Ti/TiN etc., and the metal lead wire material can be Al, AlCu alloy etc.
Figure 10 b is three-dimensional stacked WO according to the present invention
xThe part of the profile of the another embodiment of Memister.
With reference to figure 10b, be that with the difference of Figure 11 the hole that forms memory cell is prepared in contact window top, metal-oxide-semiconductor source region, share with the source region contact window, when etching memory cell hole, stop at first dielectric layer, avoid oxidation to generate WO
xThe metal silicide oxidation in metal-oxide-semiconductor source region, after oxidation step was finished, further again etching was opened contact window during storage medium; Further fill electrode material, the etching bit line place of drawing window, the etching bit line place of drawing window sidewall isolated border wall afterwards again, fill adhesion layer and W and after the bit line place of drawing window, chemico-mechanical polishing, forms bit line and draw and locate W and fill in;
Fig. 2 to Figure 11 be according to the present invention forming the profile that two-layer memory cell is the execution mode of example, but the present invention is not limited to present embodiment.
After Fig. 2 has showed that conventional front-end process finishes, the profile of deposit multilayer dielectric layer/composite bed stepped construction.101,102,103 is dielectric layer, can be silica (PSG), the SiO that mixes phosphorus
2, SiN, SiC, dielectric materials such as SiON, SiCN; 201,202 is adhesion layer/W composite bed, and adhesive layer material can be the composite bed of Ti, TiN or Ti/TiN;
Fig. 3 a is the cross-sectional view after producing hole in the stepped construction that forms memory at needs, and 301 for needing to make memory cell region;
Fig. 4 a forms annular WO for the tungsten cross section oxidation that will be positioned on the described hole sidewall
xThe cross-sectional view of storage medium contacts with oxygen plasma or oxygen the W cross section that exposes under the condition of heating or not heating, it oxidation is formed WO
xStorage medium 401, wherein 1＜x≤3.
Fig. 5 a is for filling the cross-sectional view of electrode metal material behind the memory cell hole, and 501 is memory cell second electrode material, can be Ti, TiN, Al, W, AlCu, or two or more composite bed wherein.
Fig. 6 a forms cross-sectional view behind the electrode after the chemico-mechanical polishing, 502 memory cell second electrodes for forming after the chemico-mechanical polishing, public this electrode of stacked memory cell.
Fig. 7 a is that etching forms the cross-sectional view after bit line is drawn place's window and metal-oxide-semiconductor source region contact window, and 601,602 draw window for bit line, and 603 is metal-oxide-semiconductor source region contact window.
Fig. 8 a is a metallization medium layer, after the etching, cross-sectional view after bit line is drawn place's window, metal-oxide-semiconductor source region contact window sidewall formation isolation abutment wall, 701,702,703 are sidewall isolation abutment wall, are used for bit line is drawn place's tungsten plug, top, metal-oxide-semiconductor source region tungsten plug is isolated with adhesion layer/W composite bed, and the abutment wall dielectric material can be silica (PSG), the SiO that mixes phosphorus
2, SiN, SiC, dielectric materials such as SiON, SiCN.
Fig. 9 a deposition of adhesion and W are filled in bit line and draw place's window, and the cross-sectional view behind the contact window, adhesion layer can be Ti, the composite bed of TiN or Ti/TiN.
After Figure 10 a is chemico-mechanical polishing, forms bit line and draw place's W plug and contact W plug back cross-sectional view with the metal-oxide-semiconductor source region, 801,802 draw the W plug for first, second of memory cell bit line, and 803 is that the metal-oxide-semiconductor source region contacts W and fills in.
Figure 11 with public second electrode of memory cell and the coupling of metal-oxide-semiconductor source region W plug, realizes the structure of the shared gate tube of several memory cell for the ground floor metal connecting line memory cell second electrode and metal-oxide-semiconductor source region W being filled in coupling back cross-sectional view.
So far, three-dimensional stacked WO
xMemory fabrication is finished, and subsequent technique is conventional Al interconnection process.
Three-dimensional stacked WO
xThe position that memory is made is not limited under the ground floor metal connecting line, also can be positioned on any layer of metal interconnection line.
Another embodiment of the present invention, the hole that forms memory cell is prepared in contact window top, metal-oxide-semiconductor source region, shares with the source region contact window, when etching memory cell hole, stops at first dielectric layer 101, avoids oxidation to generate WO
xThe metal silicide oxidation in metal-oxide-semiconductor source region, after oxidation step was finished, further again etching was opened contact window during storage medium.
Fig. 3 b is the cross-sectional view after producing hole in the stepped construction that forms memory at needs, and hole 302 is positioned at top, metal-oxide-semiconductor source region, that is as top, metal-oxide-semiconductor source region contact window.
Fig. 4 b forms annular WO for the tungsten cross section oxidation that will be positioned on the described hole sidewall
xThe cross-sectional view of storage medium contacts with oxygen plasma or oxygen the W cross section that exposes under the condition of heating or not heating, it oxidation is formed WO
xStorage medium 401, wherein 1＜x≤3.
Fig. 5 b is for filling the adhesion layer/cross-sectional view of W composite bed behind contact window, and wherein adhesion layer can be the composite bed of Ti, TiN or Ti/TiN.
Fig. 6 b is the cross-sectional view that forms after the chemico-mechanical polishing after W fills in, and 503 for the W that forms after the chemico-mechanical polishing fills in, and adhesion layer links to each other with the substrate MOS pipe by the W plug as the common electrode of memory cell.
Fig. 7 b is that etching forms the cross-sectional view after bit line is drawn window, and 601,602 draw window for bit line.
Fig. 8 b is a metallization medium layer, after the etching, and the cross-sectional view after bit line is drawn place's window sidewall formation isolation abutment wall, 701,702 are sidewall isolation abutment wall, are used for that bit line is drawn place's tungsten plug and isolate with adhesion layer/W composite bed, and the abutment wall dielectric material can be silica (PSG), the SiO that mixes phosphorus
2, SiN, SiC, dielectric materials such as SiON, SiCN.
Fig. 9 b deposition of adhesion and W are filled in the cross-sectional view after bit line is drawn place's window, and adhesion layer can be Ti, the composite bed of TiN or Ti/TiN.
After Figure 10 b is chemico-mechanical polishing, forms bit line and draw the W of place plug.
So far, three-dimensional stacked WO
xMemory fabrication is finished, and subsequent technique is conventional Al interconnection process.
Three-dimensional stacked WO
xThe position that memory is made is not limited under the ground floor metal connecting line, also can be positioned on any layer of metal interconnection line.
Next, will explain the integrated step of concrete technology of present embodiment with Fig. 2 to cross sectional view shown in Figure 11.
With reference to figure 2, after conventional front-end process finishes, deposit multilayer PSG, TiN/W composite bed stepped construction.PSG thickness is 10～20nm, and the TiN/W composite bed thickness is 10～30nm, and this dielectric layer/lamination layer structure can repeat stacked 2～100 layers.
Further enforcement of the present invention is patterned into line strip with dielectric layer/lamination layer structure, and every layer of TiN/W composite bed can be used as the bit line of every layer of memory cell.
Further enforcement of the present invention, deposition PSG, CMP ends at the superiors' dielectric layer, and line strip dielectric layer/composite bed stepped construction is kept apart mutually.
Further enforcement of the present invention with reference to figure 3b, is produced hole above the metal-oxide-semiconductor source region, stop at metal-oxide-semiconductor top ground floor dielectric layer, is used for the define storage units position.
Further enforcement of the present invention, with reference to figure 4b, the tungsten cross section oxidation that will be positioned on the described hole sidewall forms annular WO
xStorage medium, oxidizing process can be plasma oxidations, by the conditions such as time, power of control plasma oxidation, adjust the WO of formation
xPerformance and thickness thereof.
Further enforcement of the present invention by the further etching of RIE, ends at the metal silicide in metal-oxide-semiconductor source region with the memory cell hole.
Further enforcement of the present invention with reference to figure 5b, is filled in TiN/W composite bed 501 in the memory cell hole, and TiN and W be the method deposition of available CVD all.
Further enforcement of the present invention with reference to figure 6b, through chemico-mechanical polishing TiN/W composite bed, ends at the superiors' dielectric layer, forms memory cell public electrode and source region top W plug 503.
Further enforcement of the present invention, with reference to figure 7b, dry etching forms bit line and draws window 601 and 602.
Further enforcement of the present invention, with reference to figure 8b, deposition SiN behind the dry etching, forms on the sidewall of bit line extraction window mouth and isolates abutment wall 701 and 702.
Further enforcement of the present invention with reference to figure 9b, is filled the TiN/W composite bed and is drawn place's window in bit line, and TiN and W be the method deposition of available CVD all.
Further enforcement of the present invention with reference to figure 10b, through chemico-mechanical polishing TiN/W composite bed, ends at the superiors' dielectric layer, and bit line is drawn W plug 801 and 802.
So far, ground floor Al wiring and Cu
xThe O memory cell forms.
WO as mentioned above
xThe integrated method of Memister preparation and aluminium interconnection process can repeat before the wiring of ground floor aluminium or on the wiring of other layers aluminium, and the basic step method remains unchanged, and therefore can form three-dimensional stacked Memister structure.
List of references
[1]C.H.Ho，E.K.Lai，M.D.Lee，C.L.Pan，Y.D.Yao，K.Y.Hsieh，Rich?Liu，and?C.Y.Lu，″A?Highly?Reliable?Self-Aligned?Graded?Oxide?WOx?Resistance?Memory：ConductionMechanisms?and?Reliability″，Symposium?on?VLSI?Technology?Digest?of?Technical?Papers，p.228，2007
Claims (5)
1. three-dimensional stacked WO
xResistance random access memory, it is characterized in that comprising
A gate tube, several memory cell, memory cell is laminated on the gate tube along the substrate vertical direction, and first electrode of each memory cell links to each other with different bit lines, second electrode links to each other with gate tube by a public electrode, realizes that a gate tube controls the structure of a plurality of memory cell.
2. Memister according to claim 1 is characterized in that also comprising, stacked memory cell is prepared in before the wiring of ground floor aluminium or on the wiring of other layers aluminium, realizes three-dimensional stacked structure.
3. Memister according to claim 1, its feature also are with the W line as bit line.
4. make WO as claimed in claim 1 for one kind
xThe method of Memister is characterized in that several memory cell are stacked on gate tube, realizes that a gate tube controls the structure of a plurality of memory cell, and concrete steps are:
After front-end process finishes, the composite bed of repeated deposition dielectric layer, adhesion layer/W, totally 2～100 layers;
Produce hole in the stepped construction of needs formation memory, the position that does not need to make memory is protected by dielectric layer;
The tungsten cross section oxidation that will be positioned on the described hole sidewall forms annular WO
xStorage medium, its method for oxidation are plasma oxidation method or thermal oxidation process, 1＜x≤3;
In described hole, fill the electrode metal material;
Adopt the worn unnecessary electrode material of cmp method, form electrode in described hole;
Perforate above each layer W is used for the memory cell bit line on each layer is drawn;
Perforate above the source region of gate tube forms contact window;
Deposit a dielectric layer, etching forms the isolation abutment wall at bit line extraction window mouth and metal-oxide-semiconductor source region contact window sidewall;
Deposition of adhesion and W are filled in bit line and draw window, contact window;
Adopt worn unnecessary W of cmp method and adhesive layer material, form bit line and draw the W of place plug and metal-oxide-semiconductor source region W plug;
With the ground floor lead-in wire memory electrode and metal-oxide-semiconductor source region W plug are coupled;
Next adopt conventional aluminium interconnection process to carry out subsequent step.
5. according to the WO of claim 4
xPreparation method's method of Memister, its feature are that also the hole that forms memory cell is prepared in contact window top, metal-oxide-semiconductor source region, shares with the source region contact window.
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| Application Number | Priority Date | Filing Date | Title |
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| CN 200710172173 CN101179091A (en) | 2007-12-13 | 2007-12-13 | Three-dimensional stacked WO3 resistor accidental memory structure and manufacturing method therefor |
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| CN 200710172173 CN101179091A (en) | 2007-12-13 | 2007-12-13 | Three-dimensional stacked WO3 resistor accidental memory structure and manufacturing method therefor |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102682840A (en) * | 2011-03-18 | 2012-09-19 | 中国科学院微电子研究所 | Method and structure for improving reliability of non-volatile resistive memory |
| CN103682096A (en) * | 2013-12-31 | 2014-03-26 | 上海集成电路研发中心有限公司 | Resistive random access memory capable of realizing multilevel storage |
| CN113437212A (en) * | 2021-06-01 | 2021-09-24 | 长江先进存储产业创新中心有限责任公司 | Three-dimensional phase change memory and preparation method thereof |
-
2007
- 2007-12-13 CN CN 200710172173 patent/CN101179091A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102682840A (en) * | 2011-03-18 | 2012-09-19 | 中国科学院微电子研究所 | Method and structure for improving reliability of non-volatile resistive memory |
| CN103682096A (en) * | 2013-12-31 | 2014-03-26 | 上海集成电路研发中心有限公司 | Resistive random access memory capable of realizing multilevel storage |
| CN103682096B (en) * | 2013-12-31 | 2018-11-09 | 上海集成电路研发中心有限公司 | A kind of resistance-variable storing device of achievable multilevel storage |
| CN113437212A (en) * | 2021-06-01 | 2021-09-24 | 长江先进存储产业创新中心有限责任公司 | Three-dimensional phase change memory and preparation method thereof |
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Open date: 20080514 |