CN101174236A - Debugging card and computer debugging method - Google Patents
Debugging card and computer debugging method Download PDFInfo
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- CN101174236A CN101174236A CNA2006100634604A CN200610063460A CN101174236A CN 101174236 A CN101174236 A CN 101174236A CN A2006100634604 A CNA2006100634604 A CN A2006100634604A CN 200610063460 A CN200610063460 A CN 200610063460A CN 101174236 A CN101174236 A CN 101174236A
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Abstract
The invention provides a debug card used for debugging the functions of a computer and spliced on the slot of a motherboard, which comprises a display device and a programmable logic device. The display device comprises a VGA connector which can be connected with a display, the programmable logic device comprises a data latching module used for latching the debugging datum of the computer, and a data conversion module used for converting the debugging datum of the computer, the data conversion module is connected with a VGA controller, and the VGA controller is connected with the VGA connector. Moreover, the invention also provides a computer debugging method.
Description
Technical field
The present invention relates to a kind of test chart, particularly about a kind of test chart that detects computer effectively.The invention still further relates to a kind of computer debugging method.
Background technology
Current computer applications is extensive, uses for a long time, and computer also some faults can occur, and how computer overhauls, then the big problem for facing now.
Many test charts in order to detecting computer work state appear in industry, a kind of test chart is wherein arranged, this card is plugged on PCI (the Peripheral Component Interconnection) slot of mainboard, it comprises a display device, this display device is that some light emitting diodes constitute, this display device can show the numeric character of test process, enables (BE#) etc. such as data (Data), address (Address), instruction (Command) and hyte.
This test chart with address, data, instruction and the hyte of the pci bus cycle desiring to inspect signal condition such as enable and latched and pass through diode displaying.But because light emitting diode can not the complete information that shows computer glitch intuitively, the testing staff must get and contrast complete information carefully and overhaul, and detection efficiency is affected.
Summary of the invention
In view of above content, be necessary to provide a kind of test chart and a kind of computer debugging method that can detect computer effectively.
A kind of test chart, be used to debug computer function, be plugged on the slot of a mainboard, described test chart comprises a display device and a programmable logic device (PLD), described display device comprises that one can connect the VGA connector of a display, described programmable logic device (PLD) comprises that a data latching module and that is used to latch the computer tune-up data is used to change the data conversion module of computer tune-up data, and described data conversion module connects a vga controller, and described vga controller connects described VGA connector.
A kind of computer debugging method, this method comprises the following steps: at least
One programmable logic device (PLD) is provided, and described programmable logic device (PLD) comprises that a data latching module and that is used to latch the computer tune-up data is used to change the data conversion module of computer tune-up data;
Described data latching module is with effectively address, instruction, hyte enable on the pci bus, data and 80H address are comprised data storing;
Described data conversion module is changed the data that described data latching module stores;
The data that the process data conversion module is changed out by VGA connector output, show by a display after a vga controller data processing again.
Compared to prior art, described test chart can show that by the VGA video detection person can pass through the complete Debugging message of video checking computer, has improved detection efficiency effectively with detected data.
Description of drawings
The invention will be further described in conjunction with embodiment with reference to the accompanying drawings.
Fig. 1 is the theory diagram of test chart preferred embodiment of the present invention.
Fig. 2 is the display device theory diagram of test chart preferred embodiment of the present invention.
Fig. 3 is the sequential chart of test chart preferred embodiment of the present invention.
Fig. 4 is the VGA displaying principle block diagram of test chart preferred embodiment of the present invention.
Fig. 5 is the principle flow chart of test chart preferred embodiment of the present invention.
Fig. 6 is the random access memory data transmission principle block diagram able to programme of test chart preferred embodiment of the present invention.
Embodiment
See also Fig. 1, one test chart 10 is plugged in the pci bus slot 20 of a computer main board, described test chart 10 comprises that a programmable logic device (PLD), is used to show display device 12, a USB (Universal Serial Bus) port one 3, a ROM (read-only memory) socket (ROM Socket) 14 and one random access memory 15 able to programme of detecting information, in the present embodiment, described programmable logic device (PLD) is a field programmable gate array (FPGA) 11.
Please continue to consult Fig. 1 and Fig. 6, described USB port 13 can connect external host, it can be used as data upload or data download port, by described USB port 13, data (for example bios program) transmission that external host can need the computer that is detected is come in, in addition, also the computerized information that is detected can be delivered to external host gets on.
The described ROM (read-only memory) socket 14 BIOS chip etc. of can pegging graft on it, when the bios program of computer system damages, by an addressing functional module 141 of being located at described field programmable gate array 11 bios program is imported, to upgrade the bios program in the computer system.
Described random access memory able to programme 15 receives the external transmission data by described USB port 13 and described ROM (read-only memory) socket 14, it can have ROM (read-only memory) function storage computer information needed, bios program for example, when the computer bios program went wrong, described random access memory 15 able to programme can import bios program in computer system.
See also Fig. 2, described display device 12 comprises seven-segment display combination 121 and one VGA (Video Graphies Array) connector 122, in the present embodiment, described seven-segment display combination 121 comprises 22 seven-segment displaies, wherein, eight are used for video data, eight and are used for explicit address, the pro and con of described test chart is respectively equipped with two seven-segment displaies, be used to the data that show that the 80H address is comprised, one of them idsplay order of two other seven-segment display, another shows that hyte enables; Described VGA connector 122 connects a display 30.
See also Fig. 3, this figure is the timing figure of described test chart 10, on pci bus, and when frame signal (Frame#) when becoming low level by high level, the beginning of expression pci bus cycle.At this moment, what present on the AD bus is the address (Address) of addressing that pci bus cycle is desired, and on the C/BE# bus, present be the instruction (Command).Described test chart can be decoded to this address and instruction for 10 this moments, to determine whether to belong to the 80H address, if the device of then described test chart 10 selects signal (DEVSEL#) to maintain low level as response.When the data on the AD bus (Data) be active data and IRDY# ready signal, TRDY# ready signal simultaneously when low, the data of expression pci bus are read processing by described test chart 10 at this moment.If before end cycle, when described test chart 10 can't be responded a TRDY# ready signal, main frame provided the function of a retry, promptly sent a stop signal (STOP#) by described test chart 10, and main frame can should the cycle according to the stop signal retry.
Below in conjunction with Fig. 4 and the concise and to the point groundwork flow process of describing the procedure for displaying of test chart provided by the invention of Fig. 5.In order to realize that data are shown by described display device 12, the embodiment of the invention has adopted a field programmable gate array (FPGA) 11.
S1: when frame signal (Frame#) was low level, expression PCI information transmission began.
S2: to the instruction and the address decode, judge whether to belong to the 80H address, if, next on the pci bus data to latch.If not, turn back to S1.
S3: when IRDY# ready signal and TRDY# ready signal are low level simultaneously, the data that at this time 80H address of expression comprises are effectively, with address, instruction, hyte enable, data and data that the 80H address comprised etc. are stored in one and are located in the data latching module 112 of described field programmable gate array 11.
S4: the data in the S3 data latching module 112 are changed by a data conversion module 113 of being located at described programmable gate array 11, and the display 30 that the combination 121 of the seven-segment display by described display device 12 and VGA connector 122 connect shows, wherein in the process that display 30 shows, the described data presented that needs also changes into the VGA data by a vga controller 115, is transported in the described display 30 by described VGA connector 122.
Wherein being used for the required font symbol of VGA Display data extracts from yi word pattern ROM (read-only memory) 114.Described vga controller 115 and described font ROM (read-only memory) 114 can be located in the described field programmable gate array 11, also can be located at separately outside the described field programmable gate array 11.
In the above-described embodiments, the shown information of coming out of the display that connected of described VGA connector 122 30 is more complete than described seven-segment display combination 121.
Claims (10)
1. test chart, be used to debug computer function, be plugged on the slot of a mainboard, it is characterized in that: described test chart comprises a display device and a programmable logic device (PLD), described display device comprises that one can connect the VGA connector of a display, described programmable logic device (PLD) comprises that a data latching module and that is used to latch the computer tune-up data is used to change the data conversion module of computer tune-up data, described data conversion module connects a vga controller, and described vga controller connects described VGA connector.
2. test chart as claimed in claim 1 is characterized in that: described vga controller also connects one provides font to be used for the font ROM (read-only memory) of data-switching to described vga controller.
3. test chart as claimed in claim 1 is characterized in that: described display device is provided with one and shows that the seven-segment display of computer Debugging message makes up.
4. test chart as claimed in claim 1 is characterized in that: described programmable logic device (PLD) is a field programmable gate array.
5. test chart as claimed in claim 1, it is characterized in that: described programmable logic device (PLD) comprises that also one connects the addressing functional module of the ROM (read-only memory) socket of a grafting BIOS chip, described addressing functional module is used for when the bios program of computer system damages bios program being imported, to upgrade the bios program in the computer system.
6. test chart as claimed in claim 5 is characterized in that: described addressing bios program that functional module imports is to be stored in the random access memory able to programme.
7. computer debugging method, this method comprises the following steps: at least
One programmable logic device (PLD) is provided, and described programmable logic device (PLD) comprises that a data latching module and that is used to latch the computer tune-up data is used to change the data conversion module of computer tune-up data;
Described data latching module is with effectively address, instruction, hyte enable on the pci bus, data and 80H address are comprised data storing;
Described data conversion module is changed the data that described data latching module stores;
The data that the process data conversion module is changed out by VGA connector output, show by a display after a vga controller data processing again.
8. computer debugging method as claimed in claim 7 is characterized in that: described vga controller connection one provides the font ROM (read-only memory) of font when being used for data-switching.
9. computer debugging method as claimed in claim 7, it is characterized in that: described computer debugging method also provides a ROM (read-only memory) socket that is used for device BIOS chip, when the bios program of computer system damages, bios program can import by described ROM (read-only memory) socket, bios program is transferred to computer system via described programmable logic device (PLD), is used to upgrade the bios program of computer system.
10. computer debugging method as claimed in claim 9, it is characterized in that: described bios program is stored in a random access memory able to programme, when the bios program of computer system damages, described random access memory able to programme is transferred to computer system with bios program via described programmable logic device (PLD), is used to upgrade the bios program of computer system.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA2006100634604A CN101174236A (en) | 2006-11-03 | 2006-11-03 | Debugging card and computer debugging method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA2006100634604A CN101174236A (en) | 2006-11-03 | 2006-11-03 | Debugging card and computer debugging method |
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| Publication Number | Publication Date |
|---|---|
| CN101174236A true CN101174236A (en) | 2008-05-07 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNA2006100634604A Pending CN101174236A (en) | 2006-11-03 | 2006-11-03 | Debugging card and computer debugging method |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102243601A (en) * | 2010-05-11 | 2011-11-16 | 精英电脑股份有限公司 | Debugging system and relevant method for detecting and controlling state of computer host |
| CN113341907A (en) * | 2021-04-20 | 2021-09-03 | 深圳市创智成科技股份有限公司 | System and debugging method for universal Debug card |
-
2006
- 2006-11-03 CN CNA2006100634604A patent/CN101174236A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102243601A (en) * | 2010-05-11 | 2011-11-16 | 精英电脑股份有限公司 | Debugging system and relevant method for detecting and controlling state of computer host |
| CN113341907A (en) * | 2021-04-20 | 2021-09-03 | 深圳市创智成科技股份有限公司 | System and debugging method for universal Debug card |
| CN113341907B (en) * | 2021-04-20 | 2024-04-12 | 深圳市创智成科技股份有限公司 | System and debugging method of general Debug card |
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Open date: 20080507 |