CN101174064A - LCD driving circuit, time-schedule controller and driving method thereof - Google Patents
LCD driving circuit, time-schedule controller and driving method thereof Download PDFInfo
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- CN101174064A CN101174064A CNA2007101089347A CN200710108934A CN101174064A CN 101174064 A CN101174064 A CN 101174064A CN A2007101089347 A CNA2007101089347 A CN A2007101089347A CN 200710108934 A CN200710108934 A CN 200710108934A CN 101174064 A CN101174064 A CN 101174064A
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Abstract
The invention relates to a drive circuit, a time schedule controller as well as a drive method for a liquid crystal display (LCD); wherein, the time schedule controller comprises a video data judgment circuit and a source / gate pole time schedule controller able to reduce power consumption. The video data judgment circuit is used to receive video data; if the video data are not full picture video picture, the video data judgment circuit can analyze an effective definition parameter value from the video data; if the effective data of the video data is less than the definition of the liquid crystal panel, the video data judgment circuit starts the source electrode/ gate electrode time schedule controller for lowering power consumption, which can control a plurality of gate electrode drive chips and source drive chips and reduce the times of the breakovers of the chips.
Description
Technical field
The invention relates to a kind of technical field of liquid crystal displays, refer to a kind of driving circuit, time schedule controller and driving method thereof that is applicable to Thin Film Transistor-LCD especially.
Background technology
Fig. 1 shows the synoptic diagram of the liquid crystal panel 1 of known Thin Film Transistor-LCD.The full frame resolution of supposing this liquid crystal panel 1 is 1024 * 768, so liquid crystal panel 1 is when the show image picture, a plurality of grid drive chip (the Gate Driver IC) (not shown) that is mounted on the liquid crystal panel 1 can be switched on 768 times, a plurality of source electrode chip for driving (Source DriverIC) (not shown) that is mounted on the liquid crystal panel 1 can be switched on 1024 * 3 (R, G, B) inferior.Yet if from resolution 640 * 480 of the non-full frame of resolution of the image frame that external circuit transmitted o'clock, its effective viewing area 10 as shown in Figure 1.Because the design cause of the driving circuit of known Thin Film Transistor-LCD, when liquid crystal panel 1 is 640 * 480 image frame at display resolution, described grid drive chip on the liquid crystal panel 1 still can conducting 768 times, and the described source driving chip on the liquid crystal panel 1 still can conducting 1024 times.So for noneffective display area 11, known liquid crystal panel 1 still can be controlled the grid/source driving chip relevant with this noneffective display area 11 and move, and so will cause unnecessary power dissipation.
Summary of the invention
One of purpose of the present invention provides a kind of driving circuit and driving method thereof of LCD, can reduce the power consumption of driving circuit.
Another object of the present invention provides a kind of driving circuit and driving method thereof of LCD, can reduce clock/data output number of times of delivering to driving circuit.
Another object of the present invention is that a kind of time schedule controller that is applicable to the driving circuit of a LCD is being provided, can reduce clock/data output number of times of delivering to driving circuit.
According to a technology aspect of the present invention, provide a kind of driving circuit of LCD, it is applicable to driving one liquid crystal panel, and this liquid crystal panel has complex data line and plural gate line, and this driving circuit comprises: plural source driving chip, plural grid drive chip and time schedule controller.Described source driving chip and liquid crystal panel electrically connect.Described grid drive chip also electrically connects with liquid crystal panel.Above-mentioned time schedule controller electrically connects with described source driving chip and described grid drive chip respectively, and it also comprises: the source/drain sequential control circuit of reducing power consumption and video data decision circuitry.The source/drain sequential control circuit of reducing power consumption is suitable for controlling described source driving chip and described grid drive chip, makes the number of channel that writes the data number of times and/or be less than the gate line number of this liquid crystal panel of its number of data lines by being less than this liquid crystal panel drive this liquid crystal panel.The source/drain sequential control circuit of video data decision circuitry and reducing power consumption electrically connects, its receiving video data, and analyze the effective resolution parameter value by video data, and the source/drain sequential control circuit that can start reducing power consumption is operated.
According to another technology aspect of the present invention, provide a kind of driving method of driving circuit of LCD, it is applicable to and cooperates one drive circuit to drive a liquid crystal panel, this driving circuit comprises plural source driving chip and plural grid drive chip, and this liquid crystal panel has complex data line and plural gate line, and this method comprises the steps: to receive a video data; Analyze the non-full frame resolution parameter value of this video data; And according to this non-full frame resolution parameter value, one non-full frame drive control signal/data are provided, be suitable for controlling described source driving chip and described grid drive chip, make the number of channel that writes the data number of times and/or be less than the gate line number of this liquid crystal panel of its number of data lines by being less than this liquid crystal panel drive this liquid crystal panel.
According to another technology aspect of the present invention, be to propose a kind of time schedule controller, it is applicable in the driving circuit of a LCD that this driving circuit comprises plural source driving chip and plural grid drive chip.This time schedule controller comprises: the source/drain sequential control circuit of reducing power consumption and video data decision circuitry.The source/drain sequential control circuit of reducing power consumption electrically connects with plural source driving chip and plural grid drive chip respectively.The source/drain sequential control circuit of video data decision circuitry and reducing power consumption electrically connects, and it receives a video data, and analyzes the effective resolution parameter value by video data, and the source/drain sequential control circuit that can start reducing power consumption is operated.
According to a technology aspect more of the present invention, be to propose a kind of time schedule controller, it is applicable in the driving circuit of a liquid crystal panel that this driving circuit comprises plural source driving chip and plural grid drive chip.This time schedule controller comprises: the source/drain sequential control circuit of reducing power consumption and video data decision circuitry.The source/drain sequential control circuit of reducing power consumption is suitable for controlling described source driving chip and described grid drive chip, makes the number of channel that writes the data number of times and/or be less than the gate line number of this liquid crystal panel of its number of data lines by being less than this liquid crystal panel drive this liquid crystal panel.The source/drain sequential control circuit of video data decision circuitry and reducing power consumption electrically connects, it receives a video data, and analyze the effective resolution parameter value, and can start the source/drain sequential control circuit of this reducing power consumption according to this effective resolution parameter value by video data.
Above-mentioned video data decision circuitry judges whether video data is full frame data, if video data is not the full frame data, then the video data decision circuitry analyzes this effective resolution parameter value by video data.
In addition, whether video data decision circuitry and the effective resolution of judging video data be less than the resolution of liquid crystal panel, if the effective resolution of video data is less than the resolution of liquid crystal panel, then the video data decision circuitry starts the source/drain sequential control circuit of reducing power consumption.That is, the video data decision circuitry is sent the source/drain sequential control circuit of effective resolution parameter value to this reducing power consumption, make the source/drain sequential control circuit of reducing power consumption produce non-full frame drive control signal/data and a new data time sequence, to control the running of described grid drive chip and described source driving chip according to the effective resolution parameter value.
Above-mentioned video data decision circuitry starts the source/drain sequential control circuit of this reducing power consumption, controls described grid drive chip and described source driving chip reduces its conducting number of times for the source/drain sequential control circuit of this reducing power consumption.
Time schedule controller also comprises the source/drain sequential control circuit, when video data is the full frame video data, video data decision circuitry startup source/drain sequential control circuit makes the source/drain sequential control circuit control described source driving chip and described grid drive chip is carried out normal running.
Time schedule controller also comprises low frequency full frame Drive and Control Circuit, and low frequency full frame Drive and Control Circuit includes the polarity decision circuitry, the polarity of the non-full frame drive control signal/data that provided with the source/drain sequential control circuit of judging reducing power consumption.In addition, low frequency full frame Drive and Control Circuit electrically connects with the source/drain sequential control circuit of video data decision circuitry, reducing power consumption, described source driving chip and described grid drive chip respectively.
The video data decision circuitry starts after the source/drain sequential control circuit of reducing power consumption, low frequency full frame Drive and Control Circuit timing one Preset Time, low frequency full frame Drive and Control Circuit output full frame drive control signal/data are to described source driving chip and described grid drive chip then.In addition, the video data decision circuitry continue to start the source/drain sequential control circuit of this reducing power consumption, up to the timing of low frequency full frame Drive and Control Circuit till the Preset Time.
Description of drawings
Fig. 1 is the synoptic diagram of the liquid crystal panel module of known Thin Film Transistor-LCD.
Fig. 2 is the functional block diagram of the liquid crystal panel module of a preferred embodiment of the present invention.
Fig. 3 is the built-in function calcspar of the time schedule controller of a preferred embodiment of the present invention.
Fig. 4 is the action flow chart of a preferred embodiment of the present invention.
Fig. 5 is the process flow diagram of the low frequency full frame driving mechanism of a preferred embodiment of the present invention.
Fig. 6 A, Fig. 6 B are the operating clock synoptic diagram of known source driving chip.
Fig. 7 A, Fig. 7 B are the operating clock synoptic diagram of the source driving chip of a preferred embodiment of the present invention.
Fig. 8 is the operating clock synoptic diagram of known grid drive chip.
Fig. 9 is the operating clock synoptic diagram of the grid drive chip of a preferred embodiment of the present invention.
Symbol description:
1,24 liquid crystal panel
10 effective viewing areas
11 noneffective display areas
2 panel modules
21 time schedule controllers
211 video data decision circuitry
2111 thread counts
2112 comparers
The source/drain sequential control circuit of 212 reducing power consumptions
213 source/drain sequential control circuits
214 low frequency full frame Drive and Control Circuit
2141 timers
2142 polarity decision circuitry
221,222,223 source driving chips
231,232,233 grid drive chip
S405, S410, S415, S420, S425, S430, S435, S505, S510, S515, S520, S530 step
Embodiment
Relevant preferred embodiment of the present invention please be with reference to Fig. 2～Fig. 5.Fig. 2 shows the functional block diagram of the panel module 2 of preferred embodiment of the present invention, and it is to comprise time schedule controller (TCON) 21, plural source driving chip 221,222,223, plural grid drive chip 231,232,233 and liquid crystal panel 24.
Above-mentioned time schedule controller 21 respectively with described source driving chip 221,222,223 and described grid drive chip 231,232,233 electrically connect, and can control described source driving chip 221 for time schedule controller 21,222,223 and the running of described grid drive chip 231,232,233.Described source driving chip 221,222,223 and described grid drive chip 231,232,233 all electrically connect with liquid crystal panel 24.
The built-in function calcspar of the further display timing generator controller 21 of Fig. 3, it is source/drain sequential control circuit 212, source/drain sequential control circuit 213 and the low frequency full frame Drive and Control Circuit 214 that comprises video data decision circuitry 211, reducing power consumption, wherein video data decision circuitry 211 also comprises thread count (Line Counter) 2111 and comparer 2112, and low frequency full frame Drive and Control Circuit 214 also comprises timer 2141 and polarity decision circuitry 2142.
Above-mentioned video data decision circuitry 211 electrically connects with the source/drain sequential control circuit 212 of reducing power consumption, source/drain sequential control circuit 213 and low frequency full frame Drive and Control Circuit 214 respectively.The source/drain sequential control circuit 212 of reducing power consumption electrically connects with described grid drive chip 231,232,233 and described source driving chip 221,222,223 respectively.Source/drain sequential control circuit 213 electrically connects with described grid drive chip 231,232,233 and described source driving chip 221,222,223 respectively.Low frequency full frame Drive and Control Circuit 214 electrically connects with the source/drain sequential control circuit 212 of reducing power consumption, described grid drive chip 231,232,233 and described source driving chip 221,222,223 respectively.
In addition, the source/drain sequential control circuit 212 of the reducing power consumption of aforesaid time schedule controller 21 is suitable for controlling described grid drive chip 231,232,233 and described source driving chip 221,222,223 start makes the number of channel that writes the data number of times and/or be less than the gate line number of liquid crystal panel 24 of their number of data lines by being less than liquid crystal panel 24 drive this liquid crystal panel 24.On the other hand, data decision circuitry 211 receives a video data (not shown), and from then on the video data (not shown) analyzes an effective resolution parameter value, starts the source/drain sequential control circuit 212 of reducing power consumption again according to this effective resolution parameter value.As for detailed start-up course, after will being described in.
Fig. 4 shows the start process flow diagram of preferred embodiment of the present invention, and relevant its explanation please be in the lump with reference to Fig. 2 and Fig. 3.At first, video data decision circuitry 211 receives the video data and the synchronizing signal (step S405) of outside input.Then, whether 211 pairs of video datas of video data decision circuitry are judged, be full frame video data (step S410) to judge video data.
In present embodiment, video data decision circuitry 211 is that the video data (R, G, B) in data valid period (Data Enable) to a sliver carries out pointwise and judges, if the video data value of this line is 0 (value of R, G, B every bit is 0), represent that then the image frame that this line is sent is the black picture.Whereby, video data decision circuitry 211 just can (for example: the DVD film be judged some video data by above-mentioned means, it is all the black picture in two ends up and down, middle be image frame) several black pictures are arranged in the whole image frame (Frame) sent, and judge sliver be the black picture position institute wherein.In addition, in this way, video data decision circuitry 211 can be learnt in the present whole image frame, at a vertical synchronizing signal (V
Sync) time in the valid data line number sent, that is video data decision circuitry 211 can be found out valid data line number in a whole image frame.
If this video data is judged as the full frame video data, then video data decision circuitry 211 starts source/drain sequential control circuit 213, make source/drain sequential control circuit 213 control described grid drive chip 231,232,233 and described source driving chip 221 carry out normal operation (step S415).
If this video data is judged as non-full frame video data, then video data decision circuitry 211 analyzes the effective resolution parameter value of video data by video data, for example: valid data line number/columns (step S420).Whether in addition, video data decision circuitry 211 also can continue video data is analyzed, till a default value, fixing with the effective resolution parameter value of confirming video data.
For example: whether video data decision circuitry 211 is carried out the pointwise judgement to each bar line, be valid data to judge this line.If sliver is the black picture, then represent this line may be non-valid data.If this sliver is not all to be the black picture, then represent this line may be valid data.In addition, video data decision circuitry 211 more can write down the non-valid data line number that it is judged by thread count 2111.For example: for the image frame of this class of DVD, video data decision circuitry 211 is by the line number of the non-valid data in upper end black picture and the lower end black picture in the thread count 2111 recording image pictures, then video data decision circuitry 211 is handled by comparer 2112, to obtain the valid data line number in a whole image frame.If through behind a plurality of image frames, the number of the valid data line of described image frame is all identical, the effective resolution parameter value of then representing the DVD film to be sent is fixing, and the quantity of wherein said image frame equals this default value.
Then, video data decision circuitry 211 judges that effective resolution is whether less than the resolution (step S425) of liquid crystal panel 24.If the effective resolution in the video data is less than the resolution of liquid crystal panel 24, then video data decision circuitry 211 starts the source/drain sequential control circuit 212 of reducing power consumption, make the source/drain sequential control circuit 212 of reducing power consumption control described grid drive chip 231,232,233 reduce its conducting number of times with described source driving chip 221,222,223, with the power dissipation of reduction driving circuit, and also can reduce clock/data output number of times (step S430) of delivering to driving circuit.
For example: effective resolution is during less than the resolution of liquid crystal panel 24, video data decision circuitry 211 is sent the source/drain sequential control circuit 212 of effective resolution parameter value to reducing power consumption, make the source/drain sequential control circuit 212 of reducing power consumption produce non-full frame drive control signal/data and a new data time sequence according to this effective resolution parameter value, for described grid drive chip 231,232,233 and described source driving chip 221,222,223 operate according to these non-full frame drive control signal/data and new data time sequence.
If the effective resolution parameter value that video data decision circuitry 211 is provided is 640 * 480, and the resolution of liquid crystal panel 24 is 1024 * 768, then the source/drain sequential control circuit 212 of reducing power consumption is sent N+480 grid control signal to described grid drive chip 231,232,233, and the source/drain sequential control circuit 212 of reducing power consumption is sent M * 3+640 * 3 source control signal, wherein N is the start line number of effective viewing area, and M counts the initial of effective viewing area.
If the effective resolution in the video data is greater than the resolution of liquid crystal panel 24, then video data decision circuitry 211 starts source/drain time schedule controller 213, to control described grid drive chip 231,232,233 and described source driving chip 221 carries out normal operation (step S435).
Because the liquid crystal molecule in the liquid crystal panel 24 can't bear DC voltage for a long time, so after video data decision circuitry 211 starts the source/drain sequential control circuit 212 of reducing power consumption, liquid crystal molecule in the non-display area of liquid crystal panel 24 must carry out voltage to be upgraded, to avoid deterioration.Therefore, the present invention also provides a low frequency full frame driving mechanism, with the liquid crystal molecule deterioration in the non-display area of avoiding liquid crystal panel 24.
Fig. 5 shows the process flow diagram of low frequency full frame driving mechanism, and relevant its explanation please be in the lump with reference to Fig. 2 and Fig. 3.After video data decision circuitry 211 starts the source/drain sequential control circuit 212 of reducing power consumption, 214 runnings of video data decision circuitry 211 control low frequency full frame Drive and Control Circuit.At first, the timer 2141 of low frequency full frame Drive and Control Circuit 214 pick up counting (step S505).Then, low frequency full frame Drive and Control Circuit 214 is judged timer 2141, and whether timing is to a Preset Time (step S510), if timing is not to Preset Time as yet for timer 2141, then video data decision circuitry 211 continues the running (step S515) of the source/drain sequential control circuit 212 of control reducing power consumption.If timer 2141 timing are to Preset Time, then low frequency full frame Drive and Control Circuit 214 begins to send full frame drive control signal/data to described grid drive chip 231,232,233 and described source driving chip 221,222,223, keep liquid crystal molecule charge/discharge (step S520) to carry out low-frequency voltage renewal work.
Certainly, before low frequency full frame Drive and Control Circuit 214 is sent full frame drive control signal/data, polarity decision circuitry 2142 must be judged the polarity of non-full frame drive control signal/data that the source/drain sequential control circuit 212 of reducing power consumption is provided earlier, when avoiding source/drain sequential control circuit 212 by reducing power consumption to switch to low frequency full frame Drive and Control Circuit 214, transmit the full frame drive control signal/data with wrong polarity produce the image flicker to liquid crystal molecule situation.Therefore, the polarity decision circuitry 2142 of low frequency full frame Drive and Control Circuit 214 is judged the polarity of non-full frame drive control signal/data that the source/drain sequential control circuit 212 of reducing power consumption provided earlier, then low frequency full frame Drive and Control Circuit 214 is exported full frame drive control signal/data again to described grid drive chip 231,232,233 and described source driving chip 221,222,223.
Low frequency full frame Drive and Control Circuit 214 is sent after full frame drive control signal/data, and timer 2141 is made zero, and lays equal stress on the New count time (step S530).
In order further to understand not existing together of the present invention and known technology, please be with reference to Fig. 6 A～Fig. 9, wherein Fig. 6 A, Fig. 6 B show the operating clock synoptic diagram of known source driving chip, Fig. 7 A, Fig. 7 B show the operating clock synoptic diagram of the source driving chip of preferred embodiment of the present invention, Fig. 8 shows the operating clock synoptic diagram of known grid drive chip, and Fig. 9 shows the operating clock synoptic diagram of the grid drive chip of preferred embodiment of the present invention.
In Fig. 6 A, if the resolution of liquid crystal panel is 1024 * 768, then no matter the effective resolution of video data is why, the initial pulse of known source driving chip always just begins to send at the 1st point of liquid crystal panel, and known source driving chip begins input by the 1st point and writes data (R, G, B), just export up to the 1024th point and to write data, to convert corresponding current potential to.Shown in Fig. 6 B, concerning whole image frame, need output to write data 768 times.
Relatively, in Fig. 7 A, if the resolution of liquid crystal panel is 1024 * 768, and the effective resolution of video data is 640 * 480 o'clock, then the initial pulse wave of the source driving chip that present embodiment provided up to the starting point of effective viewing area of liquid crystal panel (for example: the 193rd point) just begin to send, and begin input by the 193rd and write data (R, G, B), just export up to the 832nd and write data, to convert corresponding current potential to.And shown in Fig. 7 B, concerning whole image frame, only need export and write data 480 times.Therefore, in fact source driving chip lacks than 1024 * 3 channel (Channel) number that liquid crystal panel drove, that is known source driving chip is 1024 * 3 to channel (Channel) number that liquid crystal panel drove, and the source driving chip of present embodiment in fact to channel (Channel) number that liquid crystal panel drove less than 1024 * 3.
Similarly, in Fig. 8, if the resolution of liquid crystal panel is 1024 * 768, then no matter the effective resolution of video data is why, known grid drive chip is still sent grid control signal (GateClock) by article one line, therefore need send 768 grid control signals (Gate Clock), that is grid drive chip needs conducting (Turn On) 768 times.In addition, for known grid drive chip, (Output Enable OE) is electronegative potential to output enable signal forever.
Relatively, in Fig. 9, if the resolution of liquid crystal panel is 1024 * 768, and when the effective resolution of video data is 640 * 480, then the output enable signal of the grid drive chip that present embodiment provided is the effective resolution variation with video data, for example: only when 624 lines of the 145th line to the, its accurate position just is an electronegative potential to output enable signal.Therefore, for grid drive chip, only need to send grid control signal at the 145th～624 line.So in fact grid drive chip is lacked than 768 channel (Channel) number that liquid crystal panel drove.Because the conducting number of times of the gate/source chip for driving that present embodiment provided lacks than known gate/source chip for driving, therefore can reduce the power dissipation of driving circuit really, and also can reduce clock/data output number of times of delivering to driving circuit.
By above explanation as can be known, the time sequence controller grid utmost point/source driving chip provided by the present invention is only sent the necessary control signal to effective viewing area, and does not need whole image output control signal, to reach the power dissipation that significantly reduces driving circuit.
In addition, the time sequence controller grid utmost point/source driving chip provided by the present invention is only sent the necessary control signal to effective viewing area, and do not need whole image output control signal, significantly to reduce clock/data output number of times of delivering to source driving chip and grid drive chip.
The foregoing description only is to give an example for convenience of description, and the interest field that the present invention advocated should be as the criterion so that claim is described certainly, but not only limits to the foregoing description.
Claims (42)
1. the driving circuit of a LCD is applicable to drive a liquid crystal panel, and this liquid crystal panel has complex data line and plural gate line, and this driving circuit comprises:
The plural number source driving chip electrically connects with this liquid crystal panel;
The plural number grid drive chip electrically connects with this liquid crystal panel; And
Time schedule controller electrically connects with described source driving chip and described grid drive chip respectively, and this time schedule controller comprises:
The source/drain sequential control circuit of one reducing power consumption, be suitable for controlling described source driving chip and described grid drive chip, make the number of channel that writes the data number of times and/or be less than the gate line number of this liquid crystal panel of its number of data lines by being less than this liquid crystal panel drive this liquid crystal panel; And
One video data decision circuitry, electrically connect with the source/drain sequential control circuit of this reducing power consumption, it receives a video data, and analyze an effective resolution parameter value, and can start the source/drain sequential control circuit of this reducing power consumption according to this effective resolution parameter value by this video data.
2. driving circuit as claimed in claim 1, wherein this video data decision circuitry is suitable for judging that this video data is non-full frame data.
3. driving circuit as claimed in claim 1, wherein this video data decision circuitry is suitable for judging the resolution of the effective resolution of this video data less than this liquid crystal panel.
4. driving circuit as claimed in claim 1, wherein this video data decision circuitry is suitable for this effective resolution parameter value is sent to the source/drain sequential control circuit of this reducing power consumption, make the source/drain sequential control circuit of this reducing power consumption produce non-full frame drive control signal/data and a data time sequence, to control the running of described grid drive chip and described source driving chip according to this effective resolution parameter value.
5. driving circuit as claimed in claim 4, wherein this time schedule controller also comprises a low frequency full frame Drive and Control Circuit, this low frequency full frame Drive and Control Circuit comprises a polarity decision circuitry, and it is suitable for judging the polarity of non-full frame drive control signal/data that the source/drain sequential control circuit of this reducing power consumption is provided.
6. driving circuit as claimed in claim 5, wherein this time schedule controller also comprises a low frequency full frame Drive and Control Circuit, this low frequency full frame Drive and Control Circuit comprises a timer, it is suitable for timing one Preset Time, then this low frequency full frame Drive and Control Circuit is exported a full frame driving data to described source driving chip and described grid drive chip, keeps liquid crystal molecule charge/discharge in this liquid crystal panel to carry out low-frequency voltage renewal work.
7. driving circuit as claimed in claim 1, wherein this video data decision circuitry starts the source/drain sequential control circuit of this reducing power consumption, controls described grid drive chip and described source driving chip reduces its conducting number of times for the source/drain sequential control circuit of this reducing power consumption.
8. driving circuit as claimed in claim 1, wherein this time schedule controller also comprises one source pole/grid sequential control circuit, and when this video data is a full frame video data, this video data decision circuitry is suitable for starting this source/drain sequential control circuit, makes this source/drain sequential control circuit control the running of described source driving chip and described grid drive chip.
9. driving circuit as claimed in claim 1, wherein this time schedule controller also comprises a low frequency full frame Drive and Control Circuit, and this low frequency full frame Drive and Control Circuit electrically connects with the source/drain sequential control circuit of this video data decision circuitry, this reducing power consumption, described source driving chip and described grid drive chip respectively.
10. driving circuit as claimed in claim 1, wherein this time schedule controller also comprises a low frequency full frame Drive and Control Circuit, this low frequency full frame Drive and Control Circuit comprises a timer, it is suitable for timing one Preset Time, this low frequency full frame Drive and Control Circuit is exported full frame drive control signal/data to described source driving chip and described grid drive chip, till this Preset Time finishes.
11. driving circuit as claimed in claim 1, wherein this video data decision circuitry comprises a thread count, and this video data decision circuitry is to write down the non-valid data line number that it is judged at this video data by this thread count.
12. driving circuit as claimed in claim 11, wherein this video data decision circuitry also comprises a comparer, and this video data decision circuitry obtains the valid data line number in the image frame of this video data by this comparer.
13. the driving method of a LCD, be applicable to and cooperate one drive circuit to drive a liquid crystal panel, this driving circuit comprises plural source driving chip and plural grid drive chip, and this liquid crystal panel has complex data line and plural gate line, and this method comprises the steps:
Receive a video data;
Analyze the non-full frame resolution parameter value of this video data; And
According to this non-full frame resolution parameter value, one non-full frame drive control signal/data are provided, be suitable for controlling described source driving chip and described grid drive chip, make the number of channel that writes the data number of times and/or be less than the gate line number of this liquid crystal panel of its number of data lines by being less than this liquid crystal panel drive this liquid crystal panel.
14. method as claimed in claim 13, wherein this method also comprises the steps: after receiving this video data
Analyze the full frame resolution parameter value of this video data; And
According to this full frame resolution parameter value, one full frame drive control signal/data are provided, be suitable for controlling described source driving chip and described grid drive chip, make the number of channel that writes the data number of times and equal the gate line number of this liquid crystal panel of its number of data lines by equaling this liquid crystal panel drive this liquid crystal panel.
15. method as claimed in claim 13, wherein this method also comprises the steps: after the running of using this described source driving chip of non-full frame drive control signal/Data Control and described grid drive chip
Provide full frame drive control signal/data to described source driving chip and described grid drive chip, to control described source driving chip and described grid drive chip, make it carry out the liquid crystal molecule charge/discharge that this liquid crystal panel is kept in low-frequency voltage renewal work.
16. method as claimed in claim 15, wherein this method also comprises the steps:
Providing these full frame drive control signal/data to described source driving chip and the described grid drive chip, select the polarity of these full frame drive control signal/data, so that can not produce the situation that image glimmers on this liquid crystal panel.
17. method as claimed in claim 13, wherein this method is in the step of the running of using this described source driving chip of non-full frame drive control signal/Data Control and described grid drive chip, the source/drain sequential control circuit of one reducing power consumption is activated, and a low frequency full frame Drive and Control Circuit timing one Preset Time, this low frequency full frame Drive and Control Circuit is exported full frame drive control signal/data to described source driving chip and described grid drive chip then.
18. method as claimed in claim 17, when wherein timing was not to this Preset Time as if this low frequency full frame Drive and Control Circuit, a video data decision circuitry then continued to start the source/drain sequential control circuit of this reducing power consumption.
19. method as claimed in claim 17, wherein this low frequency full frame Drive and Control Circuit also includes a polarity decision circuitry, the polarity of the full frame drive control signal/data that provided with the source/drain sequential control circuit of judging this reducing power consumption.
20. method as claimed in claim 13, wherein this method is controlled in the step of running of described source driving chip and described grid drive chip in using this non-full frame drive control signal/data controlling signal, the source/drain sequential control circuit of this reducing power consumption produces this non-full frame drive control signal/data and a data time sequence according to this effective resolution parameter value, to control the running of described grid drive chip and described source driving chip.
21. method as claimed in claim 13, wherein this method also comprises the steps: after receiving this video data
If this video data is a full frame video data, then start one source pole/grid sequential control circuit and control the running of described source driving chip and described grid drive chip, make the number of channel that writes the data number of times and equal the gate line number of this liquid crystal panel of its number of data lines by equaling this liquid crystal panel drive this liquid crystal panel.
22. a time schedule controller is applicable in the driving circuit of a LCD, comprising:
The source/drain sequential control circuit of one reducing power consumption electrically connects with plural source driving chip and plural grid drive chip respectively; And
One video data decision circuitry, be connected with the source/drain sequential control circuit of this reducing power consumption, it receives a video data, and analyzes an effective resolution parameter value by this video data, and the source/drain sequential control circuit that can start this reducing power consumption is operated.
23. time schedule controller as claimed in claim 22, wherein this video data decision circuitry is suitable for judging the effective resolution of this video data, and if the effective resolution of this video data is less than the resolution of this liquid crystal panel, this video data decision circuitry then starts the source/drain sequential control circuit of this reducing power consumption.
24. time schedule controller as claimed in claim 22, wherein this video data decision circuitry is suitable for this effective resolution parameter value is sent to the source/drain sequential control circuit of this reducing power consumption, make the source/drain sequential control circuit of this reducing power consumption produce non-full frame drive control signal/data and a data time sequence, to control the running of described grid drive chip and described source driving chip according to this effective resolution parameter value.
25. time schedule controller as claimed in claim 22, wherein this video data decision circuitry starts the source/drain sequential control circuit of this reducing power consumption, controls described grid drive chip and described source driving chip reduces its conducting number of times for the source/drain sequential control circuit of this reducing power consumption.
26. time schedule controller as claimed in claim 22, wherein this time schedule controller also comprises one source pole/grid sequential control circuit, and when this video data is a full frame video data, this video data decision circuitry is suitable for starting this source/drain sequential control circuit, makes this source/drain sequential control circuit control the running of described source driving chip and described grid drive chip.
27. time schedule controller as claimed in claim 22, wherein this time schedule controller also comprises a low frequency full frame Drive and Control Circuit, this low frequency full frame Drive and Control Circuit includes a polarity decision circuitry, and it is suitable for judging the polarity of non-full frame drive control signal/data that the source/drain sequential control circuit of this reducing power consumption is provided.
28. time schedule controller as claimed in claim 22, wherein this time schedule controller also comprises a low frequency full frame Drive and Control Circuit, and this low frequency full frame Drive and Control Circuit electrically connects with the source/drain sequential control circuit of this video data decision circuitry, this reducing power consumption, described source driving chip and described grid drive chip respectively.
29. time schedule controller as claimed in claim 28, after wherein the source/drain sequential control circuit of this reducing power consumption is activated, this low frequency full frame Drive and Control Circuit timing one Preset Time, this low frequency full frame Drive and Control Circuit is exported full frame drive control signal/data to described source driving chip and described grid drive chip then.
30. time schedule controller as claimed in claim 29, wherein timing is not to this Preset Time for this low frequency full frame Drive and Control Circuit, and this video data decision circuitry continues to start the source/drain sequential control circuit of this reducing power consumption.
31. a time schedule controller is applicable to that one is suitable for driving in the driving circuit of a liquid crystal panel, this driving circuit comprises plural source driving chip and plural grid drive chip, and this time schedule controller comprises:
The source/drain sequential control circuit of one reducing power consumption, be suitable for controlling described source driving chip and described grid drive chip, make the number of channel that writes the data number of times and/or be less than the gate line number of this liquid crystal panel of its number of data lines by being less than this liquid crystal panel drive this liquid crystal panel; And
One video data decision circuitry, electrically connect with the source/drain sequential control circuit of this reducing power consumption, it receives a video data, and analyze an effective resolution parameter value, and can start the source/drain sequential control circuit of this reducing power consumption according to this effective resolution parameter value by this video data.
32. time schedule controller as claimed in claim 31, wherein this video data decision circuitry is suitable for judging that this video data is non-full frame data.
33. time schedule controller as claimed in claim 31, wherein this video data decision circuitry is suitable for judging the resolution of the effective resolution of this video data less than this liquid crystal panel.
34. time schedule controller as claimed in claim 31, wherein this video data decision circuitry is suitable for this effective resolution parameter value is sent to the source/drain sequential control circuit of this reducing power consumption, make the source/drain sequential control circuit of this reducing power consumption produce non-full frame drive control signal/data and a data time sequence, to control the running of described grid drive chip and described source driving chip according to this effective resolution parameter value.
35. time schedule controller as claimed in claim 34, also comprise a low frequency full frame Drive and Control Circuit, this low frequency full frame Drive and Control Circuit comprises a polarity decision circuitry, and it is suitable for judging the polarity of non-full frame drive control signal/data that the source/drain sequential control circuit of this reducing power consumption is provided.
36. time schedule controller as claimed in claim 35, also comprise a low frequency full frame Drive and Control Circuit, this low frequency full frame Drive and Control Circuit comprises a timer, it is suitable for timing one Preset Time, and this low frequency full frame Drive and Control Circuit is exported full frame drive control signal/data to described source driving chip and described grid drive chip then.
37. time schedule controller as claimed in claim 31, also comprise one source pole/grid sequential control circuit, and when this video data is a full frame video data, this video data decision circuitry is suitable for starting this source/drain sequential control circuit, makes this source/drain sequential control circuit control the running of described source driving chip and described grid drive chip.
38. time schedule controller as claimed in claim 31, also comprise a low frequency full frame Drive and Control Circuit, it is suitable for sending full frame drive control signal/data to described grid drive chip and described source driving chip, keeps liquid crystal molecule charge/discharge in this liquid crystal panel to carry out low-frequency voltage renewal work.
39. time schedule controller as claimed in claim 31, also comprise a low frequency full frame Drive and Control Circuit, electrically connect with the source/drain sequential control circuit of this video data decision circuitry, this reducing power consumption, described source driving chip and described grid drive chip respectively.
40. time schedule controller as claimed in claim 31, also comprise a low frequency full frame Drive and Control Circuit, this low frequency full frame Drive and Control Circuit comprises a timer, it is suitable for timing one Preset Time, this low frequency full frame Drive and Control Circuit is exported full frame drive control signal/data to described source driving chip and described grid drive chip, till this Preset Time finishes.
41. time schedule controller as claimed in claim 31, wherein this video data decision circuitry comprises a thread count, and this video data decision circuitry is to write down the non-valid data line number that it is judged at this video data by this thread count.
42. time schedule controller as claimed in claim 41, wherein this video data decision circuitry also comprises a comparer, and this video data decision circuitry obtains the valid data line number in the image frame of this video data by this comparer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2007101089347A CN101174064B (en) | 2006-06-08 | 2007-06-07 | LCD driving circuit, time-schedule controller and driving method thereof |
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200610087953 CN1866086A (en) | 2006-06-08 | 2006-06-08 | Drive circuit of thin film transistor liquid display and power consumption decreasing method |
| CN200610087953.1 | 2006-06-08 | ||
| CN2007101089347A CN101174064B (en) | 2006-06-08 | 2007-06-07 | LCD driving circuit, time-schedule controller and driving method thereof |
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| CN101174064A true CN101174064A (en) | 2008-05-07 |
| CN101174064B CN101174064B (en) | 2010-06-02 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN2007101089347A Expired - Fee Related CN101174064B (en) | 2006-06-08 | 2007-06-07 | LCD driving circuit, time-schedule controller and driving method thereof |
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| CN (1) | CN101174064B (en) |
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| CN101976553A (en) * | 2010-11-04 | 2011-02-16 | 华映视讯（吴江）有限公司 | Liquid crystal drive device and method for improving starting-up delay, and time sequence control circuit |
| CN101976554A (en) * | 2010-11-04 | 2011-02-16 | 华映视讯（吴江）有限公司 | Liquid crystal driving device and sequential control circuit and method for improving startup delay |
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| JP5019668B2 (en) * | 2000-09-18 | 2012-09-05 | 三洋電機株式会社 | Display device and control method thereof |
| KR100496545B1 (en) * | 2002-12-26 | 2005-06-22 | 엘지.필립스 엘시디 주식회사 | Connector And Apparatus Of Driving Liquid Crystal Display Using The Same |
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| CN101976553A (en) * | 2010-11-04 | 2011-02-16 | 华映视讯（吴江）有限公司 | Liquid crystal drive device and method for improving starting-up delay, and time sequence control circuit |
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