CN101170296A - Self interference resisting electromotor excitation controller with dual central processor and its control method - Google Patents
Self interference resisting electromotor excitation controller with dual central processor and its control method Download PDFInfo
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- CN101170296A CN101170296A CNA2007101506843A CN200710150684A CN101170296A CN 101170296 A CN101170296 A CN 101170296A CN A2007101506843 A CNA2007101506843 A CN A2007101506843A CN 200710150684 A CN200710150684 A CN 200710150684A CN 101170296 A CN101170296 A CN 101170296A
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Abstract
The invention discloses a self-immunity generator excitation controller with dual central processors as well as a control method thereof. The controller comprises: a data acquisition module, a central process circuit and a power output circuit. The control method includes the following stages: (1) acquiring a signal; (2) amplifying and shaping the signal to make the signal acceptable; (3) acquiring real-time data; (4) implementing a self-immunity algorithm; (5) generating the signal; (6) generating excitation current. The invention has the advantages that: the method can fulfill the self-immunity control rules in the generator excitation; the whole system has higher speed, higher accuracy, more perfect robustness control effects and higher reliability, so as to lower control lagging caused by process speed limit via an ordinary single chip microcomputer with perfect regulation performance. Therefore, the invention can lower external disturbance influences on the normal operation of the power system and improve dynamic performance of generators.
Description
Technical field
What the present invention relates to is electric power system generator excitation control technology, particularly be active disturbance rejection excitation controller and control method thereof with two central processing units.
Background technology
Exciter control system is one of main device of stable power system.Along with the progress of control theory, various advanced persons' control law has appearred in succession.This hardware to the controller internal control circuit is had higher requirement.Auto-disturbance rejection technology is a kind of advanced person's a control strategy, and its amount of calculation is much bigger compared with present various control laws.We can say that can automatic disturbance rejection controller reach pre-determined characteristics, be decided by that can the processor of controller internal control circuit finish the lot of data Processing tasks in finite time.This high real-time, reliability and the jumbo calculation task of requiring is a sizable challenge to traditional uniprocessor control framework.If control circuit only relies on the speed that adopts high end chip to improve processor, not only improved the cost of product but also brought the software complexity problem.
Extended state observer in the Auto Disturbances Rejection Control Technique requires in the input signal cycle on the other hand, and the software module of extended state observer is calculated and repeatedly reached requirement up to tracking accuracy.The uniprocessor framework is difficult to be competent in the prior art.
Summary of the invention
The objective of the invention is to overcome the deficiencies in the prior art, provide a kind of in conjunction with high performance signal processor and advanced control theory, that adopts two central processing unit frameworks has two central processing unit self interference resisting electromotor excitation controllers and a control method thereof.
Technical scheme of the present invention is:
A kind of active disturbance rejection excitation controller with two central processing units, described active disturbance rejection excitation controller with two central processing units comprises: data acquisition module, central processing circuit, power output circuit; The input of described data acquisition module connects voltage transformer summation current transformer output, and the output of data acquisition module is connected with the input of the central processing circuit of two central processing units; The output of central processing circuit connects the input of power output circuit; The output of power output circuit connects the generator excitation winding; Described voltage transformer summation current transformer input connects electrical network.
A kind of control method with two central processing unit self interference resisting electromotor excitation controllers, described control method comprised with the next stage:
(2). signal acquisition stage: voltage transformer, current transformer are gathered voltage, electric current, the frequency signal of electrical network;
(2). with acquired signal amplify, shaping and be transformed to the signal phase of acceptance: above-mentioned collection voltage, electric current, frequency signal are converted to the acceptable corresponding signal than low amplitude value of central processing circuit by the signal pre-processing circuit of data acquisition module;
(3). obtain the real time data stage of system: central processing unit 1 is carried out active disturbance rejection algoritic module image data; A D adopt the inquiry working method, behind EOC, voltage, electric current, the frequency signal that collects carried out digital filtering; By calculating power, voltage, frequency, merit angle signal, and be saved in the double-port RAM.
(4). the implementation phase of active disturbance rejection algorithm: central processing unit 1 is cycle calculations in a control signal output cycle of whole excitation controller, up to the input signal of extended state observer and the error between the single order output signal less than set point; After the extended state observer computing was finished, central processing unit 1 was saved in disturbed value inside and outside the system that estimates in the double-port RAM, and finished signal to calculating of central processing unit 2 transmissions; Above process is finished by the active disturbance rejection algoritic module;
(5). the generation phase of control signal: after signal is finished in the calculating that central processing unit 2 obtains central processing unit 1, the output signal value of read-out power, voltage, frequency, merit angle, extended state observer from double-port RAM; According to active disturbance rejection excitation control law it is carried out simple plus and minus calculation and draw control signal, output to power output circuit;
(6). the exciting current generation phase: power output circuit amplifies control signal, outputs to the gated transistor rectification circuit and produces exciting current.
The invention has the beneficial effects as follows: excitation control controller of the present invention relies on advanced non-linear Auto Disturbances Rejection Control Technique, utilizes the high performance digital signal process chip to realize the Active Disturbance Rejection Control rule of generator excitation.Adopt two central processing unit frameworks, but calculate and control concurrent working basically, whole system has fast, high accuracy, high robust control effect and bigger reliability, has reduced because common single-chip microcomputer processing speed limits the control hysteresis that causes, has good adjusting function.This excitation control control system can be strengthened the stability and the fail safe of electrical network, is a kind of generator excitation control device of new generation with very big market prospect.The present invention utilizes Auto Disturbances Rejection Control Technique can eliminate the interference that model inaccuracy and external disturbance cause automatically, thereby reduces the influence of external disturbance to the normal operation of electric power system, has improved the dynamic property of generator.
Description of drawings
Fig. 1 is that excitation controller circuit of the present invention connects block diagram;
Fig. 2 a is that the signal pre-processing circuit in Fig. 1 data acquisition module connects block diagram;
Fig. 2 b is that the frequency measurement circuit in Fig. 1 data acquisition module connects block diagram;
Fig. 3 is that Fig. 1 central processing circuit connects block diagram;
Fig. 4 is that power output circuit connects block diagram among Fig. 1;
" figure number explanation "
1: control circuit 2: data acquisition module 3: central processing circuit
4: power output circuit 11: generator excitation winding 15a: voltage transformer
15b: current transformer 21: signal pre-processing circuit 211: analog quantity pre-process circuit
212: switching value pre-process circuit 213: protective relaying device 22: frequency measurement circuit
223: frequency measurement circuit 224: optical coupling isolator 225: the incident capture module
31: central processing unit 2 32: central processing unit 1 33: double-port RAM
34: synchronizing sequential circuit 35: communication bus 41: phase-shift pulse forms circuit
42: pulse modulation amplifying circuit 43: the gated transistor rectification circuit
Embodiment
Below in conjunction with accompanying drawing embodiments of the invention are described in detail.
Fig. 1 is that excitation controller circuit of the present invention connects block diagram.
As shown in Figure 1, the invention provides a kind of active disturbance rejection excitation controller with two central processing units, described active disturbance rejection excitation controller 1 with two central processing units comprises: data acquisition module 2, central processing circuit 3, power output circuit 4; The input of described data acquisition module 2 connects voltage transformer 15a summation current transformer 15b output, and the output of data acquisition module 2 is connected with the input of the central processing circuit 3 of two central processing units 31,32; The output of central processing circuit 3 connects the input of power output circuit 4; The output of power output circuit 4 connects generator excitation winding 11; Described voltage transformer 15a summation current transformer 15b input connects electrical network.。
Fig. 2 a is that the signal pre-processing circuit in Fig. 1 data acquisition module connects block diagram;
Fig. 2 b is that the frequency measurement circuit in Fig. 1 data acquisition module connects block diagram.
Shown in Fig. 2 a, 2b, described data acquisition module 2 comprises: signal pre-processing circuit 21 and frequency measurement circuit 22; Described signal pre-processing circuit 21 comprises: analog quantity pre-process circuit 211 and switching value pre-process circuit 212, the input of analog quantity pre-process circuit 211 connects the output of voltage transformer 15a summation current transformer 15b, the output of analog quantity pre-process circuit 211 connects, output connects central processing unit circuit 3, switching value pre-process circuit 212 inputs connect the output of protective relaying device 213, switching value pre-process circuit 212 outputs connect output and connect central processing unit circuit 3, and the input of protective relaying device 213 is connected on the electrical network; Described frequency measurement circuit 22 comprises: frequency measurement circuit 223, optical coupling isolator 224; The output of the input termination voltage transformer 15a summation current transformer 15b of frequency measurement circuit 223 is received central processing circuit 3 inputs behind the output series connection optical coupling isolator 224 of frequency measurement circuit 223.
Described frequency measurement circuit 223 is converted to square wave with input signal, by the event manager module 225 of optical coupling isolator 224 back incoming digital signal processors, finishes the measurement of frequency.
Fig. 3 is that Fig. 1 central processing circuit connects block diagram.
As shown in Figure 3, described central processing circuit 3 comprises: central processing unit 1 (sequence number 32 among the figure), central processing unit 2 (sequence number 31 among the figure), double-port RAM 33 and synchronizing sequential circuit 44; The READY pin of described central processing unit 1 (sequence number 32 among the figure) and two-way connection of BUSYL pin of double-port RAM 33, the R/W pin of central processing unit 1 (sequence number 32 among the figure) is connected with the R/WL of random asccess memory 33 is two-way, and the data wire of central processing unit 1 (sequence number 32 among the figure), address wire and random asccess memory 33 corresponding data line, address wire are connected; The READY pin of described central processing unit 2 (sequence number 31 among the figure) and two-way connection of BUSYR pin of double-port RAM 33, the R/W pin of central processing unit 2 (sequence number 31 among the figure) is connected with the R/WR of double-port RAM is two-way, and the data wire of central processing unit 2 (sequence number 31 among the figure), address wire and double-port RAM 33 corresponding data line, address wire are connected; Provide the synchronizing sequential circuit 34 of synchronizing clock signals to connect central processing unit 1 (sequence number 32 among the figure) and central processing unit 2 (sequence number 31 among the figure); Communication bus 35 two-way connection central processing units 1 (sequence number 32 among the figure) and central processing unit 2 (sequence number 31 among the figure).
Described central processing unit 1 (sequence number 32 among the figure) is that model is the DSP chip of TMS320F2812; Described central processing unit 2 (sequence number 31 among the figure) is that model is the enhancement mode reduced instruction set computer chip of AT91RM9200; Double-port RAM 33 is that model is the IDT70V24 chip.
Fig. 4 is that power output circuit connects block diagram among Fig. 1.
As shown in Figure 4, described power output circuit 4 comprises: phase-shift pulse forms circuit 41, pulse modulation amplifying circuit 42 and gated transistor rectification circuit 43; Central processing unit 2 (sequence number 31 among the figure) output connects phase-shift pulse and forms circuit 41 inputs, phase-shift pulse forms circuit 41 outputs connect successively pulse modulation amplifying circuit 42 and gated transistor rectification circuit 43, and the output of gated transistor rectification circuit 43 connects generator excitation winding 11.
Above-mentioned phase-shift pulse forms circuit 41 and realizes by central processing unit 2 (sequence number 31 among the figure), obtains the phase shift trigger angle.Pulse modulation amplifying circuit 42 carries out power amplification with the pulse signal that obtains.The output of pulse modulation amplifying circuit 42 is connected to gated transistor rectification circuit 43.
The invention provides a kind of control method with two central processing unit self interference resisting electromotor excitation controllers with claim 1, described control method comprised with the next stage:
(1). signal acquisition stage: voltage transformer 15a, current transformer 15b gather voltage, electric current, the frequency signal of electrical network;
(2). with acquired signal amplify, shaping and be transformed to the signal phase of acceptance: above-mentioned collection voltage, electric current, frequency signal are converted to central processing circuit 3 acceptable corresponding signals than low amplitude value by the signal pre-processing circuit 21 of data acquisition module 2;
(3). obtain the real time data stage of system: central processing unit 1 (sequence number 32 among the figure) is carried out active disturbance rejection algoritic module image data; A D adopt the inquiry working method, behind EOC, voltage, electric current, the frequency signal that collects carried out digital filtering; By calculating power, voltage, frequency, merit angle signal, and be saved in the double-port RAM 33.
(4). the implementation phase of active disturbance rejection algorithm: central processing unit 1 (sequence number 32 among the figure) is cycle calculations in a control signal output cycle of whole excitation controller, up to the input signal of extended state observer and the error between the single order output signal less than set point; After the extended state observer computing was finished, central processing unit 1 (sequence number 32 among the figure) was saved in disturbed value inside and outside the system that estimates in the double-port RAM 33, and finished signal to calculating of central processing unit 2 (sequence number 31 among the figure) transmission; Above process is finished by the active disturbance rejection algoritic module;
(5). the generation phase of control signal: after signal is finished in the calculating that central processing unit 2 (sequence number 31 among the figure) obtains central processing unit 1 (sequence number 32 among the figure), the output signal value of read-out power, voltage, frequency, merit angle, extended state observer from double-port RAM 33; According to active disturbance rejection excitation control law it is carried out simple plus and minus calculation and draw control signal, output to power output circuit 4;
(6). the exciting current generation phase: power output circuit 4 amplifies control signal, outputs to gated transistor rectification circuit 43 and produces exciting current.
Above-mentioned step (3) is made up of following flow process with the active disturbance rejection algoritic module in (4):
(1) state of inquiry A/D converter is not if finish then wait for; If conversion is finished, then the signal that collects is carried out digital filtering;
(2) calculate extended state observer, if resulting error is less than set point then finish computing and enter next step, if do not reach precision then cycle calculations;
(3) whether the inquiry random asccess memory can be write, if can not write then waits for, if can write then write the result that voltage, electric current, frequency and active disturbance rejection are expanded observer to random asccess memory, transmits completion signal to central processing unit 2;
(4) return information begins the place, carries out the next round computing.
The course of work of the present invention is: native system mainly is to utilize auto-disturbance rejection technology and two central processing unit hardware that the exciting current of generator is controlled.Alternating current sampling circuit is system voltage and current transformation than low amplitude value alternating voltage and electric current, and measures frequency.Signal is sent in the central processing unit 1 through analog quantity pre-process circuit and switching value pre-process circuit, and central processing unit 1 goes out the intermediate variable value according to the active disturbance rejection algorithm computation, and it is sent into double-port RAM.Central processing unit 2 is read each variate-value in the control law from double-port RAM, calculate control signal, is converted into pulse, control gated transistor rectification circuit output exciting current; Central processing unit 2 has the task of coordinating each module worker group simultaneously concurrently.
Claims (7)
1. the active disturbance rejection excitation controller with two central processing units is characterized in that, described active disturbance rejection excitation controller (1) with two central processing units comprising: data acquisition module (2), central processing circuit (3), power output circuit (4); The input of described data acquisition module (2) connects voltage transformer (15a) summation current transformer (15b) output, and the output of data acquisition module (2) is connected with the input of the central processing circuit (3) of two central processing units (31,32); The output of central processing circuit (3) connects the input of power output circuit (4); The output of power output circuit (4) connects generator excitation winding (11); Described voltage transformer (15a) summation current transformer (15b) input connects electrical network.
2. the active disturbance rejection excitation controller with two central processing units according to claim 1 is characterized in that, described data acquisition module (2) comprising: signal pre-processing circuit (21) and frequency measurement circuit (22); Described signal pre-processing circuit (21) comprising: analog quantity pre-process circuit (211) and switching value pre-process circuit (212), the input of analog quantity pre-process circuit (211) connects the output of voltage transformer (15a) summation current transformer (15b), the output of analog quantity pre-process circuit (211) connects, output connects central processing unit circuit (3), switching value pre-process circuit (212) input connects the output of protective relaying device (213), switching value pre-process circuit (212) output connects output and connects central processing unit circuit (3), and the input of protective relaying device (213) is connected on the electrical network; Described frequency measurement circuit (22) comprising: frequency measurement circuit (223), optical coupling isolator (224); The output of input termination voltage transformer (15a) summation current transformer (15b) of frequency measurement circuit (223) is received central processing circuit (3) input behind the output series connection optical coupling isolator (224) of frequency measurement circuit (223).
3. the active disturbance rejection excitation controller with two central processing units according to claim 1, it is characterized in that described central processing circuit (3) comprising: central processing unit 1 (32), central processing unit 2 (31), double-port RAM (33) and synchronizing sequential circuit (44); The two-way connection of BUSYL pin of the READY pin of described central processing unit 1 (32) and double-port RAM (33), the two-way connection of R/WL of the R/W pin of central processing unit 1 (32) and random asccess memory (33), data wire, address wire and random asccess memory (33) corresponding data line of central processing unit 1 (32), address wire are connected; The two-way connection of BUSYR pin of the READY pin of described central processing unit 2 (31) and double-port RAM (33), the R/W pin of central processing unit 2 (31) is connected with the R/WR of double-port RAM is two-way, and data wire, address wire and double-port RAM (33) corresponding data line of central processing unit 2 (31), address wire are connected; Provide the synchronizing sequential circuit (34) of synchronizing clock signals to connect central processing unit 1 (32) and central processing unit 2 (31); Two-way connection central processing unit 1 (32) of communication bus (35) and central processing unit 2 (31).
4. the active disturbance rejection excitation controller with two central processing units according to claim 3 is characterized in that, described central processing unit 1 (32) is that model is the DSP chip of TMS320F2812; Described central processing unit 2 (31) is that model is the enhancement mode reduced instruction set computer chip of AT91RM9200; Double-port RAM (33) is that model is the IDT70V24 chip.
5. the active disturbance rejection excitation controller with two central processing units according to claim 1, it is characterized in that described power output circuit (4) comprising: phase-shift pulse forms circuit (41), pulse modulation amplifying circuit (42) and gated transistor rectification circuit (43); Central processing unit 2 (31) outputs connect phase-shift pulse and form circuit (41) input, phase-shift pulse forms circuit (41) output connect successively pulse modulation amplifying circuit (42) and gated transistor rectification circuit (43), and the output of gated transistor rectification circuit (43) connects generator excitation winding (11).
6. the control method with two central processing unit self interference resisting electromotor excitation controllers with claim 1 is characterized in that, described control method comprised with the next stage:
(1). signal acquisition stage: voltage transformer (15a), current transformer (15b) are gathered voltage, electric current, the frequency signal of electrical network;
(2). with acquired signal amplify, shaping and be transformed to the signal phase of acceptance: above-mentioned collection voltage, electric current, frequency signal are converted to the acceptable corresponding signal than low amplitude value of central processing circuit (3) by the signal pre-processing circuit (21) of data acquisition module (2);
(3). obtain the real time data stage of system: central processing unit 1 (32) is carried out active disturbance rejection algoritic module image data; A D adopt the inquiry working method, behind EOC, voltage, electric current, the frequency signal that collects carried out digital filtering; By calculating power, voltage, frequency, merit angle signal, and be saved in the double-port RAM (33).
(4). the implementation phase of active disturbance rejection algorithm: central processing unit 1 (32) is cycle calculations in a control signal output cycle of whole excitation controller, up to the input signal of extended state observer and the error between the single order output signal less than set point; After the extended state observer computing was finished, central processing unit 1 (32) was saved in disturbed value inside and outside the system that estimates in the double-port RAM (33), and finished signal to calculating of central processing unit 2 (31) transmissions; Above process is finished by the active disturbance rejection algoritic module;
(5). the generation phase of control signal: after signal is finished in the calculating that central processing unit 2 (31) obtains central processing unit 1 (32), the output signal value of read-out power, voltage, frequency, merit angle, extended state observer from double-port RAM (33); According to active disturbance rejection excitation control law it is carried out simple plus and minus calculation and draw control signal, output to power output circuit (4);
(6). the exciting current generation phase: power output circuit (4) amplifies control signal, outputs to gated transistor rectification circuit (43) and produces exciting current.
7. the control method with active disturbance rejection excitation controller of two central processing units according to claim 6 is characterized in that, described step (3) is made up of following flow process with the active disturbance rejection algoritic module in (4):
(1) state of inquiry A/D converter is not if finish then wait for; If conversion is finished, then the signal that collects is carried out digital filtering;
(2) calculate extended state observer, if resulting error is less than set point then finish computing and enter next step, if do not reach precision then cycle calculations;
(3) whether the inquiry random asccess memory can be write, if can not write then waits for, if can write then write the result that voltage, electric current, frequency and active disturbance rejection are expanded observer to random asccess memory, transmits completion signal to central processing unit 2;
(4) return information begins the place, carries out the next round computing.
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101594112B (en) * | 2009-04-13 | 2012-11-07 | 北京前沿科学研究所 | Method for controlling frequency stabilization of permanent magnet wind-driven generator capable of adapting to changing torque |
| CN104270041A (en) * | 2014-09-26 | 2015-01-07 | 广州航海学院 | Rimer motor synchronous speed regulating control system based on active disturbance rejection control technology |
| CN113533837A (en) * | 2021-06-23 | 2021-10-22 | 上海南土信息科技有限公司 | Alternating current detection module |
| CN114448302A (en) * | 2022-01-15 | 2022-05-06 | 北京工业大学 | Active disturbance rejection control method for observing disturbance by using filter |
-
2007
- 2007-12-03 CN CNA2007101506843A patent/CN101170296A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101594112B (en) * | 2009-04-13 | 2012-11-07 | 北京前沿科学研究所 | Method for controlling frequency stabilization of permanent magnet wind-driven generator capable of adapting to changing torque |
| CN104270041A (en) * | 2014-09-26 | 2015-01-07 | 广州航海学院 | Rimer motor synchronous speed regulating control system based on active disturbance rejection control technology |
| CN113533837A (en) * | 2021-06-23 | 2021-10-22 | 上海南土信息科技有限公司 | Alternating current detection module |
| CN114448302A (en) * | 2022-01-15 | 2022-05-06 | 北京工业大学 | Active disturbance rejection control method for observing disturbance by using filter |
| CN114448302B (en) * | 2022-01-15 | 2023-07-21 | 北京工业大学 | Active disturbance rejection control method for observing disturbance by using filter |
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