CN101170096A - Electronic assembly and its base plate - Google Patents
Electronic assembly and its base plate Download PDFInfo
- Publication number
- CN101170096A CN101170096A CN 200610159822 CN200610159822A CN101170096A CN 101170096 A CN101170096 A CN 101170096A CN 200610159822 CN200610159822 CN 200610159822 CN 200610159822 A CN200610159822 A CN 200610159822A CN 101170096 A CN101170096 A CN 101170096A
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- Prior art keywords
- junction
- contraposition pad
- pad
- substrate
- contraposition
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
Abstract
The invention discloses an electronic component and a base plate thereof. The electronic component includes a base plate and a chip. The base plate has a bearing plane, which is provided with a first test pad, a second test pad, a first contrapuntal pad, a second contrapuntal pad and a plurality of connection points. The connection points have at least one first standard connection point. The first and the second contrapuntal pads are near the circumference of the first standard connection point respectively and are in open circuit state with the first standard connection point respectively and are in electrically connected with the first test pad. The first standard connection point is electrically connected with the second test pad. The chip is arranged on the bearing plane and has a plurality of joint pads, which are electrically connected with the connection points correspondingly. The first and the second test pads are not covered by the chip.
Description
Technical field
The present invention is relevant for a kind of electronic building brick and substrate thereof, and is particularly to a kind of electronic building brick and substrate thereof that carries out bit test.
Background technology
Continuous progress along with integrated circuit technique, all kinds of chips extensively are applied in the various electronic products, yet, allow these chips bring into play their effect, the most important condition be exactly must make chip joint sheet exactly with bearing substrate on contact electrically connect, so that the signal of telecommunication can correctly be passed to chip via bearing substrate, in the past, in (wire bonding) technology that engages with routing with chip join during to bearing substrate, because the joint sheet of chip and the contact of bearing substrate all expose, therefore the accuracy of GPRS routing joint is not difficult, but, along with the consumer must the compact standard that requires improve day by day for electronic product, and the joint sheet quantity of chip strengthens and the multiple growth with chip functions, the routing joining technique has been not suitable for being applied to the portions of electronics product, and for this reason, chip bonding (flip chip bonding) technology is arisen at the historic moment and is widely used.
Fig. 1 is the part sectioned view of explanation chip bonding processing procedure.Please refer to Fig. 1, so-called chip bonding technology is to form projection (bump) 50 on the joint sheet 110 of chip 100, then, chip 100 is overturned (flip) afterwards, projection 50 on the joint sheet 110 of chip 100 is electrically connected with contact 210 on the bearing substrate 200, so, chip 100 can be electrically connected to bearing substrate 200 via projection 50, if necessary, chip 100 also can be electrically connected to extraneous electronic installation via bearing substrate 200, yet, adopting the chip bonding technology to electrically connect in the process of chip 100 and bearing substrate 200, because chip 100 is lighttight, therefore how to make on the joint sheet 110 projection 50 can with contact 210 accurate contrapositions, just become very important problem, in case the inaccurate situation of contraposition takes place, the signal of telecommunication can't correctly be passed to chip 100 via bearing substrate 200, make that chip 100 can't normal operation, even, the situation that projection 50 is electrically connected to wrong contact 210 might take place, or single projection 50 electrically connects the situation of a plurality of contacts 210 simultaneously.
Reliability in order to ensure product, generally can after finishing electric connection, chip and bearing substrate check, with the LCD is example, when chip adopts crystal grain-glass bond (chip on glass, COG) technology is with after glass substrate in the display panels engages, because glass substrate is a light-permeable, therefore generally can carry out visual detection by gold as microscope with manual type, yet, the manual detection mode not only expends a large amount of manpowers, more there is the risk that causes detecting error because of visual fatigue, in addition, because the manual detection mode can't be integrated in the automatic assembly line, therefore product must be carried to the manual detection place by automatic assembly line, more increased the probability that product is damaged or polluted in handling process, therefore, how fast and the detection after carrying out chip and bearing substrate engages exactly, reduce the integral production cost simultaneously, the problem that has become technical field for this reason to need to be resolved hurrily.
Summary of the invention
The purpose of this invention is to provide a kind of substrate, be applicable to fast and the yield that engages of detection chip and substrate exactly.
Another object of the present invention provides a kind of electronic building brick, is applicable to fast and the yield that engages of chip and the substrate of detector electronics exactly, and has lower production cost.
The present invention proposes a kind of substrate, this substrate comprises a loading end, the loading end configuration is provided with one first testing cushion, one second testing cushion, one first contraposition pad, one second contraposition pad and a plurality of contact, and these contacts are provided with at least one first reference-junction, the first contraposition pad and the second contraposition pad are respectively adjacent in the first reference-junction periphery, the first contraposition pad and the second contraposition pad are and are electrically connected at first testing cushion, and be the shape that opens circuit respectively and between first reference-junction, and first reference-junction is and is electrically connected at second testing cushion.
The present invention proposes a kind of electronic building brick in addition, it comprises a substrate and a chip, substrate comprises a loading end, and the loading end configuration is provided with one first testing cushion, one second testing cushion, one first contraposition pad, one second contraposition pad and a plurality of contact, these contacts are provided with at least one first reference-junction, and the first contraposition pad and the second contraposition pad are respectively adjacent in the first reference-junction periphery, the first contraposition pad and the second contraposition pad are and are electrically connected at first testing cushion, and be the shape that opens circuit respectively and between first reference-junction, and first reference-junction is and is electrically connected at second testing cushion, chip configuration is in loading end and have a plurality of joint sheets, these joint sheets are electrically connected to contact accordingly, and chip does not cover first testing cushion and second testing cushion.
In an embodiment of aforesaid substrate and electronic building brick, the first contraposition pad and the second contraposition pad lay respectively at the horizontal side and the vertical side of first reference-junction.
In an embodiment of aforesaid substrate and electronic building brick, these contacts are to form a line, and first reference-junction is positioned at the row head or the row tail of this row contact.
In an embodiment of aforesaid substrate and electronic building brick, first reference-junction is positioned at the corner of these contacts.
In an embodiment of aforesaid substrate and electronic building brick, the first contraposition pad and the second contraposition pad are to fuse, and in addition, the first contraposition pad and the second contraposition pad that fuse for example are to be the L type.
In an embodiment of aforesaid substrate and electronic building brick, substrate can be glass substrate, printed circuit board (PCB) or film substrate.
In an embodiment of aforesaid substrate and electronic building brick, also dispose one the 3rd testing cushion on the loading end, one the 4th testing cushion, one the 3rd contraposition pad and one the 4th contraposition pad, also comprise one second reference-junction in the aforementioned contact, the 3rd contraposition pad and the 4th contraposition pad are respectively adjacent in the second reference-junction periphery, the 3rd contraposition pad and the 4th contraposition pad are and are electrically connected at the 3rd testing cushion, and second reference-junction is and is electrically connected at the 4th testing cushion, in addition, the 3rd contraposition pad and the 4th contraposition pad for example are horizontal side and the vertical sides that lays respectively at second reference-junction, in addition, aforementioned contact for example forms a line, and first reference-junction and second reference-junction lay respectively at the first and row tail of row of this row contact, moreover, and first reference-junction and second reference-junction lay respectively at the corner of these contacts, and in addition, the 3rd contraposition pad and the 4th contraposition pad for example fuse, wherein, the 3rd contraposition pad and the 4th contraposition pad that fuse for example are to be the L type.
In sum, in electronic building brick of the present invention and the substrate thereof, design by first and second contraposition pad and first and second testing cushion, as long as carry out simple line conduction test, can know the situation that engages of chip and substrate, therefore, can be fast and the yield that engages of detection chip and substrate exactly, reduce whole production cost simultaneously.
For above-mentioned and other purposes, feature and advantage of the present invention can be become apparent, preferred embodiment cited below particularly, and conjunction with figs. is described in detail below.
Description of drawings
Fig. 1 is the part sectioned view of explanation chip bonding processing procedure.
Fig. 2 is the partial schematic diagram of the substrate of one embodiment of the invention.
Fig. 3 is the partial schematic diagram of the electronic building brick of one embodiment of the invention.
Fig. 4 is the partial schematic diagram of the substrate of another embodiment of the present invention.
Fig. 5 is the partial schematic diagram of the substrate of yet another embodiment of the invention.
Fig. 6 is the partial schematic diagram of the substrate of further embodiment of this invention.
Embodiment
Fig. 2 is the partial schematic diagram of the substrate of one embodiment of the invention, and Fig. 3 is the partial schematic diagram of the electronic building brick of one embodiment of the invention.The electronic building brick 400 of Fig. 3 comprises as the substrate 300 of Fig. 2 and a chip 100, please refer to Fig. 2 and Fig. 3, chip 100 has a joint sheet 110, the substrate 300 of present embodiment is applicable to carrying one chip 100, substrate 300 has a loading end S30, dispose one first testing cushion 310 on the loading end S30, one second testing cushion 312, one first contraposition pad 320, one second contraposition pad 322 and a plurality of contacts 330, the position of these contacts 330 is the positions that correspond respectively to each joint sheet 110 of chip 100, and comprise one first reference-junction 332 in these contacts 330, the first contraposition pad 320 and the second contraposition pad, 322 contiguous first reference-junction, 332 sides that are positioned at, the first contraposition pad 320 and the second contraposition pad 322 all electrically connect first testing cushion 310, at this, the first contraposition pad 320, the second contraposition pad 322 and first testing cushion 310 electrically connect mutually by a connecting line 340,332 of first reference-junctions electrically connect second testing cushion 312, and both electrically connect mutually by a connecting line 342.
The joint sheet 110 of chip 100 is electrically connected to contact 330 accordingly, its electric connection mode for example is to see through projection 50, anisotropy conducting film (anisotropic conductive film, ACF) or other suitable modes, in addition, chip 100 can not cover first testing cushion 310 and second testing cushion 312, also promptly, after the joint sheet 110 of chip 100 electrically connected with the contact of substrate 300 330, first testing cushion 310 and second testing cushion 312 still can be exposed to the external world.
Hold above-mentioned, after the contact 330 of the joint sheet 110 of chip 100 and substrate 300 electrically connects, as long as whether detect first testing cushion 310 and second testing cushion 312 via first reference-junction 332, joint sheet 110, the first contraposition pad 320 and/or the second contraposition pad 322 and electrically connect, can know whether joint sheet 110 and contact 330 correctly electrically connect or have bit errors to exist, for example, if detection signal can be passed to second testing cushion 312 by first testing cushion 310, i.e. expression has bit errors to produce, so that first reference-junction 332 electrically connects the first contraposition pad 320 and/or the second contraposition pad 322 via joint sheet 110, otherwise, if detection signal can't be passed to second testing cushion 312 by first testing cushion 310, i.e. expression has first reference-junction 332 and joint sheet 110 correctly to electrically connect mutually.
Therefore, the substrate 300 of present embodiment and electronic building brick 400 are suitable for fast and the yield that engages of detection chip 100 and substrate 300 exactly, can reduce the production cost of integral body simultaneously.
Referring again to Fig. 2, in the substrate 300 of present embodiment, see it by substrate 300 tops, the first contraposition pad, the 320 contiguous horizontal side that are positioned at first reference-junction 332, and the second contraposition pad, the 322 contiguous vertical sides that are positioned at first reference-junction 332, in other words, the first contraposition pad 320 that is positioned at first reference-junction, 332 horizontal side can be used for the bit errors component on the detection level direction, and the vertical side that is positioned at first reference-junction 332 can be used for the bit errors component on the detection of vertical direction, but, the first contraposition pad 320 and the second contraposition pad 322 still can optionally be adjusted with respect to the orientation of first reference-junction 332, are not limited to said circumstances.
In addition, in the substrate 300 of present embodiment, these contacts 330 for example form a line, and only show the wherein a part of of this row contact 330 in Fig. 2, and first reference-junction 332 are positioned at the row head or the row tail of this row contact 330.
In addition, in the substrate 300 of present embodiment, substrate 300 can be glass substrate, printed circuit board (PCB) or film substrate, and therefore, substrate 300 can be applicable in each electronic product, for example flat-panel screens etc.Moreover, first testing cushion 310, second testing cushion 312, the first contraposition pad 320, the second contraposition pad, 322 connecting lines 340 and 342 and the material of contact 330 can be metal, indium tin oxide (Indium Tin Oxide, ITO) or other conductive material.
Fig. 4 is the partial schematic diagram of the substrate of another embodiment of the present invention.Please refer to Fig. 4, the substrate 500 of present embodiment is similar to the substrate 300 of Fig. 2, its difference only is that the first contraposition pad 520 and the second contraposition pad 522 fuse, all the other same sections are not then given unnecessary details at this, in addition, the first contraposition pad 520 and the second contraposition pad 522 that fuse are the L type, and certainly, the substrate 500 of present embodiment also can be formed an electronic building brick with the chip 100 of Fig. 3.
Fig. 5 is the partial schematic diagram of the substrate of yet another embodiment of the invention.Please refer to Fig. 5, the substrate 600 of present embodiment is similar to the substrate 300 of Fig. 2, one of its difference is that contact 630 is to line up a rectangular array, and first reference-junction 632 is positioned at the corner of rectangular array, substrate 600 with another difference of the substrate 300 of Fig. 2 then is, the loading end S60 of substrate 600 disposes one the 3rd testing cushion 640, one the 4th testing cushion 642, one the 3rd contraposition pad 650 and one the 4th contraposition pad 652, comprise one second reference-junction 634 in these contacts 630, the 3rd contraposition pad 650 and the 4th contraposition pad 652 contiguous second reference-junction, 634 sides that are positioned at, the 3rd contraposition pad 650 and the 4th contraposition pad 652 all electrically connect the 3rd testing cushion 640, and second reference-junction 634 electrically connects the 4th testing cushion 642.
In addition, the 3rd contraposition pad 650 is then similar to the second contraposition pad 322 to the first contraposition pad 320 of Fig. 2 to the variation of shape to the position of the 4th contraposition pad 652, in addition, first reference-junction 632 and second reference-junction 634 lay respectively at two corners at rectangular array diagonal angle, the substrate 600 of present embodiment is not given unnecessary details at this with the same section of the substrate 300 of Fig. 2, certainly, the substrate 600 of present embodiment also can be formed an electronic building brick with the chip 100 of Fig. 3.
Fig. 6 is the partial schematic diagram of the substrate of further embodiment of this invention.Please refer to Fig. 6, the substrate 700 of present embodiment is similar to the substrate 600 of Fig. 5, its difference only is that contact 730 is that annular arrangement becomes a rectangle, and first reference-junction 732 and second reference-junction 734 lay respectively at two corners at rectangle diagonal angle, all the other same sections are not then given unnecessary details at this, certainly, the substrate 700 of present embodiment also can be formed an electronic building brick with the chip 100 of Fig. 3.
In sum, electronic building brick of the present invention and substrate thereof are because other first and second contraposition pad that disposes of reference-junction, therefore when chip and substrate contraposition are inaccurate, the first contraposition pad and/or the second contraposition pad will electrically connect reference-junction via joint sheet, thus, as long as whether detect first and second testing cushion electrically connects via joint sheet and the first contraposition pad and/or the second contraposition pad, can know the situation that engages of chip and substrate, therefore, can be fast and the yield that engages of detection chip and substrate exactly, also this inspection process can be transferred to automation equipment and carry out, reduce whole production cost simultaneously.
Though the present invention discloses as above with preferred embodiment; right its is not in order to limit the present invention; have in the technical field under any and know the knowledgeable usually; without departing from the spirit and scope of the present invention; when can doing a little change and retouching, so protection scope of the present invention is when with being as the criterion that claim was defined.
Claims (10)
1. substrate, this substrate comprises a loading end, this loading end configuration is provided with one first testing cushion, one second testing cushion, one first contraposition pad, one second contraposition pad and a plurality of contact, and those contacts are provided with at least one first reference-junction, this first contraposition pad and this second contraposition pad are respectively adjacent in this first reference-junction periphery, and this first contraposition pad and this second contraposition pad are the shape that opens circuit respectively and between this first reference-junction, this first contraposition pad and this second contraposition pad are and are electrically connected at this first testing cushion, and this first reference-junction is and is electrically connected at this second testing cushion.
2. substrate as claimed in claim 1 is characterized in that, this first contraposition pad and this second contraposition pad lay respectively at the horizontal side and the vertical side of this first reference-junction.
3. substrate as claimed in claim 1 is characterized in that this first reference-junction is positioned at the corner of those contacts.
4. substrate as claimed in claim 1 is characterized in that, this first contraposition pad and this second contraposition pad are to fuse.
5. substrate as claimed in claim 1, it is characterized in that, dispose one the 3rd testing cushion, one the 4th testing cushion, one the 3rd contraposition pad and one the 4th contraposition pad on this loading end, comprise one second reference-junction in those contacts, the 3rd contraposition pad and the 4th contraposition pad are respectively adjacent in this second reference-junction periphery, and the 3rd contraposition pad and the 4th contraposition pad are and are electrically connected at the 3rd testing cushion, and this second reference-junction is and is electrically connected at the 4th testing cushion.
6. substrate as claimed in claim 5 is characterized in that, this first reference-junction and this second reference-junction lay respectively at the corner of those contacts.
7. electronic building brick comprises:
One substrate, has a loading end, this loading end configuration is provided with one first testing cushion, one second testing cushion, one first contraposition pad, one second contraposition pad and a plurality of contact, and those contacts are provided with at least one first reference-junction, this first contraposition pad and this second contraposition pad are respectively adjacent in this first reference-junction periphery, and this first contraposition pad and this second contraposition pad are the shape that opens circuit respectively and between this first reference-junction, this first contraposition pad and this second contraposition pad are and are electrically connected at this first testing cushion, and this first reference-junction is and is electrically connected at this second testing cushion; And
One chip is disposed on this loading end and has a plurality of joint sheets, and those joint sheet correspondences are connected in those contacts, and this chip does not cover this first testing cushion and this second testing cushion.
8. electronic building brick as claimed in claim 7 is characterized in that, this first contraposition pad and this second contraposition pad lay respectively at the horizontal side and the vertical side of this first reference-junction.
9. electronic building brick as claimed in claim 7, it is characterized in that, dispose one the 3rd testing cushion, one the 4th testing cushion, one the 3rd contraposition pad and one the 4th contraposition pad on this loading end, also comprise one second reference-junction in those contacts, the 3rd contraposition pad and the 4th contraposition pad are respectively adjacent in this second reference-junction periphery, and the 3rd contraposition pad and the 4th contraposition pad are and are electrically connected at the 3rd testing cushion, and this second reference-junction is and is electrically connected at the 4th testing cushion.
10. electronic building brick as claimed in claim 9 is characterized in that, this first reference-junction and this second reference-junction lay respectively at the corner of those contacts.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200610159822 CN101170096A (en) | 2006-10-27 | 2006-10-27 | Electronic assembly and its base plate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200610159822 CN101170096A (en) | 2006-10-27 | 2006-10-27 | Electronic assembly and its base plate |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN101170096A true CN101170096A (en) | 2008-04-30 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 200610159822 Pending CN101170096A (en) | 2006-10-27 | 2006-10-27 | Electronic assembly and its base plate |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN101170096A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105161037A (en) * | 2015-08-20 | 2015-12-16 | 京东方科技集团股份有限公司 | Position calibration method, test circuit board, sample panel and position calibration device |
| CN105529324A (en) * | 2014-10-21 | 2016-04-27 | 三星电子株式会社 | SYSTEM OF PACKAGE (SoP) MODULE AND MOBILE COMPUTING DEVICE HAVING THE SoP |
| CN113161251A (en) * | 2020-01-22 | 2021-07-23 | 复格企业股份有限公司 | In-process testing method and device for chip packaging |
-
2006
- 2006-10-27 CN CN 200610159822 patent/CN101170096A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105529324A (en) * | 2014-10-21 | 2016-04-27 | 三星电子株式会社 | SYSTEM OF PACKAGE (SoP) MODULE AND MOBILE COMPUTING DEVICE HAVING THE SoP |
| CN105529324B (en) * | 2014-10-21 | 2019-11-22 | 三星电子株式会社 | System-in-package module and mobile computing device with system in package |
| CN105161037A (en) * | 2015-08-20 | 2015-12-16 | 京东方科技集团股份有限公司 | Position calibration method, test circuit board, sample panel and position calibration device |
| US10247772B2 (en) | 2015-08-20 | 2019-04-02 | Boe Technology Group Co., Ltd. | Position calibration method, test circuit board, sample panel and position calibration apparatus |
| CN113161251A (en) * | 2020-01-22 | 2021-07-23 | 复格企业股份有限公司 | In-process testing method and device for chip packaging |
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