CN101170064B

CN101170064B - Method for flash technology high-voltage bar oxygen and tunnel-penetration oxidation layer

Info

Publication number: CN101170064B
Application number: CN200610117432A
Authority: CN
Inventors: 杨斌; 李铭; 龚新军; 杨鹏
Original assignee: Shanghai Hua Hong NEC Electronics Co Ltd; Shanghai Integrated Circuit Research and Development Center Co Ltd
Current assignee: Shanghai IC R&D Center Co Ltd; Shanghai Huahong Grace Semiconductor Manufacturing Corp
Priority date: 2006-10-23
Filing date: 2006-10-23
Publication date: 2010-05-12
Anticipated expiration: 2026-10-23
Also published as: CN101170064A

Abstract

The invention discloses a flash memory technology high pressure gate oxide and tunneling oxide formation method, which comprise the steps of firstly retaining a floating boom gate oxide after floatingboom etching, with the thickness of 50-70 and eroding the floating boom gate oxide by the wet method and retaining the thickness of 20-30; then utilizing high temperature pressure reducing chemical vapor deposition method to form the tunneling oxide and the high pressure gate oxide simultaneously; at last forming the tunneling oxide with the thickness of 160-180 and the gate oxide with the high pressure of 180-210. The invention can improve electric field intensity in erasing, reduce oxide trap number and is good for the erasing capability improvement of storage unit, by reducing the thickness of the tunneling oxide.

Description

Flash technology high-voltage bar oxygen and tunnel oxide formation method

Technical field

The present invention relates to a kind of semiconductor integrated circuit technique method, be meant a kind of flash technology high-voltage bar oxygen and tunnel oxide formation method especially.

Background technology

Flash memory is as a kind of main non-volatility memorizer, and it has purposes widely in fields such as smart card, microcontrollers.Compare with another kind of non-volatility memorizer EEPORM, flash memory has the advantage on the tangible area; But simultaneously, the reliability of flash memory, especially erasable number of times, poorer than EEPROM, therefore in products such as bank card, the ID card, be not used yet.

SST type flash memory is that the structure of its memory cell as shown in Figure 1 by a kind of flash type (U.S. Patent number 5029130) of Bing Yeh in the nineteen ninety invention.Wherein polycrystalline 1 is a floating boom, is below

Thick floating boom grid oxide layer.Polycrystalline 2 parts are covered on floating boom, and the control gate when wiping between control gate and the floating boom is

Thick tunnel oxide; A part is covered on active area, is below Thick high-pressure gate oxide, a transistor of formation and floating boom transistor series, this part is called as the branch grid.

The main processes of this flash memory is as follows: 1. isolated area/active area forms; 2. high voltage transistor, the memory cell trap injects; 3. floating boom gate oxidation

4. floating boom polycrystalline deposition

5. floating boom selective oxidation; 6. floating boom etching; 7. the residual oxide layer wet etching is clean; 8. high-pressure gate oxide/tunnel oxide forms

9. subsequent steps comprises that with conventional low pressure MOS technology the low voltage transistor trap injects, the low pressure gate oxidation, and polycrystalline two deposits, LDD injects, abutment wall forms, injection etc. is leaked in the source.

In above-mentioned technology, high-pressure gate oxide and tunnel oxide form simultaneously, the general thermal oxide layer that approaches that adopts The high temperature oxide layer of thickening Be formed by stacking.Earlier use one deck thermal oxidation, be because hot oxygen is best in quality with the interfacial state of silicon substrate, but the hot oxygen of this one deck can not be too thick, otherwise the wedge angle at floating boom edge can be by undue oxidation and rust, so HTO (high-temperature oxydation) layer preferably of deposit one deck quality again.The final thickness of high-pressure gate oxide/tunnel oxide also can be subjected to the influence of steps such as cleaning, low pressure grid oxygen in the technical process, but the amount of influence of these processing steps is less relatively, and basic fixed.

The erasable number of times of SST type flash memory depends primarily on the performance of wiping of memory cell.Increase along with erasable number of times, charge trap in the tunnel oxide can increase thereupon, make increasing electronics in tunnelling process, be trapped in the charge trap, thereby make the electric field strength between control gate and the floating boom reduce because of the shielding of trapped charge, the ability of wiping constantly reduces, and finally loses efficacy because of wiping.At present, the erasable number of times specification of SST type flash memory is 100,000 times.

Therefore, in this technical field, need a kind of flash technology method, strengthen the electric field strength when wiping, reduce the trap quantity of oxide layer, thereby improve the ability of wiping of memory cell.

Summary of the invention

The technical problem to be solved in the present invention provides a kind of flash technology high-voltage bar oxygen and tunnel oxide formation method, and it can reduce the tunnel oxide layer thickness, and increases the erasable number of times of flash memory.

For solving the problems of the technologies described above, the invention provides a kind of flash technology high-voltage bar oxygen and tunnel oxide formation method, at first, and floating boom grid oxide layer after the reservation floating boom etching, its thickness is Next corrodes with wet method described floating boom grid oxide layer, keeps its thickness and is

Afterwards, utilize high temperature rpcvd technology to form tunnel oxide and high-pressure gate oxide layer simultaneously; Finally, the thickness of described tunnel oxide formation is The thickness that described high-pressure gate oxide layer forms is

The present invention can form under the prerequisite of high-pressure gate oxide and tunnel oxide at the same time by suitably keeping residual floating gate oxide layers after the floating boom etching, realize that high-pressure gate oxide thickness is consistent with existing technology, and tunnel oxide is thinner than existing technology

Thereby guaranteeing to improve erasable number of times under the constant situation of other characteristic of flash memory.

By reducing the thickness of tunnel oxide, under same condition of work, not only strengthen the electric field strength when wiping, and the also corresponding minimizing of the trap quantity of oxide layer, help improving the ability of wiping of memory cell, thereby increase its erasable number of times.When the tunnel oxide layer thickness reduces to

The time, its erasable number of times can reach more than 200,000 times, doubles than existing level.

Description of drawings

The present invention is further detailed explanation below in conjunction with accompanying drawing and embodiment.

Fig. 1 is the structural representation of flash memory cell;

Fig. 2 is that the present invention keeps floating boom grid oxide layer structural representation after the floating boom etching;

Fig. 3 is a wet etching floating boom grid oxide layer structural representation of the present invention;

Fig. 4 is that high temperature rpcvd technology of the present invention forms tunnel oxide and high voltage gate oxygen structure schematic diagram simultaneously.

Embodiment

Reduce the thickness of tunnel oxide, under same condition of work, not only directly strengthen the electric field strength when wiping, and the also corresponding minimizing of the trap quantity of oxide layer, help improving the ability of wiping of memory cell, thereby increase its erasable number of times.When the tunnel oxide layer thickness reduces to

The time, its erasable number of times can reach 200,000 times.

But the high pressure oxidation layer thickness will satisfy the requirement of withstand voltage of high voltage transistor.Because flash memory work the time can be used the voltage up to 12～14V, the gross thickness of high-pressure gate oxide layer need greater than

Could guarantee its operate as normal and reliability requirement.In the technology that high-pressure gate oxide and tunnel oxide form simultaneously at present, be difficult to the tunnel oxide layer thickness is further reduced.

Therefore, the main technique step that adopts in the present invention is as follows: 1. isolated area/active area forms (with existing technology); 2. high voltage transistor, memory cell trap inject (with existing technology); The floating boom gate oxidation (with existing technology,

); The floating boom polycrystalline deposition (with existing technology,

); 5. floating boom selective oxidation (with existing technology); 6. (with existing technology, oxide layer is residual for the floating boom etching

); 7. oxide layer wet etching

8. high temperature reduced pressure chemical vapor deposition thickness is

HTO; 9. the step that continues comprises that with conventional low pressure MOS technology the low voltage transistor trap injects, the low pressure gate oxidation, and polycrystalline two deposits, LDD injects, abutment wall forms, injection etc. is leaked in the source.

Wherein, step 1～6 are with existing technology, and are bigger than very to the selection of oxide layer in step 6 floating boom etching, therefore by etching, original

The thick still residual pact of floating boom grid oxygen

Thick, as shown in Figure 2.

According to remaining thickness of oxide layer after the step 6 floating boom etching, select the suitable wet etching time, make the oxidated layer thickness that keeps on the silicon substrate be As shown in Figure 3.

Adopt high temperature reduced pressure chemical vapor deposition (LPCVD HTO) technology, deposit

Thick high-pressure gate oxide layer and tunnel oxide may ultimately reach the high-pressure gate oxide layer

As shown in Figure 4.Other processing step that continues is with existing technology.

According to above-mentioned processing step, finally can form thickness and be

The high-pressure gate oxide layer, thickness is

The tunnel oxide of floating boom sharp corner.

Residual oxide layer after existing technology is with the floating boom etching all corrosion is clean, and hot oxygen then regrows.The present invention is then with the residual oxide layer partial corrosion, keeps its thickness to be

Be because floating boom grid oxygen itself is the extraordinary oxide layer of quality, and the floating boom etching is to select in a step than very high etching, so have only the surface influenced by the floating boom etching.With the surface

Left and right sides oxide layer is fallen with the less relatively wet etching of damage, and remaining quality of oxide layer still can satisfy requirement on devices.

The existing technology high-voltage bar oxygen first step adopts the way of the hot oxygen that regrows, although thinner, its thickness is

Still can be with established floating boom wedge angle rust.The present invention is owing to kept part floating boom grid oxygen on silicon substrate, therefore, high-pressure gate oxide/tunnel oxide homogeneous step deposit forms, and protects the floating boom wedge angle as much as possible.

Because its thickness of reservation is on the silicon substrate

After the HTO deposit, the thickness of high voltage grid oxidation layer is

Consistent with existing technology; And the tunnel oxide layer thickness of floating boom sharp corner is

On average thinner than existing technology

So just realized improving erasable number of times under the constant situation of other characteristics of flash memory.

Claims

1. flash technology high-voltage bar oxygen and tunnel oxide formation method is characterized in that: at first, keep floating boom grid oxide layer after the floating boom etching, and its thickness is 50～

Secondly, described floating boom grid oxide layer is corroded with wet method, keep its thickness and be 20～ Afterwards, utilize high temperature rpcvd technology to form tunnel oxide and high-pressure gate oxide layer simultaneously; Finally, the thickness that forms of described tunnel oxide be 160～ The thickness that described high-pressure gate oxide layer forms is 180～