CN101162433A - Electric power pulling bias testing device and testing method thereof - Google Patents
Electric power pulling bias testing device and testing method thereof Download PDFInfo
- Publication number
- CN101162433A CN101162433A CNA2007101881815A CN200710188181A CN101162433A CN 101162433 A CN101162433 A CN 101162433A CN A2007101881815 A CNA2007101881815 A CN A2007101881815A CN 200710188181 A CN200710188181 A CN 200710188181A CN 101162433 A CN101162433 A CN 101162433A
- Authority
- CN
- China
- Prior art keywords
- power supply
- effect transistor
- field effect
- timing sequence
- electrifying timing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Landscapes
- Tests Of Electronic Circuits (AREA)
- Testing Of Individual Semiconductor Devices (AREA)
- Electronic Switches (AREA)
Abstract
The invention discloses a power supply bias test device, comprising an adjustable power supply, a power on sequence control circuit and a switch element, wherein the adjustable power supply connected with the switch element is used to supply the electricity for the switch element; the power on sequence control circuit is used to output switch signals to the switch element, the switch signals generated according to the set power on sequence are used to control the opening of the switch element; the adjustable power supply outputs the bias power supply by the switch element which is used to realize the bias of the power supply which needs the bias. The invention also discloses a power supply bias test method. Compared with prior art, by the simple method, the invention realizes the bias of the power supply in a system, of which the power on sequence requirement is needed, thereby reducing the complexity of the system and improving the maneuverability.
Description
Technical field
The present invention relates to a kind of test of semiconductor integrated circuit technology, specifically, relate to a kind of electric power pulling bias testing device and method of testing thereof.
Background technology
Along with the development of SIC (semiconductor integrated circuit), the integrated level of present electronic equipment is more and more higher, and is also more and more higher to the requirement of measuring technology, and wherein electric power pulling bias testing just often can have been used a kind of method of testing.
In the test macro of some mainboards, when being tested, critical component need carry out electric power pulling bias testing, when critical component need draw inclined to one side power supply many and when having electrifying timing sequence to require, need control powering on of these power supplys, a kind of practice is to control supply voltage, power-on and power-off sequential with main control server, do the systematic comparison complexity like this, and this system regards mainboard as an integral body, the power supply to mainboard inside does not draw partially.
Some test need be drawn partially the veneer internal electric source, and a kind of practice is exactly to come pressure regulation by the output current that the control peripheral components is controlled power module, but drawing of this method is discontinuous partially, and draws inclined to one side scope narrow.Another practice is removed power module exactly, and external regulated power supply is tested.Draw if desired between inclined to one side power supply and other power supplys in the system and do not have strict electrifying timing sequence requirement, directly external power supply test, but draw if desired between inclined to one side power supply and other power supplys in the system electrifying timing sequence requirement is arranged, when system powers on, need guarantee powering on synchronously of other power supplys in external power supply and the system, otherwise system can't work.
Existing patent documentation comprises: number of patent application is 02131007 Chinese patent application " a kind of system that realizes envivonment test of mainboard ", number of patent application is 03137017 Chinese patent application " a kind of system and method to the test of computing machine critical component ", number of patent application is the Jap.P. " VOLTAGE MARGIN TESTING SYSTEM FOR INFORMATIONPROCESSOR " (the boundary voltage test macro of message handler) that 03206587 Chinese patent application " a kind of voltage draws inclined to one side mould " and Japanese Patent No. are 05002502A.
No. 02131007 and No. 03137017 Chinese patent have the following disadvantages: these two patents all propose to control the electrifying timing sequence that draws inclined to one side power supply with main control computer, the system of amplitude, and more complicated, and do not relate to drawing partially of mainboard internal electric source here yet.
No. 03206587 Chinese patent has the following disadvantages: the output current that proposes to control with the switch of a plurality of field effect transistor power module in this patent, thereby the output voltage of control power supply, drawing partially of final realization power supply, it is drawing partially of carrying out under the situation that power module exists partially that this kind draws, this ladder that draws the folk prescription formula can only realize voltage draws partially, can not electrodelessly regulate, the scope that voltage is adjusted is also limited, be suitable for the integration test of the parts power supply of the integrated manufacturer of computing machine, but need in the test of wide tuning range stepless pressure regulation inapplicable at some.
05002502A number Jap.P. has the following disadvantages: the testing scheme that a kind of automatic test border operating voltage is provided in this patent, can realize automatic test, record, but, and have the system of electrifying timing sequence requirement how to draw partially not relate to for many power supplys.
Summary of the invention
Technical matters solved by the invention provides a kind of electric power pulling bias testing device, has realized having drawing partially of electrifying timing sequence requirement power supply.
Technical scheme is as follows:
A kind of electric power pulling bias testing device comprises regulated power supply, electrifying timing sequence control circuit and on-off element, and wherein, described regulated power supply is connected with described on-off element, is used for providing power supply to described on-off element; Described electrifying timing sequence control circuit is used for output switching signal and gives described on-off element, and described switching signal generates according to the electrifying timing sequence of setting, and is used to control the open-minded of described on-off element; Described regulated power supply draws inclined to one side power supply by the output of described on-off element, describedly draws inclined to one side power supply to be used to realize needs are drawn drawing partially of inclined to one side power supply.
Preferably, be provided with driving circuit between described electrifying timing sequence control circuit and on-off element, described driving circuit is used to drive the open-minded of described on-off element; Described electrifying timing sequence control circuit requires the described switching signal of output to give described driving circuit according to powering on of system under test (SUT) or veneer, described driving circuit generates drive signal according to described switching signal and sends to described on-off element, and the electrifying timing sequence of described system under test (SUT) or veneer is controlled by described electrifying timing sequence control circuit.
Preferably, described on-off element is a field effect transistor, and described driving circuit is the field effect transistor driving circuit; Described electrifying timing sequence control circuit is exported described switching signal according to the electrifying timing sequence of setting and is given the field effect transistor driving circuit, thereby the control field effect transistor is open-minded.
Preferably, the grid of described field effect transistor driving circuit and described field effect transistor is connected, and the negative pole of described regulated power supply draws the ground of inclined to one side power supply to be connected with described needs.
Preferably, described field effect transistor is a N channel field-effect pipe, and the positive pole of described regulated power supply is connected with the drain electrode of described N channel field-effect pipe, and the source electrode of described N channel field-effect pipe draws the positive pole of inclined to one side power supply to be connected with described needs; Perhaps, described field effect transistor is a P road ditch field effect transistor, and the positive pole of described regulated power supply is connected with the source electrode of described P road ditch field effect transistor, and described needs draw the positive pole of inclined to one side power supply and the drain electrode of described P road ditch field effect transistor to be connected.
Another technical matters solved by the invention provides a kind of electric power pulling bias testing method, has realized having drawing partially of electrifying timing sequence requirement power supply.
Technical scheme is as follows:
A kind of electric power pulling bias testing method, step comprises:
(1) regulated power supply is powered to field effect transistor, and the output of adjusting described regulated power supply reaches the amplitude that on-off element needs;
(2) after the energising of system under test (SUT) or veneer, the electrifying timing sequence control circuit is given described on-off element according to the electrifying timing sequence output switching signal of setting, and described switching signal is used to control the open-minded of described on-off element;
(3) after described on-off element was opened, the needs that described regulated power supply draws inclined to one side power supply to give by described on-off element output drew inclined to one side power supply;
(4) output amplitude of the described regulated power supply of adjustment is to realize that described needs are drawn drawing partially of inclined to one side power supply.
Further, in the step (2), when between described electrifying timing sequence control circuit and on-off element, being provided with driving circuit, described electrifying timing sequence control circuit requires the described switching signal of output to give described driving circuit according to powering on of described system under test (SUT) or veneer, and described driving circuit generates drive signal according to described switching signal and sends to described on-off element.
Further, in the step (2), when described on-off element is a field effect transistor, when described driving circuit is the field effect transistor driving circuit, described electrifying timing sequence control circuit is exported described switching signal according to the electrifying timing sequence of setting and is given described field effect transistor driving circuit, described field effect transistor driving circuit output drive signal is given described field effect transistor, and described drive signal is used to control the open-minded of described field effect transistor.
Further, in the step (3), described regulated power supply is set power supply by described field effect transistor output and is drawn inclined to one side power supply for described needs, and the electrifying timing sequence of described setting power supply is controlled by described electrifying timing sequence control circuit.
Further, in the step (4), system under test (SUT) or Board Power up draw inclined to one side power supply to carry out the power supply bias test by the output of adjusting described regulated power supply to the needs in described system under test (SUT) or the veneer after finishing.
Compared with prior art, the present invention has realized having reduced the complexity of system to having drawing partially of electrifying timing sequence requirement power supply in the system by a kind of simple method, has improved operability.
Description of drawings
Fig. 1 is the structural representation of electric power pulling bias testing device preferred embodiment;
Fig. 2 is the process flow diagram of the connection procedure of electric power pulling bias testing device;
Fig. 3 is the process flow diagram that powers on of system under test (SUT) or veneer.
Embodiment
With reference to the accompanying drawings, the preferred embodiments of the present invention are described in detail.
With reference to shown in Figure 1, electric power pulling bias testing device comprises field effect transistor 106, field effect transistor driving circuit 105, electrifying timing sequence control circuit 104, regulated power supply 107.
In system under test (SUT) or veneer 101, power module 102 draws inclined to one side power supply 103 power supplies to needs, and the electrifying timing sequence of system under test (SUT) or veneer 101 is subjected to the control of electrifying timing sequence control circuit 104.
Wherein electrifying timing sequence control circuit 104 is according to the requirement that powers on of system under test (SUT) or veneer 101, output switching signal is given field effect transistor driving circuit 105, field effect transistor driving circuit 105 generates drive signal according to switching signal, and this drive signal is used to control the open-minded of field effect transistor 106; Regulated power supply 107 is given in system under test (SUT) or the veneer 101 by field effect transistor 106 out-put supplies needs to draw inclined to one side power supply 103.
Herein, field effect transistor 106 can replace with power switch pipe or suitable relay as on-off element.If do on-off element with relay, relay need be selected the suitable current switching capability, and age limit is arranged, and requires relay also to be not suitable for if having to have delayed.
With reference to shown in Figure 2, draw preceding partially connection procedure to be described further to electric power pulling bias testing device.
Step S201: at first draw the power module 102 of inclined to one side power supply 103 power supplies to remove with needing in the system.
Step S202: judge whether the last electric control signal in the electrifying timing sequence control circuit 104 can drive field effect transistor 106.
Find the last electric control signal that need draw inclined to one side power supply 103 from power in the sequential control circuit 104, export to field effect transistor driving circuit 105, judge whether the last electric control signal in the electrifying timing sequence control circuit 104 can directly drive field effect transistor 106.If can directly drive field effect transistor 106, carry out step S203, otherwise carry out step S204.
Step S203: if the last electric control signal in the electrifying timing sequence control circuit 104 can directly drive field effect transistor 106, then can save field effect transistor driving circuit 105, the last electric control signal (being switching signal) of electrifying timing sequence control circuit 104 directly be outputed to the grid of field effect transistor 106.
Step S204:, then need to drive field effect transistor 106 with field effect tube drive circuit 105 if the last electric control signal in the electrifying timing sequence control circuit 104 cannot directly drive field effect transistor 106.
Step S205: the grid of the drive signal of the output of field effect transistor driving circuit 105 being received field effect transistor 106.
Step S206: judge that field effect transistor 106 is N channel field-effect pipe or P road ditch field effect transistor.
If field effect transistor 106 is N channel field-effect pipes, carry out step S207; If field effect transistor 106 is P road ditch field effect transistor, carry out step S209.
Step S207: the positive pole of regulated power supply 107 is received field effect transistor 106 drain electrodes.
Step S208: the source electrode of field effect transistor 106 is received the positive pole (VCC) that need draw inclined to one side power supply 103.
Step S209: if field effect transistor 106 is field effect transistor of P raceway groove, then the positive pole of regulated power supply 107 is received field effect transistor 106 source electrodes (drawn field effect transistor 106 is field effect transistor of N raceway groove among Fig. 1, so the positive pole of regulated power supply 107 is received field effect transistor 106 drain electrodes).
Step S210: the drain electrode of drawing the pin of the positive source (VCC) of inclined to one side power supply 103 to receive field effect transistor 106 needs.
Step S211: the negative pole of regulated power supply 107 is connected with the ground that need draw inclined to one side power supply 103 (GND).
If have multiple power supplies need draw partially in system under test (SUT) or the veneer 101, then increase multichannel regulated power supply 107, field effect transistor driving circuit 105 and field effect transistor 106 according to the method described above.
With reference to shown in Figure 3, the power supply electrifying process of system under test (SUT) or veneer 101 is described in detail.
1, opens regulated power supply 107, adjust its output voltage to field effect pipe 106 required voltage amplitudes.
Step S301: give regulated power supply 107 energisings.
Step S302: the output voltage of regulated power supply is adjusted to the amplitude that needs.
If this moment, system under test (SUT) or veneer 101 did not also power on, then not output of electrifying timing sequence control circuit 104, field effect transistor 106 is in off state, need draw this moment inclined to one side power supply 103 not have the power supply input.
Step S303: power up for system under test (SUT) or veneer 101.
2, after system under test (SUT) or veneer 101 energisings, electrifying timing sequence control circuit 104 can be given field effect transistor driving circuit 105 according to the electrifying timing sequence output switching signal of default, thereby control field effect transistor 106 is open-minded.
Step S304: electrifying timing sequence control circuit 104 is opened needed power supply according to the order of setting.
When opening need draw inclined to one side power supply 103 time, electrifying timing sequence control circuit 104 is exported to 105 1 switching signals of field effect transistor driving circuit, and field effect transistor driving circuit 105 produces a drive signal according to this switching signal and sends to field effect transistor 106.If switching signal can directly drive field effect transistor 106, directly give field effect transistor 106 with this switching signal.
Step S305: after receiving drive signal, field effect transistor 106 is open-minded.
3, after field effect transistor 106 was opened, regulated power supply 107 was given system under test (SUT) or veneer 101 by field effect transistor 106 output required voltages.
Step S306: regulated power supply 107 is exported to by field effect transistor 106 need draw 103 1 power supplys that configure of inclined to one side power supply.
This power supply is opened according to electrifying timing sequence control circuit 104 in system under test (SUT) or the veneer 101, can not influence the startup of system under test (SUT) or veneer 101.
Step S307: system under test (SUT) or veneer 101 end that powers on.
4, realize drawing partially by the output voltage of adjusting regulated power supply 107 to one-board power supply.
Step S308: after system under test (SUT) or veneer 101 power on and finish, can draw inclined to one side power supply 103 to carry out the power supply bias test to the needs in system under test (SUT) or the veneer 101 by the output voltage of adjusting regulated power supply 107.
The flow process that powers on finishes.
Claims (10)
1. an electric power pulling bias testing device is characterized in that, comprises regulated power supply, electrifying timing sequence control circuit and on-off element, and wherein, described regulated power supply is connected with described on-off element, is used for providing power supply to described on-off element; Described electrifying timing sequence control circuit is used for output switching signal and gives described on-off element, and described switching signal generates according to the electrifying timing sequence of setting, and is used to control the open-minded of described on-off element; Described regulated power supply draws inclined to one side power supply by the output of described on-off element, describedly draws inclined to one side power supply to be used to realize needs are drawn drawing partially of inclined to one side power supply.
2. electric power pulling bias testing device according to claim 1 is characterized in that, is provided with driving circuit between described electrifying timing sequence control circuit and on-off element, and described driving circuit is used to drive the open-minded of described on-off element; Described electrifying timing sequence control circuit requires the described switching signal of output to give described driving circuit according to powering on of system under test (SUT) or veneer, described driving circuit generates drive signal according to described switching signal and sends to described on-off element, and the electrifying timing sequence of described system under test (SUT) or veneer is controlled by described electrifying timing sequence control circuit.
3. electric power pulling bias testing device according to claim 2 is characterized in that, described on-off element is a field effect transistor, and described driving circuit is the field effect transistor driving circuit; Described electrifying timing sequence control circuit is exported described switching signal according to the electrifying timing sequence of setting and is given the field effect transistor driving circuit, thereby the control field effect transistor is open-minded.
4. electric power pulling bias testing device according to claim 3 is characterized in that, the grid of described field effect transistor driving circuit and described field effect transistor is connected, and the negative pole of described regulated power supply draws the ground of inclined to one side power supply to be connected with described needs.
5. electric power pulling bias testing device according to claim 4, it is characterized in that, described field effect transistor is a N channel field-effect pipe, the positive pole of described regulated power supply is connected with the drain electrode of described N channel field-effect pipe, and the source electrode of described N channel field-effect pipe draws the positive pole of inclined to one side power supply to be connected with described needs; Perhaps, described field effect transistor is a P road ditch field effect transistor, and the positive pole of described regulated power supply is connected with the source electrode of described P road ditch field effect transistor, and described needs draw the positive pole of inclined to one side power supply and the drain electrode of described P road ditch field effect transistor to be connected.
6. electric power pulling bias testing method, step comprises:
(1) regulated power supply is powered to field effect transistor, and the output of adjusting described regulated power supply reaches the amplitude that on-off element needs;
(2) after the energising of system under test (SUT) or veneer, the electrifying timing sequence control circuit is given described on-off element according to the electrifying timing sequence output switching signal of setting, and described switching signal is used to control the open-minded of described on-off element;
(3) after described on-off element was opened, the needs that described regulated power supply draws inclined to one side power supply to give by described on-off element output drew inclined to one side power supply;
(4) output amplitude of the described regulated power supply of adjustment is to realize that described needs are drawn drawing partially of inclined to one side power supply.
7. electric power pulling bias testing method according to claim 6, it is characterized in that, in the step (2), when between described electrifying timing sequence control circuit and on-off element, being provided with driving circuit, described electrifying timing sequence control circuit requires the described switching signal of output to give described driving circuit according to powering on of described system under test (SUT) or veneer, and described driving circuit generates drive signal according to described switching signal and sends to described on-off element.
8. electric power pulling bias testing method according to claim 7, it is characterized in that, in the step (2), when described on-off element is a field effect transistor, when described driving circuit is the field effect transistor driving circuit, described electrifying timing sequence control circuit is exported described switching signal according to the electrifying timing sequence of setting and is given described field effect transistor driving circuit, and described field effect transistor driving circuit output drive signal is given described field effect transistor, and described drive signal is used to control the open-minded of described field effect transistor.
9. electric power pulling bias testing method according to claim 8, it is characterized in that, in the step (3), described regulated power supply is set power supply by described field effect transistor output and is drawn inclined to one side power supply for described needs, and the electrifying timing sequence of described setting power supply is controlled by described electrifying timing sequence control circuit.
10. electric power pulling bias testing method according to claim 6, it is characterized in that, in the step (4), system under test (SUT) or Board Power up draw inclined to one side power supply to carry out the power supply bias test by the output of adjusting described regulated power supply to the needs in described system under test (SUT) or the veneer after finishing.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2007101881815A CN100573468C (en) | 2007-11-12 | 2007-11-12 | Electric power pulling bias testing device and method of testing thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2007101881815A CN100573468C (en) | 2007-11-12 | 2007-11-12 | Electric power pulling bias testing device and method of testing thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101162433A true CN101162433A (en) | 2008-04-16 |
| CN100573468C CN100573468C (en) | 2009-12-23 |
Family
ID=39297360
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2007101881815A Active CN100573468C (en) | 2007-11-12 | 2007-11-12 | Electric power pulling bias testing device and method of testing thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN100573468C (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102339650A (en) * | 2011-10-20 | 2012-02-01 | 中兴通讯股份有限公司 | Memory bank testing device and method |
| CN104950265A (en) * | 2015-05-29 | 2015-09-30 | 上海斐讯数据通信技术有限公司 | Automatic testing method and automatic testing system for power source drawing deflection |
-
2007
- 2007-11-12 CN CNB2007101881815A patent/CN100573468C/en active Active
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102339650A (en) * | 2011-10-20 | 2012-02-01 | 中兴通讯股份有限公司 | Memory bank testing device and method |
| CN104950265A (en) * | 2015-05-29 | 2015-09-30 | 上海斐讯数据通信技术有限公司 | Automatic testing method and automatic testing system for power source drawing deflection |
| CN104950265B (en) * | 2015-05-29 | 2018-07-13 | 上海斐讯数据通信技术有限公司 | Draw the automatic test approach and system of inclined power supply |
Also Published As
| Publication number | Publication date |
|---|---|
| CN100573468C (en) | 2009-12-23 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN102243618B (en) | Universal serial bus device, bus interfacing device and related method | |
| KR101620345B1 (en) | LDO regulator and semiconductor device having the same | |
| TWI337799B (en) | ||
| CN100587646C (en) | Voltage supply circuit, power supply circuit, microphone unit, and sensitivity adjustment method | |
| US8255718B2 (en) | Power saving system and method employed in computer | |
| CN107209524B (en) | Linear power supply and the electronic device for using it | |
| US20100259106A1 (en) | Switching control method capable of continuously providing power and related apparatus and power supply system | |
| CN105794111B (en) | Electric current is controlled during powered up and down sequence | |
| TW200630627A (en) | Testing apparatus and power source circuits | |
| US7378896B2 (en) | Single pin for multiple functional control purposes | |
| US8850175B2 (en) | Computer apparatus and resetting method for real time clock thereof | |
| CN103576816B (en) | Switching on and shutting down control circuit | |
| CN108964648A (en) | A kind of time sequence control device and method | |
| CN100573468C (en) | Electric power pulling bias testing device and method of testing thereof | |
| US20100250983A1 (en) | Power saving control system | |
| CN103699175A (en) | Mainboard | |
| CN110703892A (en) | EC reset circuit and electronic equipment based on USB C type interface | |
| US20030122531A1 (en) | Switched mode power supply device adapted for low current drains, and cellular phone equipped with such a device | |
| US8250391B2 (en) | Method and system of improving memory power efficiency | |
| CN109491447A (en) | A kind of start-up circuit applied to band-gap reference circuit | |
| CN104104331A (en) | Transconductance enhancement circuit unit and crystal oscillator circuit | |
| TWI242325B (en) | Overvoltage protection apparatus | |
| CN111884498A (en) | Power-down time sequence control circuit and method for multi-channel power supply of indoor distribution system | |
| CN101399525B (en) | Voltage level clamping circuit and comparator module | |
| CN108073209B (en) | Band gap reference circuit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| ASS | Succession or assignment of patent right |
Owner name: STATE GRID SHANGHAI ELECTRIC POWER COMPANY Free format text: FORMER OWNER: ZTE CORPORATION Effective date: 20150105 |
|
| C41 | Transfer of patent application or patent right or utility model | ||
| COR | Change of bibliographic data |
Free format text: CORRECT: ADDRESS; FROM: 518057 SHENZHEN, GUANGDONG PROVINCE TO: 200122 PUDONG NEW AREA, SHANGHAI |
|
| TR01 | Transfer of patent right |
Effective date of registration: 20150105 Address after: 200122 Shanghai City, Pudong New Area source deep road, No. 1122 Patentee after: State Grid Shanghai Municipal Electric Power Company Address before: 518057 Nanshan District high tech Industrial Park, Guangdong, South Road, science and technology, ZTE building, legal department Patentee before: ZTE Corporation |