CN101159276B - Pixel structure and manufacturing method therefor - Google Patents
Pixel structure and manufacturing method therefor Download PDFInfo
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- CN101159276B CN101159276B CN2007101870238A CN200710187023A CN101159276B CN 101159276 B CN101159276 B CN 101159276B CN 2007101870238 A CN2007101870238 A CN 2007101870238A CN 200710187023 A CN200710187023 A CN 200710187023A CN 101159276 B CN101159276 B CN 101159276B
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Abstract
The invention relates to a pixel structure and a manufacturing method thereof. The manufacturing method comprises (1) carrying out a first photomask process to form a first patterned metal layer on a substrate, wherein the first metal layer comprises a grid electrode; (2) carrying out a second photomask process to form a patterned insulating layer and a patterned semiconductor layer above the grid electrode, wherein the patterned insulating layer is positioned on the first metal layer, and the patterned semiconductor layer is positioned on the patterned insulating layer; and (3) carrying out a third photomask process to define a thin-film transistor and a pixel electrode coupled with the thin-film transistor and form a protective layer for covering the thin-film transistor. The invention can save a large amount of time and raw materials in process, remarkably reduce the overall production cost, and reduce supply time.
Description
Technical field
The present invention relates to a kind of dot structure and manufacture method thereof, and be particularly related to dot structure and manufacture method thereof that a kind of use three road photo-marsk processes are finished.
Background technology
Along with the evolution of flat-panel screens industrial technology, the panel manufacturer also seeks new manufacturing technology one after another and reduces manufacturing cost, to start out bigger demand market.Wherein, the thin film transistor base plate in order to control is the key component that influences the panel quality in the panel.Therefore, how to take into account under the quality prerequisite of finished product element, changing technology, just becoming the emphasis of each tame manufacturer active development to reduce production costs.
A slice thin film transistor base plate approximately needs the photo-marsk process in five roads or four roads traditionally.But each road photo-marsk process all must very expend time in and Material Cost through steps such as deposition source material, formation photoresist, exposure, development, etchings.
Summary of the invention
The present invention relates to a kind of dot structure and manufacture method thereof, only need three road photo-marsk processes can finish thin-film transistor and holding wire, connect structure such as pad, can save many times and Material Cost.
According to the present invention, a kind of dot structure is proposed, comprise thin-film transistor and pixel electrode.Thin-film transistor is arranged on the substrate, comprises grid, insulating barrier, semiconductor layer, source electrode and drain electrode.Grid is formed in the first road photo-marsk process process; Insulating barrier is arranged on the grid, is formed in the second road photo-marsk process process; Semiconductor layer is arranged on the insulating barrier, is formed in the second road photo-marsk process process; Source electrode and drain electrode are arranged on the semiconductor layer, are formed in the 3rd road photo-marsk process process.Pixel electrode is arranged on the substrate and is electrically connected at thin-film transistor, is formed in the 3rd road photo-marsk process process, and pixel electrode is polycrystalline attitude (poly) metal oxide.
In the above-mentioned dot structure, this semiconductor layer can comprise semiconductor channel layer and ohmic contact layer.
In the above-mentioned dot structure, this thin-film transistor also can comprise: metal oxide layer, be arranged between this semiconductor layer and this source electrode and this drain electrode, and this drain electrode electrically connects this pixel electrode via this metal oxide layer.
In the above-mentioned dot structure, this metal oxide layer and this pixel electrode can be made of same rete.
In the above-mentioned dot structure, the material of this metal oxide layer and this pixel electrode can be indium tin oxide.
Above-mentioned dot structure also can comprise: protective layer, cover this thin-film transistor, and this protective layer is a photo anti-corrosion agent material.
Above-mentioned dot structure also can comprise: scan line, be electrically connected at this grid, and wherein this insulating barrier also is arranged on this scan line, and this pixel electrode part covers the insulating barrier on this scan line, to form electric capacity.
Above-mentioned dot structure also can comprise: data wire, constitute by metal level and metal oxide layer, and wherein this data wire is electrically connected at this source electrode, and this metal level is arranged on this data metal oxide layer.
Above-mentioned dot structure also can comprise: protective layer, be covered on this data wire, and this protective layer is a photo anti-corrosion agent material.
According to the present invention, a kind of one pixel structure process method is proposed, comprise the following steps.At first be step a, carry out the first road photo-marsk process, to form the patterning the first metal layer on substrate, the patterning the first metal layer comprises grid.Then be step b, carry out the second road photo-marsk process, to form patterned insulation layer and patterned semiconductor layer in the grid top, patterned insulation layer is positioned on the patterning the first metal layer, and patterned semiconductor layer is positioned on the patterned insulation layer.Be step c then, carry out the 3rd road photo-marsk process,, and form protective layer cover film transistor with the pixel electrode that defines thin-film transistor and couple with thin-film transistor.
In the above-mentioned manufacture method, step a can may further comprise the steps: deposition first metal material layer on this substrate; On this first metal material layer, form the first pattern photoresist layer; With this first pattern photoresist layer is mask, and this first metal material layer of etching is to form this patterning the first metal layer.
In the above-mentioned manufacture method, step b can may further comprise the steps: deposition of insulative material layer on this patterning the first metal layer; Deposited semiconductor material layer on this insulation material layer; Form the second pattern photoresist layer on this semiconductor material layer, this second pattern photoresist layer has first thickness and second thickness, and this first thickness is greater than this second thickness; With this second pattern photoresist layer is mask, and this semiconductor material layer of etching and this insulation material layer are to form this patterned insulation layer and this patterned semiconductor layer; Remove this second pattern photoresist layer with cineration technics, with this patterned semiconductor layer of exposed portions serve with this second thickness; This patterned semiconductor layer of etching exposed portions serve; And remove remaining this second pattern photoresist layer.
In the above-mentioned manufacture method, this patterned semiconductor layer can comprise semiconductor channel layer and be positioned at ohmic contact layer on this semiconductor channel layer that step c can may further comprise the steps: form metal oxide layer on this ohmic contact layer; On this metal oxide layer, form second metal level; Form the 3rd pattern photoresist layer on this second metal level, the 3rd pattern photoresist layer has the 3rd thickness and the 4th thickness, and the 3rd thickness is greater than the 4th thickness; With the 3rd pattern photoresist layer is mask, and this second metal level of etching and this metal oxide layer are with this ohmic contact layer of exposed portions serve; And this ohmic contact layer of etching exposed portions serve.
In the above-mentioned manufacture method, step c also can may further comprise the steps: remove the 3rd patterning photoresist layer with the 4th thickness with cineration technics, with this second metal level of exposed portions serve; And this remaining the 3rd pattern photoresist layer is flowed again, to form this protective layer.
In the above-mentioned manufacture method, step c also can may further comprise the steps: this metal oxide layer crystallization is become polycrystalline attitude metal oxide; And this second metal level of etching exposed portions serve, with source electrode and the drain electrode that forms this thin-film transistor, and expose this metal oxide layer partly, as this pixel electrode.
In the above-mentioned manufacture method, the temperature of this metal oxide layer of crystallization can be greater than 200 ℃.
According to the present invention, reintroduce a kind of one pixel structure process method, comprise the following steps.At first, provide substrate, substrate has pixel region.Then, on substrate, form the patterning the first metal layer.Then, form insulating barrier and semiconductor layer, wherein insulating barrier is positioned on the patterning the first metal layer of pixel region, and semiconductor layer is positioned on the insulating barrier.Then, on substrate, form metal oxide layer, and this metal oxide layer overlay pattern the first metal layer, semiconductor layer and insulating barrier.Then, on metal oxide layer, form second metal level.Then, via half-tone type photomask (halftone mask) or grey modulation type photomask (gray-tone mask) the patterning metal oxide layer and second metal level, with data wire and the pixel electrode that forms thin-film transistor and couple with thin-film transistor.Then, (reflow) photo anti-corrosion agent material that flows again is to form the protective layer of cover film transistor AND gate data wire.
In the above-mentioned manufacture method, the step that forms this patterning metal level on this substrate can may further comprise the steps: deposition first metal material layer on this substrate; On this first metal material layer, form the first pattern photoresist layer; This first metal material layer of etching, to form this patterning the first metal layer, wherein this patterning the first metal layer comprises scan line, is coupled to the grid of this scan line and scans connection pad and data connection pad.
In the above-mentioned manufacture method, the step that forms this insulating barrier and this semiconductor layer can may further comprise the steps: deposition of insulative material layer on this patterning the first metal layer; Deposited semiconductor material layer on this insulation material layer; Form the second pattern photoresist layer on this semiconductor material layer, this second pattern photoresist layer has first thickness and second thickness, and this first thickness is greater than this second thickness; With this second pattern photoresist layer is mask, and this semiconductor material layer of etching and this insulation material layer are to form this insulating barrier and this patterned semiconductor layer on this scan line and this grid; Remove this second pattern photoresist layer with cineration technics, to expose this patterned semiconductor layer that is positioned on this scan line with this second thickness; Etching is positioned at this patterned semiconductor layer on this scan line, is positioned at this semiconductor layer on this grid with formation; And remove remaining this second pattern photoresist layer.
In the above-mentioned manufacture method, this semiconductor layer can comprise semiconductor channel layer and be positioned at ohmic contact layer on this semiconductor channel layer, and can may further comprise the steps via this half-tone type photomask or this this metal oxide layer of grey mode optical mask patternization and this second metal level and the step that forms this protective layer: on this second metal level, form the 3rd pattern photoresist layer, the 3rd pattern photoresist layer has the 3rd thickness and the 4th thickness, and the 3rd thickness is greater than the 4th thickness; With the 3rd pattern photoresist layer is mask, and this second metal level of etching and this metal oxide layer are with this ohmic contact layer of exposed portions serve; This ohmic contact layer of etching exposed portions serve; Remove the 3rd patterning photoresist layer with cineration technics, to expose this second metal level of this pixel electrode, this scanning connection pad and this data connection pad top with the 4th thickness; Make this remaining the 3rd pattern photoresist layer flow again, to form this protective layer; This metal oxide layer crystallization is become polycrystalline attitude metal oxide; And be mask with this protective layer, this second metal level that etching is exposed is to expose this pixel electrode and to be positioned at this scanning connection pad and this metal oxide layer of this data connection pad top.
In the above-mentioned manufacture method, the temperature of this metal oxide layer of crystallization can be greater than 200 ℃.
The present invention can save many times and former material on technology, significantly reduce whole production cost and reduce the supply time.
For foregoing of the present invention can be become apparent, below elaborate especially exemplified by preferred embodiment and conjunction with figs..
Description of drawings
Fig. 1 illustrates one pixel structure process method of the present invention;
Fig. 2 A illustrates the plane graph according to the first road photo-marsk process of a kind of dot structure manufacture method of one embodiment of the present invention;
Fig. 2 B illustrates along the profile of Fig. 2 A section line AA ' and BB ';
Fig. 3 A illustrates the plane graph according to the second road photo-marsk process of a kind of dot structure manufacture method of one embodiment of the present invention;
Fig. 3 B-Fig. 3 E illustrates along the manufacturing process profile of Fig. 3 A section line AA ' and BB ';
Fig. 4 A illustrates the plane graph according to the first step of the 3rd road photo-marsk process of a kind of dot structure manufacture method of one embodiment of the present invention;
Fig. 4 B illustrates along the manufacturing process profile of Fig. 4 A section line AA ' and BB ';
Fig. 5 A illustrates the plane graph according to second step of the 3rd road photo-marsk process of a kind of dot structure manufacture method of one embodiment of the present invention;
Fig. 5 B illustrates along the manufacturing process profile of Fig. 5 A section line AA ' and BB ';
Fig. 6 A illustrates the plane graph according to the third step of the 3rd road photo-marsk process of a kind of dot structure manufacture method of one embodiment of the present invention;
Fig. 6 B-Fig. 6 D illustrates along the manufacturing process profile of Fig. 6 A section line AA ' and BB ';
Fig. 7 A illustrates the plane graph according to the 4th step of the 3rd road photo-marsk process of a kind of dot structure manufacture method of one embodiment of the present invention; And
Fig. 7 B-Fig. 7 C illustrates along the manufacturing process profile of Fig. 7 A section line AA ' and BB '.
Wherein, description of reference numerals is as follows:
10: substrate
10a: pixel region
20: thin-film transistor
20a: source electrode
20b: drain electrode
21: data wire
22: scan line
28: pixel electrode area
30,32: pixel electrode
40: the second electrodes
100: the patterning the first metal layer
102: the scanning connection pad
104: grid
106: the first electrodes
108: the data connection pad
210: insulation material layer
210a: insulating barrier
220: semiconductor material layer
220a: patterned semiconductor layer
220b: semiconductor layer
222,222a, 222b: semiconductor channel layer
224,224a, 224b, 224c: ohmic contact layer
230,230a, 230b, 230c: the second pattern photoresist layer
310,310a: metal oxide layer
320,320a: second metal level
330,330a, 330b, 330c: the 3rd pattern photoresist layer
340: protective layer
Embodiment
Please refer to Fig. 1, it illustrates one pixel structure process method of the present invention.And please refer to Fig. 2 A and Fig. 2 B, Fig. 2 A illustrates the plane graph according to the execution first road photo-marsk process of a kind of dot structure manufacture method of one embodiment of the present invention, and Fig. 2 B is the profile along Fig. 2 A section line AA ' and BB '.Please refer to Fig. 2 A, shown in step 1, carry out the first road photo-marsk process, the substrate 10 with pixel region 10a is provided, on substrate 10, to form patterning the first metal layer 100.Shown in Fig. 2 B, in the first road photo-marsk process, at first on substrate 10, deposit the first metal material layer (not shown).Then, on first metal material layer, form the first pattern photoresist layer (not shown).Then, be mask with the first pattern photoresist layer, etching first metal material layer is to form patterning the first metal layer 100 on substrate 10.Shown in Fig. 2 A, patterning the first metal layer 100 comprises scan line 22, is coupled to the grid 104 and scanning connection pad 102, data connection pad 108 and first electrode 106 of scan line 22.
Please refer to Fig. 3 A-Fig. 3 E, Fig. 3 A illustrates the plane graph according to the execution second road photo-marsk process of a kind of dot structure manufacture method of one embodiment of the present invention, and Fig. 3 B-Fig. 3 E illustrates along the manufacturing process profile of Fig. 3 A section line AA ' and BB '.Shown in Fig. 3 B, at first, deposition of insulative material layer 210 on patterning the first metal layer 100.Then, deposited semiconductor material layer 220 on insulation material layer 210, semiconductor material layer 220 comprises semiconductor channel layer 222 and ohmic contact layer 224, and wherein the material of semiconductor channel layer 222 is an amorphous silicon for example, and the material of ohmic contact layer 224 for example is the n+ amorphous silicon.Then, on semiconductor material layer 220, form the second pattern photoresist layer 230.The second pattern photoresist layer 230 forms by half-tone type photomask or grey modulation type photomask, and the second pattern photoresist layer 230 comprises the second pattern photoresist layer 230a and the second pattern photoresist layer 230b.Wherein the second pattern photoresist layer 230a has thickness t 1 and the second pattern photoresist layer 230b has thickness t 2, lay respectively at grid 104 and first electrode, 106 tops, and thickness t 1 is greater than thickness t 2.
Shown in Fig. 3 C, then, with the second pattern photoresist layer 230 is mask etching semiconductor material layer 220 and insulation material layer 210, to form patterned insulation layer 210a and patterned semiconductor layer 220a above the grid 104 and first electrode 106, wherein patterned semiconductor layer 220a comprises semiconductor channel layer 222a and ohmic contact layer 224a.
Shown in Fig. 3 D, then, carry out ashing (ashing) technology to reduce the thickness of the second pattern photoresist layer 230, removed fully up to the second pattern photoresist layer 230b with thickness t 2, be positioned at the patterned semiconductor layer 220a on first electrode 106 of scan line 22 with exposed portions serve, and staying the second pattern photoresist layer 230c partly, the second pattern photoresist layer 230c has thickness t 3.
Then, be etched in the patterned semiconductor layer 220a that exposes on the scan line 22 (first electrode 106), to expose patterned insulation layer 210a, shown in Fig. 3 E.Then, remove the remaining second pattern photoresist layer 230c, on grid 104, to form the patterned semiconductor layer 220b that comprises ohmic contact layer 224b and semiconductor channel layer 222b, shown in Fig. 3 E and Fig. 3 A.Therefore, shown in the step 2 of Fig. 1, form patterned insulation layer 210a and patterned semiconductor layer 220b in the second road photo-marsk process, patterned insulation layer 210a is positioned on the patterning the first metal layer 100 of part, and patterned semiconductor layer 220b is positioned on the patterned insulation layer 210a of grid 104 tops.
Please refer to Fig. 4 A and Fig. 4 B, Fig. 4 A illustrates the plane graph according to the first step of execution the 3rd road photo-marsk process of a kind of dot structure manufacture method of one embodiment of the present invention, and Fig. 4 B illustrates along the manufacturing process profile of Fig. 4 A section line AA ' and BB '.Shown in Fig. 4 B, at first, on the ohmic contact layer 224b of patterning the first metal layer 100, patterned semiconductor layer 220b and patterned insulation layer 210a, form metal oxide layer 310, the material of metal oxide layer 310 be preferably indium tin oxide (indium tin oxide, ITO).Then, on metal oxide layer 310, form second metal level 320.Then, on second metal level 320, form the 3rd pattern photoresist layer 330, the three pattern photoresist layer 330 and comprise the 3rd pattern photoresist layer 330a and the 3rd pattern photoresist layer 330b with thickness t 4 via half-tone type photomask or grey modulation type photomask; Wherein the 3rd pattern photoresist layer 330a has thickness t 4 and the 3rd pattern photoresist layer 330b has thickness t 5, and thickness t 4 is greater than thickness t 5.Shown in Fig. 4 A, the 3rd thin pattern photoresist layer 330b is covered in zone, scanning connection pad 102 and data connection pad 108 tops that preboarding becomes pixel electrode, and the 3rd thicker pattern photoresist layer 330a is covered in the predetermined source electrode and drain electrode top that forms data wire and thin-film transistor.
Please refer to Fig. 5 A and Fig. 5 B, Fig. 5 A illustrates the plane graph according to second step of execution the 3rd road photo-marsk process of a kind of dot structure manufacture method of one embodiment of the present invention, and Fig. 5 B illustrates along the manufacturing process profile of Fig. 5 A section line AA ' and BB '.Shown in Fig. 5 B, at first, with the 3rd pattern photoresist layer 330 is mask, with second metal level 320 and metal oxide layer 310 etchings becoming patterning second metal level 320a and patterning metal oxide layer 310a, to expose the ohmic contact layer 224b of grid 104 upper sections.
Please refer to Fig. 6 A-Fig. 6 D, Fig. 6 A illustrates the plane graph according to the third step of execution the 3rd road photo-marsk process of a kind of dot structure manufacture method of one embodiment of the present invention, and Fig. 6 B-Fig. 6 D illustrates along the manufacturing process profile of Fig. 6 A section line AA ' and BB '.Shown in Fig. 6 B, at first, the ohmic contact layer 224b of etching exposed portions serve with formation ohmic contact layer 224c, and exposes semiconductor channel layer 222b.
Shown in Fig. 6 C, then, carry out cineration technics to reduce the thickness of the 3rd pattern photoresist layer 330, removed fully up to the 3rd patterning photoresist layer 330b with thickness t 5, the patterning second metal level 320a that comprise pixel electrode area 28 to expose, scans connection pad 102 and data connection pad 108 tops, and stay the 3rd patterning photoresist layer 330c with thickness t 6.As shown in Figure 6A, the data wire 21 that forms thin-film transistor 20 and couple, and the pixel electrode area 28 that comprises the second metal level 320a and metal oxide layer 310a with thin-film transistor 20.
Shown in Fig. 6 D, then, make remaining the 3rd pattern photoresist layer 330c flow again, to form protective layer 340.This step makes photo anti-corrosion agent material softening in the mode of heating, makes it mobile naturally and cover thin-film transistor 20 and data wire 21 tops.
Please refer to Fig. 7 A-Fig. 7 C, Fig. 7 A illustrates the plane graph according to the 4th step of the 3rd road photo-marsk process of a kind of dot structure manufacture method of one embodiment of the present invention, and Fig. 7 B-Fig. 7 C illustrates along the manufacturing process profile of Fig. 7 A section line AA ' and BB '.Shown in Fig. 7 B, at first, metal oxide layer 310a crystallization (crystallize) is become polycrystalline attitude metal oxide 310b.Wherein, in order to the temperature of crystallization metal oxide layer 310a greater than 200 ℃.
Shown in Fig. 7 C, then, the patterning second metal level 320a of etching exposed portions serve, with the pixel electrode 30,32 that exposes the polycrystalline attitude, wherein pixel electrode 32 parts are covered on the insulating barrier 210a of this scan line 22, please be simultaneously with reference to shown in Fig. 7 A.First electrode 106, insulating barrier 210a and second electrode 40 constitute storage capacitors, and wherein second electrode 40 is the part of another pixel electrode 32.Thin-film transistor 20 comprises grid 104, insulating barrier 210a, semiconductor channel layer 222b, ohmic contact layer 224c, source electrode 20a and drain electrode 20b.Insulating barrier 210a is arranged on the grid 104, and semiconductor channel layer 222b, ohmic contact layer 224c are arranged on the insulating barrier 210a.Source electrode 20a and drain electrode 20b are arranged on the ohmic contact layer 224c.Pixel electrode 30 is electrically connected at thin-film transistor 20.Scan line 22 is electrically connected at grid 104, and data wire 21 is electrically connected at source electrode 20a, and data wire 21 is made up of part second metal level and part polycrystalline attitude metal oxide layer, and the protective layer 340 that is formed by photo anti-corrosion agent material also is covered on the data wire 21.The metal oxide layer that also comprises the polycrystalline attitude in the thin-film transistor 20, the metal oxide layer of this polycrystalline attitude is arranged between ohmic contact layer 224c and source electrode 20a and the drain electrode 20b, and the polycrystalline attitude metal oxide layer of drain electrode 20b end electrically connects pixel electrode 30, and the polycrystalline attitude metal oxide layer and the pixel electrode 30 of drain electrode 20b end are made of same rete.Because the electric conducting material with polycrystalline attitude, so the whole pixel structure has better conductivity compared with traditional dot structure.Please be simultaneously with reference to Fig. 7 A and Fig. 7 C, shown in the step 3 among Fig. 1, the pixel electrode 30 and second electrode 40 that define thin-film transistor 20 in the 3rd road photo-marsk process and couple with thin-film transistor 20, and form the protective layer 340 of cover film transistor 20.
Disclosed dot structure of the above embodiment of the present invention and manufacture method thereof, only need three road photo-marsk processes can finish thin-film transistor in the dot structure and holding wire, holding wire connects structures such as pad, on technology, save many times and use former material, can significantly reduce whole production cost and reduce the supply time.
In sum, though the present invention with a preferred embodiment openly as above, yet preferred embodiment is not in order to limit the present invention.The persons of ordinary skill in the technical field of the present invention, without departing from the spirit and scope of the present invention, when doing various changes and modification.Therefore, protection scope of the present invention should be as the criterion with claims.
Claims (20)
1. dot structure comprises:
Thin-film transistor is arranged on the substrate, comprising:
Grid is formed in the first road photo-marsk process process;
Insulating barrier is arranged on this grid, is formed in the second road photo-marsk process process;
Semiconductor layer is arranged on this insulating barrier, is formed in the second road photo-marsk process process;
Source electrode and drain electrode are arranged on this semiconductor layer, are formed in the 3rd road photo-marsk process process; And
Metal oxide layer is arranged between this semiconductor layer and this source electrode and this drain electrode; And
Pixel electrode is arranged on this substrate, is electrically connected at this thin-film transistor, is formed in the 3rd road photo-marsk process process, and this pixel electrode is a polycrystalline attitude metal oxide, and this drain electrode electrically connects this pixel electrode via this metal oxide layer.
2. dot structure as claimed in claim 1, wherein this semiconductor layer comprises semiconductor channel layer and ohmic contact layer.
3. dot structure as claimed in claim 2, wherein this metal oxide layer and this pixel electrode are made of same rete.
4. dot structure as claimed in claim 2, wherein the material of this metal oxide layer and this pixel electrode is an indium tin oxide.
5. dot structure as claimed in claim 1 also comprises: protective layer, cover this thin-film transistor, and this protective layer is a photo anti-corrosion agent material.
6. dot structure as claimed in claim 1 also comprises: scan line, be electrically connected at this grid, and wherein this insulating barrier also is arranged on this scan line, and this pixel electrode part covers the insulating barrier on this scan line, to form electric capacity.
7. dot structure as claimed in claim 1 also comprises: data wire, constitute by metal level and metal oxide layer, and wherein this data wire is electrically connected at this source electrode, and this metal level is arranged on the metal oxide layer in this data wire.
8. dot structure as claimed in claim 7 also comprises: protective layer, be covered on this data wire, and this protective layer is a photo anti-corrosion agent material.
9. one pixel structure process method may further comprise the steps:
Step a carries out the first road photo-marsk process, and to form the patterning the first metal layer on substrate, this patterning the first metal layer comprises grid;
Step b carries out the second road photo-marsk process, and to form patterned insulation layer and patterned semiconductor layer above this grid, wherein this patterned insulation layer is positioned on this patterning the first metal layer, and this patterned semiconductor layer is positioned on this patterned insulation layer; And
Step c carries out the 3rd road photo-marsk process, with the pixel electrode that defines thin-film transistor and couple with this thin-film transistor, and forms the protective layer that covers this thin-film transistor.
10. manufacture method as claimed in claim 9, wherein step a may further comprise the steps:
Deposition first metal material layer on this substrate;
On this first metal material layer, form the first pattern photoresist layer;
With this first pattern photoresist layer is mask, and this first metal material layer of etching is to form this patterning the first metal layer.
11. manufacture method as claimed in claim 9, wherein step b may further comprise the steps:
Deposition of insulative material layer on this patterning the first metal layer;
Deposited semiconductor material layer on this insulation material layer;
Form the second pattern photoresist layer on this semiconductor material layer, this second pattern photoresist layer has first thickness and second thickness, and this first thickness is greater than this second thickness;
With this second pattern photoresist layer is mask, and this semiconductor material layer of etching and this insulation material layer are to form this patterned insulation layer and this patterned semiconductor layer;
Remove this second pattern photoresist layer with cineration technics, with this patterned semiconductor layer of exposed portions serve with this second thickness;
This patterned semiconductor layer of etching exposed portions serve; And
Remove remaining this second pattern photoresist layer.
12. manufacture method as claimed in claim 9, wherein this patterned semiconductor layer comprises semiconductor channel layer and is positioned at ohmic contact layer on this semiconductor channel layer, and step c may further comprise the steps:
On this ohmic contact layer, form metal oxide layer;
On this metal oxide layer, form second metal level;
Form the 3rd pattern photoresist layer on this second metal level, the 3rd pattern photoresist layer has the 3rd thickness and the 4th thickness, and the 3rd thickness is greater than the 4th thickness;
With the 3rd pattern photoresist layer is mask, and this second metal level of etching and this metal oxide layer are with this ohmic contact layer of exposed portions serve; And
This ohmic contact layer of etching exposed portions serve.
13. manufacture method as claimed in claim 12, wherein step c is further comprising the steps of:
Remove the 3rd patterning photoresist layer with cineration technics, with this second metal level of exposed portions serve with the 4th thickness; And
This remaining the 3rd pattern photoresist layer is flowed again, to form this protective layer.
14. manufacture method as claimed in claim 13, wherein step c is further comprising the steps of:
This metal oxide layer crystallization is become polycrystalline attitude metal oxide; And
This second metal level of etching exposed portions serve with source electrode and the drain electrode that forms this thin-film transistor, and exposes this metal oxide layer partly, as this pixel electrode.
15. manufacture method as claimed in claim 14, wherein the temperature of this metal oxide layer of crystallization is greater than 200 ℃.
16. an one pixel structure process method may further comprise the steps:
Substrate is provided, and this substrate has pixel region;
On this substrate, form the patterning the first metal layer;
Form insulating barrier and semiconductor layer, wherein this insulating barrier is positioned on the patterning the first metal layer of this pixel region, and this semiconductor layer is positioned on this insulating barrier;
On this substrate, form metal oxide layer, and this metal oxide layer covers this patterning the first metal layer, this semiconductor layer and this insulating barrier;
On this metal oxide layer, form second metal level;
Via half-tone type photomask or this metal oxide layer of grey mode optical mask patternization and this second metal level, with data wire and the pixel electrode that forms thin-film transistor and couple with this thin-film transistor; And
Mobile again photo anti-corrosion agent material is to form the protective layer that covers this thin-film transistor and this data wire.
17. manufacture method as claimed in claim 16, the step that wherein forms this patterning the first metal layer on this substrate may further comprise the steps:
Deposition first metal material layer on this substrate;
On this first metal material layer, form the first pattern photoresist layer;
This first metal material layer of etching, to form this patterning the first metal layer, wherein this patterning the first metal layer comprises scan line, is coupled to the grid of this scan line and scans connection pad and data connection pad.
18. manufacture method as claimed in claim 17, the step that wherein forms this insulating barrier and this semiconductor layer may further comprise the steps:
Deposition of insulative material layer on this patterning the first metal layer;
Deposited semiconductor material layer on this insulation material layer;
Form the second pattern photoresist layer on this semiconductor material layer, this second pattern photoresist layer has first thickness and second thickness, and this first thickness is greater than this second thickness;
With this second pattern photoresist layer is mask, and this semiconductor material layer of etching and this insulation material layer are to form this insulating barrier and this patterned semiconductor layer on this scan line and this grid;
Remove this second pattern photoresist layer with cineration technics, to expose this patterned semiconductor layer that is positioned on this scan line with this second thickness;
Etching is positioned at this patterned semiconductor layer on this scan line, is positioned at this semiconductor layer on this grid with formation; And
Remove remaining this second pattern photoresist layer.
19. manufacture method as claimed in claim 17; wherein this semiconductor layer comprises semiconductor channel layer and is positioned at ohmic contact layer on this semiconductor channel layer, and may further comprise the steps via this half-tone type photomask or this this metal oxide layer of grey mode optical mask patternization and this second metal level and the step that forms this protective layer:
Form the 3rd pattern photoresist layer on this second metal level, the 3rd pattern photoresist layer has the 3rd thickness and the 4th thickness, and the 3rd thickness is greater than the 4th thickness;
With the 3rd pattern photoresist layer is mask, and this second metal level of etching and this metal oxide layer are with this ohmic contact layer of exposed portions serve;
This ohmic contact layer of etching exposed portions serve;
Remove the 3rd patterning photoresist layer with cineration technics, to expose this second metal level of this pixel electrode, this scanning connection pad and this data connection pad top with the 4th thickness;
Make this remaining the 3rd pattern photoresist layer flow again, to form this protective layer;
This metal oxide layer crystallization is become polycrystalline attitude metal oxide; And
With this protective layer is mask, and this second metal level that etching is exposed is to expose this pixel electrode and to be positioned at this scanning connection pad and this metal oxide layer of this data connection pad top.
20. manufacture method as claimed in claim 19, wherein the temperature of this metal oxide layer of crystallization is greater than 200 ℃.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2007101870238A CN101159276B (en) | 2007-11-19 | 2007-11-19 | Pixel structure and manufacturing method therefor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2007101870238A CN101159276B (en) | 2007-11-19 | 2007-11-19 | Pixel structure and manufacturing method therefor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101159276A CN101159276A (en) | 2008-04-09 |
| CN101159276B true CN101159276B (en) | 2010-09-22 |
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