CN100397213C - Manufacturing method of thin film transistor array substrate - Google Patents
Manufacturing method of thin film transistor array substrate Download PDFInfo
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- CN100397213C CN100397213C CNB2003101242245A CN200310124224A CN100397213C CN 100397213 C CN100397213 C CN 100397213C CN B2003101242245 A CNB2003101242245 A CN B2003101242245A CN 200310124224 A CN200310124224 A CN 200310124224A CN 100397213 C CN100397213 C CN 100397213C
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Abstract
The present invention relates to a fabrication method of a thin-film transistor array substrate, which comprises: firstly, a substrate which has a picture element zone and a welding pad zone is provided; a plurality of scanning wires, a plurality of data wires and a plurality of thin-film transistors are at least configured on the picture element zone; a plurality of welding pads are configured on the welding pad zone; subsequently, a protecting layer and a flat layer are orderly formed above the thin-film transistor array substrate, wherein the flat layer has a plurality of first openings and a plurality of second openings; the flat layer is provided with first thickness in the picture element zone and has second thickness in the welding pad zone, and the first thickness is larger than the second thickness; then, the flat layer is used as a cover screen, material layers in the first openings and the second openings are removed until drain poles of the thin-film transistors and the welding pads are exposed; finally, a plurality of picture element electrodes which are electrically connected to the drain poles and a plurality of electrode material layers which are electrically connected to the welding pads are formed on the flat layer.
Description
Technical field
The present invention relates to a kind of thin-film transistor array base-plate (plurality of groups of substrates of thin-film transistor) (ThinFilm Transistor array substrate; TFT array substrate) manufacture method particularly relates to a kind of manufacture method of avoiding the thin-film transistor array base-plate that metal level and protective seam be damaged when heavy industry.
Background technology
Liquid crystal display panel of thin film transistor (Thin Film Transistor Liquid CrystalDisplay panel, TFT LCD panel) constituted by thin-film transistor array base-plate (plurality of groups of substrates of thin-film transistor), colour filter array (array) substrate (Color filter array substrate) and liquid crystal layer, wherein thin-film transistor array base-plate is the thin film transistor (TFT) of being arranged with array (array) by a plurality of, and a pixel electrode (PixelElectrode) of corresponding configuration with each thin film transistor (TFT) is formed.And above-mentioned thin film transistor (TFT) is to comprise grid (Gate), channel layer (Channel), drain electrode (Drain) and source electrode (Source), and thin film transistor (TFT) is intended for the switch module of liquid crystal display.
The principle of operation of thin-film transistor component and traditional semiconductor MOS assembly are similar, all are the assemblies with three terminals (grid, drain electrode and source electrode).Usually thin-film transistor component can be divided into polysilicon (Polysilicon) and two types of amorphous silicon (Amorphous silicon) materials.Wherein, amorphous silicon film transistor is to belong to comparatively proven technique.With regard to the amorphous silicon film transistor LCD, its manufacturing process roughly is included in and forms grid, channel layer, source/drain, pixel electrode and protective seam on the substrate.
Look synoptic diagram on Fig. 1 one existing known thin-film transistor array base-plate.Fig. 2 A to Fig. 2 E is the technology of I-I ' section among Fig. 1 and the diagrammatic cross-section of structure.
See also shown in Fig. 1 and Fig. 2 A, have the manufacture method of known thin-film transistor array base-plate (thin film transistor (TFT) array multiple substrate) 100 now, be at first to carry out the first road photo-marsk process, with formation grid 112 and the connected distribution 120 that scans on substrate 50, and form weld pad 122 at the end that is scanning distribution 120 simultaneously.Afterwards, above substrate 50, cover a gate dielectric layer 130.
Then see also shown in Fig. 1 and Fig. 2 B, carry out the second road photo-marsk process, on the gate dielectric layer above the grid 112 130, to form a channel layer 114.
Then see also shown in Fig. 1 and Fig. 2 C; carry out the 3rd road photo-marsk process; with the data wiring 140 that forms source/drain 116/118 and is connected with source electrode 116, and simultaneously after the end of data wiring 140 forms another weld pad 142, covering one protective seam 150 above substrate 50.
Connect and see and see also shown in Fig. 1 and Fig. 2 D, carry out the 4th road photo-marsk process,, expose the protective seam 150 of drain electrode 118 and weld pad 122,142 tops on protective seam 150, to form the flatness layer (Planarization layer) 160 of a patterning.Subsequently, be etching mask with flatness layer 160, remove gate dielectric layer 130 and protective seam 150 on the weld pad 122,142, and remove the protective seam 150 in the drain electrode 118.
See also at last shown in Fig. 1 and Fig. 2 E, carry out the 5th road photo-marsk process, with formation pixel electrode 170 on flatness layer 160, and at weld pad 122,142 surface coverage one electrode material layer 172.
The above-mentioned purpose that forms flatness layer on protective seam is in order to improve the aperture opening ratio of LCD.Because the existence of flatness layer, pixel electrode can extend the top that covers the partial data distribution to improve aperture opening ratio, this is because the thickness of flatness layer is enough thick, therefore can avoid stray capacitance between pixel electrode and the data wiring (Parasitic capacitance) too big, and the characteristic of panel is affected.
In subsequent technique,, be that (Anisotropic Conductive Film ACF) is electrically connected to weld pad by anisotropic conductive film in order to driving data distribution and the chip for driving that scans distribution.But the technology of joint chip usually can need rework.When heavy industry, be coated with flatness layer owing to the weld pad peripheral region; if desire to remove anisotropic conductive film; regular meeting's flatness layer that material is close tears up, and then causes the destruction of below protective seam and metal level, and makes the monoblock thin-film transistor array base-plate to re-use.
This shows that the manufacture method of above-mentioned existing thin-film transistor array base-plate still has many defectives, and demands urgently further being improved.For the defective of the manufacture method that solves existing thin-film transistor array base-plate, relevant manufacturer there's no one who doesn't or isn't seeks solution painstakingly, but does not see always that for a long time suitable design finished by development, and this obviously is the problem that the anxious desire of relevant dealer solves.
Because the defective that the manufacture method of above-mentioned existing thin-film transistor array base-plate exists, the inventor is based on being engaged in this type of product design manufacturing abundant for many years practical experience and professional knowledge, actively studied innovation, in the hope of founding a kind of manufacture method of new thin-film transistor array base-plate, can improve the manufacture method of general existing thin-film transistor array base-plate, make it have more practicality.Through constantly research, design, and after studying repeatedly and improving, create the present invention who has practical value finally.
Summary of the invention
The objective of the invention is to, overcome the defective of the manufacture method existence of existing thin-film transistor array base-plate, and provide a kind of manufacture method of new thin-film transistor array base-plate (plurality of groups of substrates of thin-film transistor), technical matters to be solved is to make it be suitable for reducing the heavy industry mortality of follow-up chip join technology, thereby be suitable for practicality more, and have the value on the industry.
The object of the invention to solve the technical problems is the manufacture method of a kind of thin-film transistor array base-plate that proposes according to the present invention realized by the following technical solutions, it may further comprise the steps: a substrate is provided, have a pixel region and a pad zone, at least dispose most bar scan wirings, most bar data wiring and most thin film transistor (TFT)s on this pixel region, and dispose most weld pads on this pad zone at least with a grid, one source pole and a drain electrode; Above this substrate, form a protective seam; On this protective seam, form a flatness layer, this flatness layer has most first openings and most second openings, those first openings are to be positioned at those drain electrode tops, those second openings are to be positioned at those weld pad tops, this flatness layer that wherein is positioned at this pixel region has one first thickness, and this flatness layer that is positioned at this pad zone has one second thickness, and this first thickness is greater than this second thickness; With this flatness layer is mask, removes the material layer that those first openings and those second openings are exposed, up to exposing those drain electrodes and those weld pads; And on this flatness layer, form most pixel electrodes and most electrode material layers, wherein those pixel electrodes are to electrically connect with those drain electrodes, and those electrode material layers are to electrically connect with those weld pads.
The object of the invention to solve the technical problems also can be applied to the following technical measures to achieve further.
The manufacture method of aforesaid thin-film transistor array base-plate, wherein before removing the material layer that those first openings and those second openings exposed, this of this flatness layer first thickness is between 2～6 microns, and this of this flatness layer second thickness is between 0.3～1.4 micron.
The manufacture method of aforesaid thin-film transistor array base-plate, wherein after removing the material layer that those first openings and those second openings exposed, this of this flatness layer second thickness is less than 0.8 micron.
The manufacture method of aforesaid thin-film transistor array base-plate, the method for wherein said this flatness layer of formation comprises: form a photosensitive type dielectric layer; And use a semi-modulation type photomask that this photosensitive type dielectric layer is carried out single exposure technology.
The manufacture method of aforesaid thin-film transistor array base-plate, wherein said semi-modulation type photomask are striated semi-modulation type photomask, netted semi-modulation type photomask or point-like semi-modulation type photomask.
The manufacture method of aforesaid thin-film transistor array base-plate, the method for wherein said this flatness layer of formation comprises: form a dielectric layer; Form a patterning photoresist layer on this dielectric layer, this patterning photoresist layer has most the 3rd openings and most the 4th openings, those the 3rd openings are to be positioned at those drain electrode tops, those the 4th openings are to be positioned at those weld pad tops, this patterning photoresist layer that wherein is positioned at this pixel region has one the 3rd thickness, and this patterning photoresist layer that is positioned at this pad zone has one the 4th thickness, and the 3rd thickness is greater than the 4th thickness; With this patterning photoresist layer is mask, removes this dielectric layer that is not covered by this patterning photoresist layer, to form this flatness layer; And remove this patterning photoresist layer.
The manufacture method of aforesaid thin-film transistor array base-plate, the formation method of wherein said patterning photoresist layer comprises: form a photo anti-corrosion agent material layer on this dielectric layer; And use a semi-modulation type photomask that this photo anti-corrosion agent material layer is carried out single exposure technology, to form this patterning photoresist layer
The manufacture method of aforesaid thin-film transistor array base-plate, wherein said semi-modulation type photomask are striated semi-modulation type photomask, netted semi-modulation type photomask or point-like semi-modulation type photomask.
The manufacture method of aforesaid thin-film transistor array base-plate, the formation method of wherein said patterning photoresist layer comprises: form a photo anti-corrosion agent material layer on this dielectric layer; And this photo anti-corrosion agent material layer carried out majority time exposure technology, to form this patterning photoresist layer.
The manufacture method of aforesaid thin-film transistor array base-plate, the method for wherein said this flatness layer of formation comprises: form a photosensitive type dielectric layer; And this photosensitive type dielectric layer carried out majority time exposure technology, to form this flatness layer.
The object of the invention to solve the technical problems also adopts following technical scheme to realize.The manufacture method of a kind of thin-film transistor array base-plate that proposes according to the present invention, it may further comprise the steps: a substrate is provided, and this substrate has a pixel region and a pad zone; Form most bar scan wirings and most grids on this pixel region, and form most first weld pads at this pad zone, those grids and those first weld pads are to be electrically connected to those scan wirings respectively; On this substrate, form a gate dielectric layer, cover those scan wirings and those grids; Form most channel layers on this gate dielectric layer, the position of those channel layers is the positions corresponding to those grids; On each those channel layer, form an one source pole and a drain electrode, form most bar data distributions at this pixel region, and in this pad zone, form most second weld pads, those source electrodes and those second weld pads are to be electrically connected to those data wirings respectively, and those grids, those channel layers, those source electrodes and those drain electrodes are to constitute most thin film transistor (TFT)s; Above this substrate, form a protective seam; On this protective seam, form a flatness layer, this flatness layer has most first openings and most second openings, those first openings are to be positioned at those drain electrode tops, those second openings are to be positioned at those first weld pads and those second weld pads top, this flatness layer that wherein is positioned at this pixel region has one first thickness, and this flatness layer that is positioned at this pad zone has one second thickness, and this first thickness is greater than this second thickness; With this flatness layer is mask, removes the material layer that those first openings and those second openings are exposed, up to exposing those drain electrodes, those first weld pads and those second weld pads; And on this flatness layer, form most pixel electrodes and most electrode material layers, and wherein those drain electrodes are to electrically connect with those pixel electrodes, those electrode material layers are to electrically connect with those first weld pads and those second weld pads.
The object of the invention to solve the technical problems also can be applied to the following technical measures to achieve further.
The manufacture method of aforesaid thin-film transistor array base-plate, wherein before removing the material layer that those first openings and those second openings exposed, this of this flatness layer first thickness is between 2～6 microns, and this of this flatness layer second thickness is between 0.3～1.4 micron.
The manufacture method of aforesaid thin-film transistor array base-plate, wherein after removing the material layer that those first openings and those second openings exposed, this of this flatness layer second thickness is less than 0.8 micron
The manufacture method of aforesaid thin-film transistor array base-plate, the method for wherein said this flatness layer of formation comprises: form a photosensitive type dielectric layer; And use a semi-modulation type photomask that this photosensitive type electricity layer is carried out single exposure technology.
The manufacture method of aforesaid thin-film transistor array base-plate, wherein said semi-modulation type photomask are striated semi-modulation type photomask, netted semi-modulation type photomask or point-like semi-modulation type photomask.
The manufacture method of aforesaid thin-film transistor array base-plate, the method for wherein said this flatness layer of formation comprises: form a dielectric layer; Form a patterning photoresist layer on this dielectric layer, this patterning photoresist layer has most the 3rd openings and most the 4th openings, those the 3rd openings are to be positioned at those drain electrode tops, those the 4th openings are to be positioned at those first weld pads and those second weld pads top, this patterning photoresist layer that wherein is positioned at this pixel region has one the 3rd thickness, and this patterning photoresist layer that is positioned at this pad zone has one the 4th thickness, and the 3rd thickness is greater than the 4th thickness; With this patterning photoresist layer is mask, removes this dielectric layer that is not covered by this patterning photoresist layer, to form this flatness layer; And remove this patterning photoresist layer.
The manufacture method of aforesaid thin-film transistor array base-plate, the formation method of wherein said patterning photoresist layer comprises: form a photo anti-corrosion agent material layer on this dielectric layer; And use a semi-modulation type photomask that this photo anti-corrosion agent material layer is carried out single exposure technology, to form this patterning photoresist layer.
The manufacture method of aforesaid thin-film transistor array base-plate, wherein said semi-modulation type photomask are striated semi-modulation type photomask, netted semi-modulation type photomask or point-like semi-modulation type photomask.
The manufacture method of aforesaid thin-film transistor array base-plate, the formation method of wherein said patterning photoresist layer comprises: form a photo anti-corrosion agent material layer on this dielectric layer; And this photo anti-corrosion agent material layer carried out majority time exposure technology, to form this patterning photoresist layer.
The manufacture method of aforesaid thin-film transistor array base-plate, the method for wherein said this flatness layer of formation comprises: form a photosensitive type dielectric layer; And this photosensitive type dielectric layer carried out majority time exposure technology, to form this flatness layer.
The present invention compared with prior art has tangible advantage and beneficial effect.By above technical scheme as can be known, in order to reach aforementioned goal of the invention, major technique of the present invention thes contents are as follows:
The present invention proposes a kind of manufacture method of thin-film transistor array base-plate.This method is that a substrate at first is provided, and this substrate has a pixel region and a pad zone.At least dispose plurality of scanning wirings, many data wirings and a plurality of thin film transistor (TFT) on this pixel region with a grid, one source pole and a drain electrode.At least dispose a plurality of weld pads on the pad zone.Then, above substrate, form a protective seam.Afterwards, form a flatness layer on protective seam, flatness layer has a plurality of first openings and a plurality of second opening.First opening is to be positioned at the drain electrode top, and second opening is to be positioned at the weld pad top.Wherein, the flatness layer that is positioned at pixel region has one first thickness, and the flatness layer that is positioned at pad zone has one second thickness, and first thickness is greater than second thickness.Then, be mask with the flatness layer, remove the material layer that first opening and second opening are exposed, up to exposing drain electrode and weld pad.At last, on flatness layer, form a plurality of pixel electrodes and a plurality of electrode material layer.Wherein, drain electrode is to electrically connect with pixel electrode, and electrode material layer is to electrically connect with weld pad.
In addition, in the manufacture method of the thin-film transistor array base-plate of present embodiment, before removing the material layer that first opening and second opening exposed, first thickness of flatness layer for example is that second thickness of flatness layer for example is between 0.3～1.4 micron between 2～6 microns (μ m).After removing the material layer that first opening and second opening exposed, second thickness of flatness layer for example is less than 0.8 micron.
Based on the foregoing invention purpose, the present invention also proposes a kind of manufacture method of thin-film transistor array base-plate.This method is that a substrate at first is provided, and substrate has a pixel region and a pad zone.Then, on pixel region, form plurality of scanning wirings and a plurality of grid.Form a plurality of first weld pads at pad zone, and the grid and first weld pad are to be electrically connected to scan wiring respectively.Afterwards, on substrate, form a gate dielectric layer, cover scan wiring and grid.Then, on gate dielectric layer, form a plurality of channel layers, and the position of channel layer is the position corresponding to grid.Then, on each channel layer, form an one source pole and a drain electrode, form many data distributions at pixel region, and in pad zone, form a plurality of second weld pads.Wherein, the source electrode and second weld pad are to be electrically connected to data wiring respectively, and grid, channel layer, source electrode and drain electrode are to constitute a plurality of thin film transistor (TFT)s.Afterwards, above substrate, form a protective seam.Then, form a flatness layer on protective seam, flatness layer has a plurality of first openings and a plurality of second opening.First opening is to be positioned at the drain electrode top, and second opening is to be positioned at first weld pad and second weld pad top.Wherein, the flatness layer that is positioned at pixel region has one first thickness, and the flatness layer that is positioned at pad zone has one second thickness, and first thickness is greater than second thickness.Coming, is mask with the flatness layer again, removes first and opens the material layer that is exposed with mouthful second opening, up to exposing drain electrode, first weld pad and second weld pad.At last, on flatness layer, form a plurality of pixel electrodes and a plurality of electrode material layer.Wherein, drain electrode is to electrically connect with pixel electrode, and electrode material layer is to electrically connect with first weld pad and second weld pad.
In addition, in the manufacture method of the thin-film transistor array base-plate of present embodiment, before removing the material layer that first opening and second opening exposed, first thickness of flatness layer for example is between 2～6 microns, and second thickness of flatness layer for example is between 0.3～1.4 micron.After removing the material layer that first opening and second opening exposed, second thickness of flatness layer for example is less than 0.8 micron.
In the manufacture method of the thin-film transistor array base-plate of above-mentioned two kinds of embodiment, the method that forms flatness layer for example is to form a photosensitive type dielectric layer earlier, then the photosensitive type dielectric layer is carried out majority time exposure technology, perhaps use a semi-modulation type photomask that the photosensitive type dielectric layer is carried out single exposure technology.Wherein, semi-modulation type photomask for example comprises striated semi-modulation type photomask, netted semi-modulation type photomask or point-like semi-modulation type photomask.
Via as can be known above-mentioned, the manufacture method of thin-film transistor array base-plate of the present invention is that a substrate at first is provided, and substrate has a pixel region and a pad zone.At least dispose plurality of scanning wirings, many data wirings and a plurality of thin film transistor (TFT) on the pixel region.Dispose a plurality of weld pads on the pad zone.Then, form a protective seam and a flatness layer in regular turn above substrate, flatness layer has a plurality of first openings and a plurality of second opening, and flatness layer has one first thickness at pixel region, has one second thickness at pad zone, and first thickness is greater than second thickness.Then, be mask with the flatness layer, remove the material layer in first opening and second opening, up to drain electrode that exposes thin film transistor (TFT) and weld pad.At last, on flatness layer, form a plurality of pixel electrode and a plurality of electrode material layers that are electrically connected to weld pad that are electrically connected to drain electrode.
By technique scheme; the manufacture method of thin-film transistor array base-plate of the present invention has the following advantages at least: by semi-modulation type photomask or double exposure technology; can be respectively at the pixel region of thin-film transistor array base-plate and the flatness layer of pad zone acquisition different-thickness; and be that the flatness layer of pad zone almost disappeared after mask removed material layer in first opening and second opening with the flatness layer.So,, can not destroy the protective seam and the metal level of pad zone yet, and then can improve the success ratio of chip join heavy industry because anisotropic conductive film is close with the flatness layer material even need rework when carrying out chip join follow-up.
In sum; the manufacture method of the thin-film transistor array base-plate that the present invention is special; because the flatness layer of pad zone almost disappears; so follow-up when carrying out the chip join heavy industry; also can not destroy the protective seam and the metal level of pad zone; therefore can improve the success ratio of chip join heavy industry, be very suitable for reducing the heavy industry mortality of follow-up chip join technology, thereby be suitable for practicality more.It has above-mentioned many advantages and practical value, and in similar manufacture method, do not see have similar design to publish or use and really genus innovation, no matter it is all having bigger improvement on manufacture method or on the function, have large improvement technically, and produced handy and practical effect, and the manufacture method of more existing thin-film transistor array base-plate has the multinomial effect of enhancement, thereby be suitable for practicality more, and have the extensive value of industry, really be a new and innovative, progressive, practical new design.
Above-mentioned explanation only is the general introduction of technical solution of the present invention, for can clearer understanding technological means of the present invention, and can be implemented according to the content of instructions, below with preferred embodiment of the present invention and conjunction with figs. describe in detail as after.
Description of drawings
Look synoptic diagram on Fig. 1 one existing known thin-film transistor array base-plate.
Fig. 2 A to Fig. 2 E is the technology of I-I ' section among Fig. 1 and the diagrammatic cross-section of structure.
Fig. 3 be the preferred embodiment according to the present invention thin-film transistor array base-plate on look synoptic diagram.
Fig. 4 A to Fig. 4 F is the technology of II-II ' section among Fig. 3 and the diagrammatic cross-section of structure.
Fig. 5 A～Fig. 5 C is the synoptic diagram of the employed semi-modulation type photomask of thin-film transistor array base-plate of the preferred embodiment according to the present invention.
Fig. 6 A～6B figure double exposes technology with the flow process of formation flatness layer and the diagrammatic cross-section of structure.
Fig. 7 A～Fig. 7 D is that another kind of formation is as the flow process of the method for the flatness layer of Fig. 4 D and the diagrammatic cross-section of structure.
50: substrate 100: thin film transistor (TFT) (electric crystal) array base palte
112: grid 114: channel layer
116: source electrode 118: drain electrode
120: scan distribution 122,142: weld pad
130: gate dielectric layer 140: the data distribution
150: protective seam 160: flatness layer
170: pixel electrode 172: electrode material layer
200: thin-film transistor array base-plate 210: thin film transistor (TFT)
212: grid 214: channel layer
216: source electrode 218: drain electrode
220: scan distribution 222,242: weld pad
230: gate dielectric layer 240: the data distribution
250: protective seam 260: flatness layer
262: dielectric layer 270: pixel electrode
272: electrode material layer 280: etch stop layer
285: ohmic contact layer 290: the photo anti-corrosion agent material layer
292: patterning photoresist layer 300: semi-modulation type photomask
31O: complete transmission region 320: part transmission region
330: light tight regional A: pixel region
B: pad zone O1: first opening
O2: second opens O3: the 3rd opening
O4: the 4th opens H1: first thickness
H2: the second thickness H3: the 3rd thickness
H4: the 4th thickness
Embodiment
Below in conjunction with accompanying drawing and preferred embodiment, its concrete manufacture method of manufacture method, step, feature and the effect thereof of the thin-film transistor array base-plate that foundation the present invention is proposed, describe in detail as after.
Fig. 3 is the last TV structure synoptic diagram of the thin-film transistor array base-plate of the preferred embodiment according to the present invention.Fig. 4 A to Fig. 4 F is the technology of II-II ' section among Fig. 3 and the diagrammatic cross-section of structure.
Disclosed is the manufacture method of a kind of thin-film transistor array base-plate (plurality of groups of substrates of thin-film transistor), is that a wherein dot structure and the part of solder pads with thin film transistor (TFT) array (array) elaborates in the following stated and diagram.
See also shown in Fig. 3 and Fig. 4 A, the manufacture method of the thin-film transistor array base-plate 200 of preferred embodiment of the present invention is that a substrate 50 at first is provided, and this substrate 50 has a pixel region A and a pad zone B.Then carry out the first road photo-marsk process, on the pixel region A of substrate 50, to form plurality of scanning wirings 220 and a plurality of grids 212, and form a plurality of first weld pads 222 at pad zone B, and the grid 212 and first weld pad 222 are to be electrically connected to scan wiring 220 respectively, wherein, scan wiring 220, grid 212 and first weld pad 222 all belong to the first metal layer (M1) afterwards, on substrate 50, form a gate dielectric layer 230, cover scan wiring 220 and grid 212, wherein, the material of gate dielectric layer 230 for example is silicon nitride or monox.
Then see also shown in Fig. 3 and Fig. 4 B, carry out the second road photo-marsk process, on the gate dielectric layer above the grid 212 230, to define channel layer 214.Simultaneously, for example in, successively form an etch stop layer 280 and an ohmic contact layer 285 on channel layer 214 with photo-marsk process.Wherein, the material of channel layer 214 for example is amorphous silicon (a-Si), and the material of etch stop layer 280 for example is a silicon nitride, and the material of ohmic contact layer 285 for example is through doped amorphous silicon (n+a-Si).
Then see also shown in Fig. 3 and Fig. 4 C, carry out the 3rd road photo-marsk process, above each channel layer 214, form one source pole 216, a drain electrode 218 and many data distributions 240, and form a plurality of second weld pads 242 at the pad zone B of substrate 50.Wherein, the source electrode 216 and second weld pad 242 are to be electrically connected to data wiring 240 respectively.Grid 212, channel layer 214, source electrode 216 are to constitute a plurality of thin film transistor (TFT)s 210 with drain electrode 218.Source electrode 216, drain electrode 218, data distribution 240 and second weld pad 242 are all second layer metal layer (M2).
After having defined second metal level, on substrate 50, form a protective seam 250, cover second metal level (source electrode 216, drain electrode 218, data distribution 240 and second weld pad 242).Wherein, the material of protective seam 250 for example is silicon nitride or monox.
Then see also shown in Fig. 3 and Fig. 4 D, carry out the 4th road photo-marsk process, on protective seam, form a flatness layer 260.Flatness layer 260 has a plurality of first opening O1 and a plurality of second opening O2.The first opening O1 is positioned at drain electrode 218 tops, and the second opening O2 is positioned at first weld pad 222 and second weld pad, 242 tops.Wherein, the flatness layer 260 that is positioned at pixel region A has one first thickness H1, and the flatness layer 260 that is positioned at pad zone B has one second thickness H2, and the first thickness H1 is greater than the second thickness H2.At this moment, the first thickness H1 of flatness layer 260 for example is between 2～6 microns, and the second thickness H2 of flatness layer 260 for example is between 0.3～1.4 micron.
Form the method for flatness layer 260, for example be to use a semi-modulation type photomask (not shown) to carry out single exposure technology.Wherein, the material of flatness layer 260 for example is a kind of photosensitive type dielectric layer, therefore has the characteristic of photo anti-corrosion agent material.Fig. 5 A～Fig. 5 C is the structural representation of the employed semi-modulation type photomask of thin-film transistor array base-plate of the preferred embodiment according to the present invention.Please consult jointly shown in Fig. 3 D and Fig. 5 A～Fig. 5 C, semi-modulation type photomask 300 for example can be divided into complete transmission region 310, part transmission region 320 with light tight regional 330.Having the negative photoresist characteristic with flatness layer 260 is example, photic zone 310 territories for example are in alignment with above the pixel region A fully in exposure technology, partly transmission region 320 for example is that light tight regional 330 for example is in alignment with first weld pad 222 and second weld pad, 242 tops in alignment with pad zone B top.Because the flatness layer 260 of pad zone B is partly exposure only, therefore its second thickness H2 will be less than the first thickness H1 after developing.Semi-modulation type photomask 300 for example is striated semi-modulation type photomask (shown in Fig. 5 A), netted semi-modulation type photomask (shown in Fig. 5 B) or point-like semi-modulation type photomask (shown in Fig. 5 C).In this technology, the crack should be less than the resolution of exposure technology between the semi-modulation type photomask 300, and flatness layer 260 should adopt the material that is easier to carry out reflow (Reflow), so will be easier to obtain desirable flatness
In addition, the method that forms flatness layer 260 is also carried out multiexposure, multiple exposure technology.Wherein, the material of flatness layer 260 for example is a kind of photosensitive type dielectric layer, therefore has the characteristic of photo anti-corrosion agent material.Fig. 6 A～Fig. 6 B double exposes technology to form the flow process diagrammatic cross-section of flatness layer.See also shown in Fig. 3 and Fig. 6 A, exposure technology for example is to adopt one first photomask (not shown) for the first time, makes the drain electrode 218 and the flatness layer 260 of pad zone B top that light reaction take place.Then see also shown in Fig. 6 B, exposure technology then adopts one second photomask (not shown) for the second time, makes the flatness layer 260 of drain electrode 218, first weld pad 222 and second weld pad 242 (being illustrated in Fig. 3) top that light reaction take place fully.So; carrying out after developing process removes with flatness layer 260 that light reaction will take place (shade partly); the protective seam 250 of drain electrode 218, first weld pad 222 and second weld pad, 242 tops can come out, and flatness layer 260 also can be less than the first thickness H1 of pixel region A at the second thickness H2 of pad zone B.
Then seeing also shown in Fig. 3 and Fig. 4 E, is mask with flatness layer 260, removes the material layer that the first opening O1 and the second opening O2 are exposed, up to exposing drain electrode 218, first weld pad 222 and second weld pad 242.Behind the material layer in removing the first opening O1 and the second opening O2, the minimizing that the thickness of flatness layer 260 also can trace, therefore the second thickness H2 for example be less than 0.8 micron for good, perhaps the flatness layer on the pad zone B 260 can complete obiterations.But if flatness layer 260 complete obiterations on the pad zone B, then the gross thickness of the gate dielectric layer 230 of pad zone B and protective seam 250 is being good greater than 500 dusts.
See also at last shown in Fig. 3 and Fig. 4 F, carry out the 5th road photo-marsk process, on flatness layer 260, form a plurality of pixel electrodes 270 and a plurality of electrode material layers 272.Wherein, drain electrode 218 is to electrically connect with pixel electrode 270 in the first opening O1, and electrode material layer 272 is to electrically connect with first weld pad 222 and second weld pad 242 in the second opening O2.
See also shown in Fig. 4 F; because the thickness of the flatness layer 260 on pad zone B is less than 0.8 micron; or even complete obiteration; even so the arts demand heavy industry of follow-up applying chip can not destroy the protective seam below the flatness layer 260 250, gate dielectric layer 230 in removing the process of anisotropic conductive film yet with weld pad 222.
Fig. 7 A～Fig. 7 D is flow process and the structural profile synoptic diagram of another kind of formation as the method for the flatness layer of Fig. 4 D.See also shown in Fig. 7 A, the another kind of method that forms the flatness layer 260 of Fig. 4 D for example is to form a dielectric layer 262 earlier on protective seam 250.Then see also shown in Fig. 7 B, form a patterning photoresist layer 292 on dielectric layer 262, patterning photoresist layer 292 has a plurality of the 3rd opening O3 and a plurality of the 4th opening O4, and the 3rd opening O3 is positioned at drain electrode 218 tops, the 4th opening O4 is positioned at first weld pad 222 and second weld pad 242 (being illustrated in Fig. 3) top, wherein, the patterning photoresist layer 292 that is positioned at pixel region A has one the 3rd thickness H3, and the patterning photoresist layer 292 that is positioned at pad zone B has one the 4th thickness H4, and the 3rd thickness H3 is greater than the 4th thickness H4, and the formation method of patterning photoresist layer 292 for example is at first to form a photo anti-corrosion agent material layer 290 on dielectric layer 262.Then, use the 300 pairs of photo anti-corrosion agent material layers of semi-modulation type photomask 290 shown in Fig. 5 A～Fig. 5 C to carry out single exposure technology, can form patterning photoresist layer 292.But the formation method of patterning photoresist layer 292 also at first forms a photo anti-corrosion agent material layer 290 on dielectric layer 262.Then, photo anti-corrosion agent material layer 290 is carried out multiexposure, multiple exposure technology, promptly can form patterning photoresist layer 292 with the method shown in Fig. 6 A～Fig. 6 B.Then seeing also shown in Fig. 7 B and Fig. 7 C, is mask with patterning photoresist layer 29 2, removes and is not patterned the dielectric layer 262 that photoresist layer 292 is covered, to form flatness layer 260.See also at last shown in Fig. 7 D, remove patterning photoresist layer 292 and can obtain the flatness layer 260 identical with Fig. 4 D.
Indulge the above; by semi-modulation type photomask or double exposure technology; can be respectively at the pixel region of thin-film transistor array base-plate and the flatness layer of pad zone acquisition different-thickness; and be that the flatness layer of pad zone almost disappeared after mask removed material layer in first opening and second opening with the flatness layer.So,, can not destroy the protective seam and the metal level of pad zone yet, and then can improve the success ratio of chip join heavy industry because anisotropic conductive film is close with the flatness layer material even need rework when carrying out chip join follow-up.
The above, it only is preferred embodiment of the present invention, be not that the present invention is done any pro forma restriction, though the present invention discloses as above with preferred embodiment, yet be not in order to limit the present invention, any those skilled in the art, in not breaking away from the technical solution of the present invention scope, when the method that can utilize above-mentioned announcement and technology contents are made a little change or be modified to the equivalent embodiment of equivalent variations, but every content that does not break away from technical solution of the present invention, according to technical spirit of the present invention to any simple modification that above embodiment did, equivalent variations and modification all still belong in the scope of technical solution of the present invention.
Claims (20)
1. the manufacture method of a thin-film transistor array base-plate is characterized in that it may further comprise the steps:
One substrate is provided, have a pixel region and a pad zone, at least dispose most bar scan wirings, most bar data wiring and most thin film transistor (TFT)s on this pixel region, and dispose most weld pads on this pad zone at least with a grid, one source pole and a drain electrode;
Above this substrate, form a protective seam;
On this protective seam, form a flatness layer, this flatness layer has most first openings and most second openings, those first openings are to be positioned at those drain electrode tops, those second openings are to be positioned at those weld pad tops, this flatness layer that wherein is positioned at this pixel region has one first thickness, and this flatness layer that is positioned at this pad zone has one second thickness, and this first thickness is greater than this second thickness;
With this flatness layer is mask, removes the material layer that those first openings and those second openings are exposed, up to exposing those drain electrodes and those weld pads; And
Form most pixel electrodes and most electrode material layers on this flatness layer, wherein those pixel electrodes are to electrically connect with those drain electrodes, and those electrode material layers are to electrically connect with those weld pads.
2. the manufacture method of thin-film transistor array base-plate according to claim 1, it is characterized in that wherein before removing the material layer that those first openings and those second openings exposed, this of this flatness layer first thickness is between 2～6 microns, and this of this flatness layer second thickness is between 0.3～1.4 micron.
3. the manufacture method of thin-film transistor array base-plate according to claim 1 is characterized in that wherein this of this flatness layer second thickness is less than 0.8 micron after removing the material layer that those first openings and those second openings exposed.
4. the manufacture method of thin-film transistor array base-plate according to claim 1 is characterized in that the method for wherein said this flatness layer of formation comprises:
Form a photosensitive type dielectric layer; And
Use a semi-modulation type photomask that this photosensitive type dielectric layer is carried out single exposure technology.
5. the manufacture method of thin-film transistor array base-plate according to claim 4 is characterized in that wherein said semi-modulation type photomask is striated semi-modulation type photomask, netted semi-modulation type photomask or point-like semi-modulation type photomask.
6. the manufacture method of thin-film transistor array base-plate according to claim 1 is characterized in that the method for wherein said this flatness layer of formation comprises:
Form a dielectric layer;
Form a patterning photoresist layer on this dielectric layer, this patterning photoresist layer has most the 3rd openings and most the 4th openings, those the 3rd openings are to be positioned at those drain electrode tops, those the 4th openings are to be positioned at those weld pad tops, this patterning photoresist layer that wherein is positioned at this pixel region has one the 3rd thickness, and this patterning photoresist layer that is positioned at this pad zone has one the 4th thickness, and the 3rd thickness is greater than the 4th thickness;
With this patterning photoresist layer is mask, removes this dielectric layer that is not covered by this patterning photoresist layer, to form this flatness layer; And
Remove this patterning photoresist layer.
7. the manufacture method of thin-film transistor array base-plate according to claim 6 is characterized in that the formation method of wherein said patterning photoresist layer comprises:
Form a photo anti-corrosion agent material layer on this dielectric layer; And
Use a semi-modulation type photomask that this photo anti-corrosion agent material layer is carried out single exposure technology, to form this patterning photoresist layer.
8. the manufacture method of thin-film transistor array base-plate according to claim 7 is characterized in that wherein said semi-modulation type photomask is striated semi-modulation type photomask, netted semi-modulation type photomask or point-like semi-modulation type photomask.
9. the manufacture method of thin-film transistor array base-plate according to claim 6 is characterized in that the formation method of wherein said patterning photoresist layer comprises:
Form a photo anti-corrosion agent material layer on this dielectric layer; And
This photo anti-corrosion agent material layer is carried out majority time exposure technology, to form this patterning photoresist layer.
10. the manufacture method of thin-film transistor array base-plate according to claim 1 is characterized in that the method for wherein said this flatness layer of formation comprises:
Form a photosensitive type dielectric layer; And
This photosensitive type dielectric layer is carried out majority time exposure technology, to form this flatness layer.
11. the manufacture method of a thin-film transistor array base-plate is characterized in that it may further comprise the steps:
One substrate is provided, and this substrate has a pixel region and a pad zone;
Form most bar scan wirings and most grids on this pixel region, and form most first weld pads at this pad zone, those grids and those first weld pads are to be electrically connected to those scan wirings respectively;
On this substrate, form a gate dielectric layer, cover those scan wirings and those grids;
Form most channel layers on this gate dielectric layer, the position of those channel layers is the positions corresponding to those grids;
On each those channel layer, form an one source pole and a drain electrode, form most bar data distributions at this pixel region, and in this pad zone, form most second weld pads, those source electrodes and those second weld pads are to be electrically connected to those data wirings respectively, and those grids, those channel layers, those source electrodes and those drain electrodes are to constitute most thin film transistor (TFT)s;
Above this substrate, form a protective seam;
On this protective seam, form a flatness layer, this flatness layer has most first openings and most second openings, those first openings are to be positioned at those drain electrode tops, those second openings are to be positioned at those first weld pads and those second weld pads top, this flatness layer that wherein is positioned at this pixel region has one first thickness, and this flatness layer that is positioned at this pad zone has one second thickness, and this first thickness is greater than this second thickness;
With this flatness layer is mask, removes the material layer that those first openings and those second openings are exposed, up to exposing those drain electrodes, those first weld pads and those second weld pads; And
Form most pixel electrodes and most electrode material layers on this flatness layer, wherein those drain electrodes are to electrically connect with those pixel electrodes, and those electrode material layers are to electrically connect with those first weld pads and those second weld pads.
12. the manufacture method of thin-film transistor array base-plate according to claim 11, it is characterized in that wherein before removing the material layer that those first openings and those second openings exposed, this of this flatness layer first thickness is between 2～6 microns, and this of this flatness layer second thickness is between 0.3～1.4 micron.
13. the manufacture method of thin-film transistor array base-plate according to claim 11 is characterized in that wherein the 3rd thickness of this flatness layer is less than 0.8 micron after removing the material layer that those first openings and those second openings exposed.
14. the manufacture method of thin-film transistor array base-plate according to claim 11 is characterized in that the method for wherein said this flatness layer of formation comprises:
Form a photosensitive type dielectric layer; And
Use a semi-modulation type photomask that this photosensitive type dielectric layer is carried out single exposure technology.
15. the manufacture method of thin-film transistor array base-plate according to claim 14 is characterized in that wherein said semi-modulation type photomask is striated semi-modulation type photomask, netted semi-modulation type photomask or point-like semi-modulation type photomask.
16. the manufacture method of thin-film transistor array base-plate according to claim 11 is characterized in that the method for wherein said this flatness layer of formation comprises:
Form a dielectric layer;
Form a patterning photoresist layer on this dielectric layer, this patterning photoresist layer has most the 3rd openings and most the 4th openings, those the 3rd openings are to be positioned at those drain electrode tops, those the 4th openings are to be positioned at those first weld pads and those second weld pads top, this patterning photoresist layer that wherein is positioned at this pixel region has one the 3rd thickness, and this patterning photoresist layer that is positioned at this pad zone has one the 4th thickness, and the 3rd thickness is greater than the 4th thickness;
With this patterning photoresist layer is mask, removes this dielectric layer that is not covered by this patterning photoresist layer, to form this flatness layer; And
Remove this patterning photoresist layer
17. the manufacture method of thin-film transistor array base-plate according to claim 16. the formation method that it is characterized in that wherein said patterning photoresist layer comprises:
Form a photo anti-corrosion agent material layer on this dielectric layer; And
Use a semi-modulation type photomask that this photo anti-corrosion agent material layer is carried out single exposure technology, to form this patterning photoresist layer.
18. the manufacture method of thin-film transistor array base-plate according to claim 17 is characterized in that wherein said semi-modulation type photomask is striated semi-modulation type photomask, netted semi-modulation type photomask or point-like semi-modulation type photomask.
19. the manufacture method of thin-film transistor array base-plate according to claim 16 is characterized in that the formation method of wherein said patterning photoresist layer comprises:
Form a photo anti-corrosion agent material layer on this dielectric layer; And
This photo anti-corrosion agent material layer is carried out majority time exposure technology, to form this patterning photoresist layer.
20. the manufacture method of thin-film transistor array base-plate according to claim 11 is characterized in that the method for wherein said this flatness layer of formation comprises:
Form a photosensitive type dielectric layer; And
This photosensitive type dielectric layer is carried out majority time exposure technology, to form this flatness layer.
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| CN100417995C (en) * | 2005-10-10 | 2008-09-10 | 友达光电股份有限公司 | Wire substrate of liquid-crystal display device and production thereof |
| CN101442060B (en) * | 2008-12-25 | 2011-04-20 | 友达光电股份有限公司 | Pixel array and method of manufacturing the same |
| TWI451178B (en) * | 2011-11-07 | 2014-09-01 | Hannstar Display Corp | Array substrate, liquid crystal display for the same and manufacturing method thereof |
| TWI441198B (en) * | 2011-12-30 | 2014-06-11 | Au Optronics Corp | Panel and method for fabricating the same |
| CN104335113A (en) * | 2012-05-26 | 2015-02-04 | 希百特股份有限公司 | Mask level reduction for mofet |
| KR102104356B1 (en) * | 2012-12-24 | 2020-04-24 | 엘지디스플레이 주식회사 | Array substrate for fringe field switching mode liquid crystal display device and Method of fabricating the same |
| TWI657563B (en) * | 2015-12-15 | 2019-04-21 | 優顯科技股份有限公司 | Opto-electronic apparatus and manufacturing method thereof |
| TWI719863B (en) | 2020-03-20 | 2021-02-21 | 研能科技股份有限公司 | Manufacturing method of narrow type inkjet print head chip |
| CN113492592B (en) * | 2020-03-20 | 2022-09-20 | 研能科技股份有限公司 | Method for manufacturing long and narrow ink jet head chip |
| CN113497023B (en) * | 2020-03-20 | 2024-02-06 | 研能科技股份有限公司 | Long and narrow type ink jet head chip |
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