CN101154381B - Device for obtaining coefficient of linear prediction wave filter - Google Patents
Device for obtaining coefficient of linear prediction wave filter Download PDFInfo
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- CN101154381B CN101154381B CN2006100629926A CN200610062992A CN101154381B CN 101154381 B CN101154381 B CN 101154381B CN 2006100629926 A CN2006100629926 A CN 2006100629926A CN 200610062992 A CN200610062992 A CN 200610062992A CN 101154381 B CN101154381 B CN 101154381B
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Abstract
A device for calculating linear prediction filter coefficient completes calculation according to multiple iteration and comprises an auto correlation coefficient memory, a reflection coefficient calculation module, an error amount calculation module, a filter coefficient calculation module, a filter coefficient memory and a top control module, wherein, the auto correlation coefficient memory stores known auto correlation coefficient in advance; according to the auto correlation coefficient and the filter coefficient and the minimum error amount of the previous iteration, the reflection coefficient calculation module completes calculation to obtain the reflection coefficient of the current iteration; the error amount calculation module completes calculation according to the minimum error amount of the previous iteration and the reflection coefficient of the current iteration to obtain the minimum error amount of the current iteration; the filter coefficient calculation module completes calculation according to the reflection coefficient of the current iteration and the filter coefficient of the previous iteration to obtain the filter coefficient of the current iteration; moreover, the top control module generates control signal to control and dispatch the modules and memories.
Description
Technical field
The present invention relates to signal processing technology, especially refer to a kind of device that obtains coefficient of linear prediction wave filter.
Background technology
Linear prediction is one of core technology in the speech processes, successfully is applied to speech recognition, synthesizes aspects such as reaching coding.And the content of a key is the coefficient of finding the solution linear prediction filter in the linear prediction, because LD (Levinson-Durbin, the row Vincent-Du Bin) algorithm adopts the processing mode of recursion iteration when finding the solution the coefficient of linear prediction filter, have simply, characteristics such as effective easily and fast, so be widely used.
In Levinson-Durbin algorithm process process, import coefficient of autocorrelation earlier, carry out initialization then, then utilize the result of a preceding iteration to carry out next iteration, all can than a preceding iteration after iteration is finished each time more and obtain a filter coefficient, therefore by certain number of times as after 27 iteration, will obtain 27 new filter coefficients, and that filter coefficient that obtains during initialization remains in iteration at every turn constant.
Fig. 1 has provided the process flow diagram that the Levinson-Durbin algorithm is realized, for convenience of explanation, is 27 to describe with iterations still, and wherein P (m) refers to filter coefficient (m refers to iterations, value can be 0,1,2......), P
m(K) specifically refer to K filter coefficient producing after the m time iteration, P (0) or P
0The filter coefficient that obtains when (0) referring to initialization, Jmin refers to minimum error values, J
Min mSpecifically refer to the minimum error values that produces after the m time iteration.Carry out initialization after at first importing coefficient of autocorrelation, this moment, m got initial value 0, obtained FACTOR P (0) and error amount J
Min 0, then iterations is added 1, if iterations does not also reach 27 times, ask for reflection coefficient Tm value earlier, then ask for each rank filter coefficient P (1) ..., P (m), ask for minimum error values J subsequently
Min m, and filter coefficient and the minimum error values of utilizing the filter coefficient that obtains for the m time and minimum error values to upgrade to obtain for the m-1 time; After iterations reaches 27 times, preserve filter coefficient P (0), P (1) ..., P (27) and export as net result.
Because prior art generally realizes the Levinson-Durbin algorithm by software, thereby obtains filter coefficient, from said process as can be seen, for the linear filter on m rank, though only need ask for q
pThe rank filter coefficient is lower than q but must obtain earlier for this reason
pEach rank predictive coefficient because this algorithm is recursive solution, algorithm complexity, especially multiplication, add up and arithmetic element such as division is repeated to call, operand is huge.Therefore be difficult in the asic chip and realize, be unfavorable for the popularization in hardware.
Summary of the invention
The object of the present invention is to provide a kind of device of asking for linear predictive filter coefficient, and this device is applicable to and asks for each rank filter coefficient.
Device that the present invention program provides is finished the process of asking for of filter coefficient according to iteration repeatedly, comprising: coefficient of autocorrelation storer, reflection coefficient ask for that module, error amount are asked for module, filter coefficient is asked for module, filter coefficient storage and top layer control module; Described coefficient of autocorrelation storer stores the coefficient of autocorrelation that is used for iteration in advance; Reflection coefficient is asked for module, is used for finishing the asking for of reflectance value of iteration each time; Error amount is asked for module, is used for finishing the asking for of minimum error values of iteration each time; Filter coefficient is asked for module, is used for finishing the asking for of filter coefficient of iteration each time; Filter coefficient storage is stored the filter coefficient that obtains after each iteration is finished; The top layer control module is used to produce the read-write control signal of above-mentioned each module and storer, and each module and storer are read and write scheduling;
Wherein, described reflection coefficient is asked for the minimum error values that module asks for the last iteration that module provides according to the coefficient of autocorrelation in the described coefficient of autocorrelation storer, the filter coefficient of last iteration in the described filter coefficient storage and described error amount and is carried out computing, obtains the reflection coefficient of this iteration; Described error amount this iteration reflection coefficient that module asks for module and provide according to the minimum error values of last iteration and described reflection coefficient is provided is carried out computing, obtains the minimum error values of this iteration; Described filter coefficient asks for that module is asked for this iteration reflection coefficient that module provides according to described reflection coefficient and the filter coefficient of the last iteration in the described filter coefficient storage carries out computing, obtain the filter coefficient of this iteration, and be saved in the described filter coefficient storage.
Described filter coefficient storage is the filter coefficient update module, is used for utilizing when the memory filter coefficient filter coefficient of the N time iteration of filter coefficient update of the N+1 time iteration, and N is a natural number.
Described error amount is asked for module and is comprised error amount register and error calculation unit, described error amount register reads the initial value of first autocorrelation value as minimum error values after receiving the outside enabling signal m_start that sends of described device from described coefficient of autocorrelation storer; The minimum error values that described error calculation unit is asked for this iteration reflection coefficient that module provides and the last iteration in the described error amount register according to described reflection coefficient obtains the minimum error values of this iteration and is used for upgrading the minimum error values of last iteration in the described error amount register.
Described error calculation unit comprises reflection coefficient mould square computing unit, first d type flip flop, multiplier B, second d type flip flop, subtracter and 3d flip-flop, wherein the output terminal of reflection coefficient mould square computing unit links to each other with the first d type flip flop input end, and the output terminal of first d type flip flop links to each other with the input end of multiplier B; Another input end of multiplier B links to each other with described error amount register, receives the minimum error values of last iteration, and the output terminal of multiplier B links to each other with the second d type flip flop input end; An input end of the second d type flip flop output terminal subtracter links to each other, and another input end of subtracter links to each other with described error amount register, receives the minimum error values of last iteration; Subtracter is exported the minimum error values of this iteration, and the subtracter output terminal links to each other with the 3d flip-flop input end, and the 3d flip-flop output terminal links to each other with described error amount register, exports the minimum error values of this iteration.
Described reflection coefficient is asked for module and is comprised that multiplier C, four d flip-flop, first adder, the 5th d type flip flop, second get conjugate unit, divider, the 6th d type flip flop and reflection coefficient register, wherein multiplier C input end links to each other with described coefficient of autocorrelation storer, and another input end links to each other with described filter coefficient storage; The output terminal of multiplier C links to each other with the input end of four d flip-flop, and the output terminal of four d flip-flop links to each other with an input end of first adder; The output terminal of first adder links to each other with the input end of the 5th d type flip flop, and the output terminal of the 5th d type flip flop links to each other with another input end of first adder and an input end of divider; Second gets the conjugate unit input end asks for module with described error amount and links to each other, output terminal links to each other with another input end of divider, the conjugation of last iteration minimum error values is provided, divider carries out divide operations after receiving the divider enabling signal that described top layer control module sends, export the reflection coefficient of this iteration; The 6th d type flip flop input end receives the reflection coefficient of this iteration, and output terminal links to each other with described reflection coefficient register; The reflection coefficient of described this iteration of reflection coefficient register holds.
Described filter coefficient is asked for module and is comprised that the 3rd gets conjugate unit, multiplier D, the 7th d type flip flop, second adder, selector switch and the 8th d type flip flop, wherein the 3rd input end of getting conjugate unit links to each other with described filter coefficient storage, and output terminal links to each other with the input end of multiplier D; Another input end of multiplier D is asked for module with described reflection coefficient and is linked to each other, and receives the reflection coefficient of this iteration, and output terminal links to each other with the input end of the 7th d type flip flop; The output terminal of the 7th d type flip flop links to each other with an input end of second adder, and another input end of second adder links to each other with described filter coefficient storage, receives the filter coefficient of last iteration; 0 input end of selector switch links to each other with the output terminal of second adder, and 1 input end is asked for module with described reflection coefficient and linked to each other, and control end receives and states the selection signal sel that the top layer control module sends, and exports the filter coefficient of this iteration; The input end of the 8th d type flip flop links to each other with the output terminal of selector switch, and output terminal links to each other with filter coefficient storage.
Described multiplier C and multiplier D can utilize a multiplexing multiplier to realize, described multiplexing multiplier is the time division multiplex multiplier, comprise a multiplication unit and two MUX, wherein
Described multiplication unit is a complex multiplier, is used to realize that complex multiplication or real number multiply each other;
Described two MUX are used to receive identical control signal, and export one road signal respectively to the input signal of described multiplication unit as described multiplication unit.
The control end of a described selector switch receives the first control signal pp_flag, and 0 input end receives the filter coefficient of table tennis RAM output or the filter coefficient that 1 input end receives pang RAM output; Input is read enable signal and is received first control signal with the control end of importing two reverse selector switchs reading address signal, and 0 output terminal is connected with table tennis RAM respectively or 1 output terminal is connected with pang RAM respectively; The control end that three reverse selector switchs of enable signal and input writing address signal are write in input filter coefficient, input receives second control signal, and 0 output terminal is connected with table tennis RAM respectively or 1 output terminal is connected with pang RAM biography respectively; And described first control signal and second control signal be designature each other.
Described top layer control module comprises first counter, second counter, the 3rd counter, coefficient of autocorrelation read control signal generator and filter coefficient read-write control signal generator, wherein first counter is used to indicate iterations, and produces control signal pp_flag according to the first counter lowest order; Second counter is used for beginning to count down when the first counter meter during to new value, and initial value is first Counter Value of last iteration, until being decremented to 0; The 3rd counter is used for after second Counter Value is 0, and the beginning accumulated counts is up to 2 times of values of this iteration first counter; Coefficient of autocorrelation read control signal generator is used for the count value according to first counter and second counter, produces reading enable signal and reading address signal of visit coefficient of autocorrelation storer; Filter coefficient read-write control signal generator is used for the count value according to second counter and the 3rd counter, produces filter coefficient read-write enable signal and read/write address signal.
Technical solution of the present invention is utilizing hardware to realize obtaining of coefficient of linear prediction wave filter, and implementation structure is more flexible, is adapted to ask for each rank filter coefficient, and also applicable when coefficient of autocorrelation length and filter coefficient length change; The special multiplexing process of passing through utilizes a time division multiplex multiplier to realize the function of a plurality of multipliers, can save hardware resource consumption, helps chip design and the popularization in hardware.
Description of drawings
Fig. 1 is the realization flow figure of Levinson-Durbin algorithm;
Fig. 2 obtains the sequential chart that the filter coefficient device is realized the LD algorithm in the embodiment of the invention;
Fig. 3 is the block diagram that obtains the filter coefficient device in the embodiment of the invention;
Fig. 4 is the structural drawing of the storer of coefficient of autocorrelation shown in Fig. 3;
Fig. 5 is the structural drawing that error amount shown in Fig. 3 is asked for module;
Fig. 6 is the structural drawing that reflection coefficient shown in Fig. 3 is asked for module;
Fig. 7 is the structural drawing that filter coefficient shown in Fig. 3 is asked for module;
Fig. 8 is the structural drawing of filter coefficient storage shown in Fig. 3;
Fig. 9 is the structural drawing of the control module of top layer shown in Fig. 3;
Figure 10 is the production process of 3 counters shown in Fig. 9;
Figure 11 is the sequential chart of 3 counters shown in Fig. 9;
Figure 12 is the implementation structure figure of time division multiplex multiplier in the embodiment of the invention.
Embodiment
The present invention adopts the serial method for designing, carry out repeatedly iteration by hardware, realize the Levinson-Durbin algorithm, obtain coefficient of linear prediction wave filter, and implementation structure is a kind of universal architecture, even also applicable when coefficient of autocorrelation length and filter coefficient length variations.Below in conjunction with drawings and Examples, the present invention is described in further detail.
Fig. 2 has provided and has obtained the overall sequential chart that the filter coefficient device obtains filter coefficient in the embodiment of the invention, just realizes the sequential chart of LD algorithm.It is 27 to describe that present embodiment continues with iterations.Should be appreciated that iterations of the present invention is not limited to this a kind of situation 27 times, also can select other iterations as required.For these 27 times, can be divided into for three steps again to finish: the first step is calculated reflectance value Tm at every turn, the second step calculating filter coefficient value P, and the 3rd step was calculated minimum error values Jmin.After receiving enabling signal, begin to carry out iteration, enabling signal can be outside input signal, each iteration is finished the calculating of reflection coefficient Tm, filter coefficient P (1)～P (m) and minimum error values Jmin in order successively, perhaps finishes reflection coefficient Tm, minimum error values Jmin and filter coefficient P (1)～P (m) successively.Because the minimum error values Jmin that this iteration obtains always is used for next iteration, so when carrying out last iteration promptly during the 27th iteration, can not carry out the calculating of Jmin value, promptly after the calculating of finishing P (1)～P (27) value, give external module with regard to exportable complement mark, the expression filter coefficient is finished as calculated, and external module just can read filter coefficient P (1)～P (27) after receiving complement mark.
Obtain each several part function that the device of filter coefficient finishes software described in the embodiment of the invention and transfer to different hardware modules respectively and finish, finally generate filter coefficient and output.See also Fig. 3, this device comprises that specifically coefficient of autocorrelation storer, error amount ask for module, reflection coefficient and ask for module, filter coefficient storage, filter coefficient and ask for module and six modules of top layer control module.
Wherein the coefficient of autocorrelation storer is used to store known coefficient of autocorrelation x (0)～x (27), receiving after coefficient of autocorrelation that the top layer control module sends reads enable signal and coefficient of autocorrelation and read address signal, finding corresponding coefficient of autocorrelation and export to that error amount is asked for module and reflection coefficient is asked for mould;
Error amount is asked for module and is used for finishing the minimum error values J of iteration each time
MinAsk for, and with minimum error values J
MinBe transferred to reflection coefficient and ask for module.Initial minimum error values is J
Min 0Come from the coefficient of autocorrelation storer, order
(corresponding first coefficient of autocorrelation value, this value is arithmetic number), this moment m=0, the m value adds 1 then, afterwards minimum error values J
Min mBy previous minimum error values J
Min M-1The reflection coefficient of asking for module and providing with reflection coefficient carries out computing and obtains, and the concrete operation process is
Reflection coefficient is asked for the asking for of reflectance value Tm that module is used for finishing iteration each time, and its input comes from coefficient of autocorrelation storer, filter coefficient storage and error amount and asks for module, and the concrete operation process is
Filter coefficient is asked for the asking for of filter coefficient P (m) that module is used for finishing iteration each time, the input of this module comes from reflection coefficient and asks for module and filter coefficient storage, and when k equaled 0, P (0) value was 1, when k was worth for other, the concrete operation process was:
As can be seen, the number of filter coefficient progressively increases progressively in each iteration, promptly the 1st iteration obtains P (1), the 2nd time iteration obtains P (1), P (2), the rest may be inferred, after iteration 27 times, obtain P (1), P (2) ..., P (27), each filter coefficient that obtains all is stored in the filter coefficient storage;
Filter coefficient storage is used to store the filter coefficient that obtains after each iteration is finished, the filter coefficient P that obtains when removing initialization
0(0) outside, the coefficient of iteration acquisition each time will be covered by the filter coefficient that next iteration obtains, that is to say the filter coefficient that utilizes the N time iteration of filter coefficient update that the N+1 iteration obtains, wherein N is a natural number, and for example the 1st iteration obtains P
1(1), at this moment preserves P in the filter coefficient storage
1(0), P
1(1); The 2nd time iteration obtains P
2(1), P
2(2), the filter coefficient of at this moment preserving in the filter coefficient storage is P
2(0), P
2(1), P
2(2); In like manner, after the 27th iteration, the filter coefficient of preserving in the filter coefficient storage is P
27(0), P
27(1), P
27(2) ..., P
27(27), P wherein
0(0), P
1(0) ... P
27(0) equates.
The top layer control module is finished above-mentioned 5 modules and storer: coefficient of autocorrelation storer, error amount are asked for module, reflection coefficient and are asked for the scheduling operation that module, filter coefficient storage, filter coefficient are asked for module.
Respectively each module is specifically described below in conjunction with accompanying drawing.
1, coefficient of autocorrelation storer
See also Fig. 4, Fig. 4 has provided the structural drawing of coefficient of autocorrelation storer, and that this example provides is RAM, coefficient of autocorrelation is written into storer in advance, wherein x_ren is that coefficient of autocorrelation is read enable signal, and x_radr is that coefficient of autocorrelation is read address signal, and these two signals are from the top layer control module; X_rdata is the coefficient of autocorrelation read data, and the output signal that is the coefficient of autocorrelation storer is a coefficient of autocorrelation.
The described RAM degree of depth can be 28, be used to deposit 28 known coefficient of autocorrelation x (the 0)～x (27) of input, when the storage coefficient of autocorrelation, the data of each address correspondence are the coefficient of autocorrelation of corresponding label, the i.e. corresponding x (0) in 0 address, the corresponding x (1) in 1 address ..., the corresponding x (27) in 27 addresses, the bit wide during the coefficient of autocorrelation storage can be decided according to input.If when the coefficient of autocorrelation of input does not have 28, then the coefficient of autocorrelation of back is all write 0.When for example only importing 10 coefficient of autocorrelation, then x (0)～x (9) corresponds to 10 autocorrelation value of input, and x (10)～x (27) mends 0.
The coefficient of autocorrelation storer receives after coefficient of autocorrelation that the top layer control module sends reads enable signal x_ren and coefficient of autocorrelation and read address signal x_radr, find corresponding data just coefficient of autocorrelation export to as the x_rdata signal that error amount is asked for module and reflection coefficient is asked for module.
2, error amount is asked for module
See also Fig. 5, Fig. 5 has provided the structural drawing that error amount is asked for module, and error amount is asked for module and comprised initialization unit and error calculation unit two parts as can be seen.
Wherein be provided with the error amount register in the initialization unit.After receiving enabling signal m_start, for example when the m_start rising edge is effective, first autocorrelation value x (0) in the coefficient of autocorrelation storer is latched in the error amount register, finish initialization;
Comprise in the error calculation unit, multiplier A, first gets conjugate unit, first d type flip flop, multiplier B, second d type flip flop, subtracter and 3d flip-flop.
Reflection coefficient mould square computing unit can be got conjugate unit by multiplier A and first and forms, and the reflection coefficient register divides the two-way output reflection coefficient, and one the tunnel arrives multiplier A after getting conjugate unit through first, and another road directly arrives multiplier A; Multiplier A is a complex multiplier, and this two-way is carried out multiplication operations, obtain the reflection coefficient mould square | T
m|
2
Then the reflection coefficient mould square | T
m|
2Send first d type flip flop to; After the reflection coefficient renewal enabling signal j_en that first d type flip flop receives is effective, will | T
m|
2Latch a beat and export to next multiplier B; Preserve minimum error values J in the error amount register
Min, and output J
MinGive multiplier B and subtracter.
Multiplier B is right | T
m|
2And J
MinCarry out multiplication operations, and with product | T
m|
2J
MinExport to subtracter after latching a beat again by second d type flip flop; The minimum error values J that subtracter utilizes the error amount register directly to send
MinDeduct the product of second d type flip flop output | T
m|
2J
Min, obtain the minimum error values of this iteration, export to 3d flip-flop then; After subtraction was finished, it is effective that indicator signal j_end is finished in the error amount renewal, and the minimum error values that 3d flip-flop obtains this iteration is latched in the error amount register, and upgrade original minimum error values of preserving
Signal m_start, signal j_en, three signals of signal j_end all are monopulse useful signals in the present embodiment, and it is effective to be rising edge, and all from the top layer control module.
3, reflection coefficient is asked for module
See also Fig. 6, Fig. 6 has provided the structural drawing that reflection coefficient is asked for module, and reflection coefficient is asked for module and comprised that multiplier C, four d flip-flop, first adder, the 5th d type flip flop, second get conjugate unit, divider, the 6th d type flip flop and reflection coefficient register.
When carrying out the m time iteration, obtained m-1 filter coefficient, the 1st coefficient of autocorrelation that m-1 filter coefficient of multiplier C receiving filter coefficient memory output and coefficient of autocorrelation storer are exported, and carry out a multiply operation, obtain first product, send four d flip-flop to, continue then m-2 filter coefficient and the 2nd coefficient of autocorrelation are multiplied each other, obtain second product, and the like, obtain m product, just the product of the 0th filter coefficient and m coefficient of autocorrelation; With iteration for the third time is example, is respectively P
3(2) x (1), P
3(1) x (2), P
3(0) x (3).
The product that four d flip-flop obtains multiply operation is delivered to totalizer after latching a beat; Behind the 5th d type flip flop beat of signal latch with totalizer output, divide two tunnel transmission, the one road delivers to divider, and one the tunnel feeds back to first adder; First product addition that first adder feeds back at second sum of products the 5th d type flip flop of enable signal cc_en valid period to four d flip-flop output that add up, the result who obtains feeds back to first adder through the 5th d type flip flop, again with the 3rd product addition, and the like the operation that adds up, obtain the 1st sum P to m product
3(2) x (1)+P
3(1) x (2)+P
3(0) x (3).
Divider receives the 5th d type flip flop and latchs the accumulation result of exporting behind the beat, and the error amount minimum error values of asking for the output of error amount register in the module is through second the value after getting conjugate unit, divider enabling signal div_start arrives and just finishes adding up of m product when for example rising edge is effective constantly, start divider simultaneously, with the conjugation of accumulation result divided by minimum error values.The algorithm that divider adopts displacement to subtract each other carries out, and the umber of beats that the dividend bit wide decision of minimum error values conjugation just needs after the divider computing is finished, obtains reflection coefficient T
3, and export divider end mark signal div_end to the top layer control module, reflection coefficient is delivered to the 6th d type flip flop; Upgrade at reflection coefficient that the 6th d type flip flop latchs reflection coefficient in the reflection coefficient register when finishing indicator signal t_end effectively for example rising edge is effective.
The enable signal cc_en that adds up is the useful signals of clapping more, divider enabling signal div_start, reflection coefficient upgrades finishes indicator signal t_end, divider is finished indicator signal div_end, all are monopulse useful signals, and except the div_end signal exported the top layer control module to, other three signals all were from the top layer control module.
4, filter coefficient is asked for module
See also shown in Figure 7ly, Fig. 7 has disclosed the structure that filter coefficient is asked for module, and filter coefficient asks for module and comprise that the 3rd gets conjugate unit, multiplier D, the 7th d type flip flop, second adder, selector switch and the 8th d type flip flop.
Filter coefficient storage gets conjugate unit with the 3rd respectively and second adder links to each other, be used to export the filter coefficient that last iteration is preserved, export a k filter coefficient to the three and get conjugate unit, m-k filter coefficient be to second adder, 1＜=k＜=m-1.With by the second time iteration coefficient calculations for the third time the iteration coefficient be example, be specially here output the 1st FACTOR P
2(1) gets conjugate unit, the 2nd FACTOR P to the 3rd
2(2) to second adder, the one road delivers to the 3rd gets conjugate unit, and one the road delivers to second adder; The 3rd gets conjugate unit to filter coefficient P
2(1) gets conjugate operation, obtain (P
2(1))
*, (P
2(2))
*, and with (P
2(1))
*, (P
2(2))
*Deliver to multiplier D; The reflection coefficient register that error amount is asked in the module links to each other with selector switch with multiplier D respectively, exports this reflection coefficient T
3Give multiplier D; Multiplier D is to the conjugation (P of the 1st filter coefficient
2(1))
*, and reflection coefficient T
3Carry out multiplication operations, product (P
2(1))
*T
3Deliver to the 7th d type flip flop; The 7th d type flip flop is delivered to second adder after product is latched a beat; Product after second adder will postpone and the 2nd filter coefficient P
2(2) addition obtains being (P
2(1))
*T
3+ P
2(2) i.e., iterative filter FACTOR P for the third time
3(2), export the 2nd FACTOR P
2(2) get conjugate unit, the 1st FACTOR P to the 3rd
2(1) to second adder, so operate, can obtain another filter coefficient P of this iteration
3(1), can certainly obtain P as required successively
3(1), P
3(2).
Because iteration all can increase a filter coefficient each time, to m filter coefficient increasing newly P for example
3(3), can make it equal reflection coefficient, be T herein
3Therefore provide a selector switch, present embodiment is the selector switch of alternative, and 0 input end receives the output signal of second adder, and the reflection coefficient of 1 input end reception reflection coefficient register output is T for example
3Sel is for selecting signal, and the result after selecting to export delivers to the 8th d type flip flop; The 8th d type flip flop latchs the filter coefficient that this iteration obtains when filter coefficient update output enable signal p_en is effective, and deliver in the filter coefficient storage, in order to express needs, filter coefficient in these up-to-date writing filtering device coefficient memories is called as p_wdata, and the filter coefficient that filter coefficient storage utilizes p_wdata to upgrade last iteration preservation promptly utilizes P
3(1), P
3(2) and P
3(3) replace P
2(1) and P
2(2).Thereby the filter coefficient that obtains afterwards through this iteration is P
3(0), P
3(1), P
3(2) and P
3(3), select signal sel and filter coefficient update output enable signal p_en all from the top layer control module.
5, filter coefficient storage
See also shown in Figure 8ly, Fig. 8 has disclosed the structure of filter coefficient storage, and filter coefficient is asked for module and comprised 6 alternative selector switchs and ping-pong ram.The degree of depth of table tennis RAM and pang RAM all is set to 28 according to the number of the 27th iteration postfilter, and the data of each address correspondence are the filter coefficient of corresponding label, i.e. the corresponding P (0) in 0 address, the corresponding P (1) in 1 address, ..., the corresponding P (m) in m address, the bit wide of data is decided according to output.Because what adopt when calculating this iterative filter coefficient is original filter coefficient of preserving, filter coefficient read/write conflict when therefore adopting the ping-pong ram structure to avoid filter coefficient update, suppose this iteration when upgrading filter coefficient value be upgrade successively in order P (1), P (2) ... P (m), like this in iteration for the third time during calculating filter coefficient, because P (1)～P (2) value that need to keep this moment is not the value P of last iteration
2(1) and P
2But value P (2), through upgrading after this iteration
3(1), P
3(2), thus need to adopt ping-pong ram to come the memory filter coefficient value, the feasible filter coefficient P that is used for this iteration
2(1) and P
2(2) if from table tennis (or pang) when RAM reads, the filter coefficient P that newly obtains
3(1), P
3(2) write pang (or table tennis) RAM.And the initial value P (0) of filter coefficient just is initialised to when to be enabling signal m_start effective among table tennis RAM and pang the RAM simultaneously, all no longer does renewal in the later iteration.
Pp_flag among Fig. 8 ,～pp_flag is a ping-pong ram switching mark signal, p_wen is that filter coefficient is write enable signal, p_wadr is the filter coefficient writing address signal, p_wdata is the wave filter write data, p_ren is that filter coefficient is read enable signal, p_radr is that filter coefficient is read address signal, p_rdata is the filter coefficient read data, it wherein is the output signal of filter coefficient storage except p_rdata, p_wdata asks for module from filter coefficient, and other 6 signals are input signal and all come from the top layer control module.
When ping-pong ram switching mark signal～pp_flag is 1, two reverse selector switchs on the right and selector switch 1 passage conducting are read enable signal p_ren and filter coefficient according to filter coefficient and are read address signal p_radr read for example filter coefficient P that produces of iteration for the second time of already present last iterative filter coefficient from pang RAM
2(1) and P
2(2), output is used to carry out iteration for the third time as signal p_rdata; At this moment pp_flag is 0, three reverse selector switch 0 passage conductings on the left side are write enable signal p_wen and filter coefficient writing address signal p_wadr according to filter coefficient and are write for example FACTOR P that produces of iteration for the third time of filter coefficient that this iteration produces to table tennis RAM
3(1), P
3(2) and P
3(3), these three coefficients write table tennis RAM as signal p_wdata; During the 4th iteration, pp_flag becomes 1, and～pp_flag becomes 0, three of the left side reverse selector switch 1 passage conductings at this moment, and pang RAM is used to store the i.e. filter coefficient P of the 4th iteration generation of new iteration
4(1), P
4(2), P
4(3) and P
4(4), these four coefficients write pang RAM as signal p_wdata, and table tennis RAM continues to preserve the FACTOR P of iteration generation for the third time
3(1), P
3(2) and P
3And export these three coefficients and be used for iteration the 4th time (3), as signal p_rdata; When carrying out the 5th iteration, pp_flag becomes 0 again, and at this moment table tennis RAM begins to preserve the coefficient of the 5th iteration generation, and pang RAM continues to preserve the coefficient of the 4th iteration generation.
Be not difficult to think to reach, also can adopt the register-stored filter coefficient here, do like this hardware resource requirements is increased, realize complicated more on the sequential;
6, top layer control module
The top layer control module is responsible for producing the timing control signal of each module, reaches the scheduling to each module.See also Fig. 9, Fig. 9 has disclosed the structural drawing of top layer control module, and the top layer control module comprises three counters, coefficient of autocorrelation read control signal generator and filter coefficient read-write control signal generator; Comprise a plurality of d type flip flops in addition.
Can produce ping-pong ram switching mark pp_flag signal according to counter 1; According to counter 1 sum counter 2, can produce coefficient of autocorrelation read control signal x_ren and x_radr; Can produce output according to counter 3 and select signal sel, can produce filter coefficient read-write control signal p_ren, p_radr, p_wen and p_wadr according to counter 2 sum counters 3; Make a call to one and clap the back and obtain t_end according to ask for div_end sign register that module sends here from reflection coefficient, and then make a call to one and clap generation j_en, then make a call to two clap the j_end signal.
See also Figure 10, Figure 10 has provided the course of work of 3 counters.At first counter 1 puts 1 to counter when algorithm enabling signal m_start is effective, adds 1 at the iterations enable signal m_next that adds up when effective, finishes 1～27 tally function; Counter 2 is when algorithm enabling signal m_start is effective, and is clear 0 to counter, puts number when effective and is m_cnt at the iterations enable signal m_next that adds up, and m_cnt is the value of last iteration here, begins then to count down, up to being 0; Counter 3 when algorithm enabling signal m_start is effective or reflection coefficient calculate and to finish signal t_end to put number when effective be 2, when the enable signal p_cnt_add_en that adds up is effective, add 1 then, finish the function that 2～2m_cnt counts; Add up enable signal when reflection coefficient calculates finish indicator signal t_end effectively and m_cnt put 1 when being not 1, when counting down to 2m_cnt-1 or algorithm enabling signal when effective clear 0.
Coefficient of autocorrelation read control signal generator mainly comprises d type flip flop and subtracter, as shown in Figure 10, T calculates and selects number enable signal t_en can be used in read enable signal x_ren as coefficient of autocorrelation, t_en can utilize this d type flip flop to obtain, t_en it algorithm enabling signal m_start effectively or the iterations enable signal m_next that adds up put 1 when effective, when t_cnt is 0 clear 0, wherein the m_next signal can utilize a selector switch to obtain, when m_cnt equals 27, this selector switch exported for 0 (representing with a bit), otherwise output j_end signal.The inhibit signal of t_en is as adding up enable signal cc_en; Can produce ping-pong ram switching mark pp_flag signal according to counter 1 in addition, for example pp_flag can be according to utilizing m_cnt[0] lowest bit switched of value m_cnt[0 just] as the pp_flag signal; According to counter 1 sum counter 2, can produce coefficient of autocorrelation and read address signal x_radr, the value t_cnt that for example utilizes the value m_cnt of iterations counter (counter 1) to deduct reflection coefficient down counter (counter 2) determines address signal x_radr, (this subtracter is not shown).
Filter coefficient read-write control signal generator mainly comprises d type flip flop, selector switch and arithmetic logic unit, as shown in figure 10, P calculate select number enable signal p_en work as reflection coefficient calculate finish indicator signal t_end effectively and m_cnt put 1 when being not equal to 1, when p_cnt count down to 2m_cnt-1 clear 0; The p_en signal is produced filter coefficient read control signal p_ren signal behind the exclusive disjunction mutually with the t_en signal logic, reading address signal p_radr is that p selects Signal Message Address p_adr signal, the p_adr signal demand produces by 3 grades of selector switchs, the first order is passed through p_cnt[0] select p_cnt[5:1] still m_cnt-p_cnt[5:1], the second level by the p_en signal effectively and p_cnt when being not equal to 2m_cnt selected be 0 or previous stage select output valve, the third level is selected t_cnt or second level output by the t_en signal.Filter coefficient is write enable signal p_wen and can be produced according to p_en and p_end signal, the lowest order p_cnt[0 of the inhibit signal of p_en and p_cnt for example] carry out logical OR with p_end again behind the logical and and can obtain p_wen, and the p_end signal obtains according to the negative edge of the inhibit signal of p_en, and writing address signal p_wadr is according to high 5bit count value p_cnt[5:1] high 5bit count value p_cnt[5:1 just] inhibit signal of signal produces.
See also shown in Figure 11ly, Figure 11 has disclosed the sequential relationship of each counter, and m_start is the algorithm enabling signal, and m_end is the algorithm end signal.After algorithm enabling signal m_start is effective, begin three counters are put initial value.When counter m_cnt counts new value, for example the value of m_cnt becomes at 3 o'clock from 2, counter t_cnt also begins to count down accordingly, initial value be the previous count value of counter m_cnt also with regard to the time 2, after counter t_cnt counts down to 0, begin to start p_cnt counter accumulated counts, the p_cnt initial value is fixed as 2, and the higher limit of accumulated value is 2*m_cnt.
In 6 modules mentioning, there are many places to use multiplier in the above,,, promptly all stagger, finish time division multiplex by the moment that will use multiplier so the multiplier in the module is carried out multiplexing because that multiplier unit consumes in hardware resource is bigger.
See also Figure 12, Figure 12 has disclosed the implementation structure figure of time division multiplex multiplier in the embodiment of the invention, and multiplexing multiplier can replace these four multipliers of multiplier A, multiplier B, multiplier C and multiplier D by time-sharing multiplex; Perhaps replace wherein two or three, for example replace multiplier A and multiplier B, multiplier C and multiplier D are kept; Can also replace with two multiplexing multipliers further, each multiplexing multiplier is respectively replaced two, and for example a time division multiplex multiplier is replaced multiplier A and multiplier B, and another time division multiplex multiplier is replaced multiplier C and multiplier D.Multiplexing multiplier specifically comprises a multiplication unit, two MUX, and the MUX way equals the number of the multiplier replaced, and these two MUX adopt same input end to select control signal.Wherein the input of multiplexing multiplier select control signal just the selection control signal of two selector switchs from the top layer control module, this signal demand is used the sequential of counter 1 (m_cnt[4:0]), counter 2 (t_cnt[4:0]) sum counter 3 (p_cnt[5:0]), selects control signal to determine the conducting of a concrete paths in the MUX by input.When supposing to need to use multiplier A, select control signal to select two current input ends of multiplexing multiplier all to correspond to two input ends of multiplier A by input, the result that the multiplication unit computing draws is exactly the result of multiplier A, can realize the function of multiplier A.
Technical solution of the present invention can realize by ASIC (special chip) when utilizing hardware to realize the Levinson-Durbin algorithm, and implementation structure is more flexible, is adapted to ask for each rank filter coefficient; The special multiplexing process of passing through utilizes a time division multiplex multiplier to realize the function of a plurality of multipliers, can save hardware resource consumption, helps chip design and the popularization in hardware.
To the present invention, in realization, can further adopt multistage flowing water to realize, such as with error of calculation value Jmin and calculating filter coefficient value P parallel processing, add one-level flowing water, sequential time delay will reduce like this, but need the multipliers that increase more.
The hardware implementation structure of mentioning among the present invention in addition is a kind of universal architecture, even also applicable when coefficient of autocorrelation length and filter coefficient length variations.
Obviously, those skilled in the art can carry out various changes and modification to the present invention and not break away from the spirit and scope of the present invention.Like this, if of the present invention these are revised and modification belongs within the scope of claim of the present invention and equivalent technologies thereof, then the present invention also is intended to comprise these changes and modification interior.
Claims (9)
1. a device that obtains coefficient of linear prediction wave filter is characterized in that, comprising:
The coefficient of autocorrelation storer, storage is used for the coefficient of autocorrelation of iteration;
Reflection coefficient is asked for module, is used for finishing the asking for of reflectance value of iteration each time;
Error amount is asked for module, is used for finishing the asking for of minimum error values of iteration each time;
Filter coefficient is asked for module, is used for finishing the asking for of filter coefficient of iteration each time;
Filter coefficient storage is stored the filter coefficient that obtains after each iteration is finished;
The top layer control module is used to produce the read-write control signal of above-mentioned each module and storer, and each module and storer are read and write scheduling;
Wherein, described reflection coefficient is asked for the minimum error values that module asks for the last iteration that module provides according to the filter coefficient of the coefficient of autocorrelation in the described coefficient of autocorrelation storer, last iteration and described error amount and is carried out computing, obtains the reflection coefficient of this iteration;
Described error amount is asked for the reflection coefficient that module asks for this iteration that module provides according to the minimum error values of last iteration and described reflection coefficient and is carried out computing, obtains the minimum error values of this iteration;
Described filter coefficient asks for that module is asked for the reflection coefficient of this iteration that module provides according to described reflection coefficient and the filter coefficient of the last iteration in the described filter coefficient storage carries out computing, obtain the filter coefficient of this iteration, and be saved in the described filter coefficient storage;
Described top layer control module comprises first counter, second counter, the 3rd counter, coefficient of autocorrelation read control signal generator and filter coefficient read-write control signal generator, wherein
First counter is used to indicate iterations, and produces control signal pp_flag according to the first counter lowest order;
Second counter is used for beginning to count down when the first counter meter during to new value, and initial value is first Counter Value of last iteration, until being decremented to 0;
The 3rd counter is used for after second Counter Value is 0, the beginning accumulated counts, and up to 2 times of values of this iteration first counter, its initial value is fixed as 2;
Coefficient of autocorrelation read control signal generator is used for the count value according to first counter and second counter, produces reading enable signal and reading address signal of visit coefficient of autocorrelation storer;
Filter coefficient read-write control signal generator is used for the count value according to second counter and the 3rd counter, produces filter coefficient read-write enable signal and read/write address signal.
2. device as claimed in claim 1, it is characterized in that, described filter coefficient storage is the filter coefficient update module, is used for utilizing when the memory filter coefficient filter coefficient of the N time iteration of filter coefficient update of the N+1 time iteration, and N is a natural number.
3. device as claimed in claim 1 is characterized in that, described error amount is asked for module and comprised error amount register and error calculation unit,
Described error amount register is used to receive the outside enabling signal m_start that sends of described device, and reads the initial value of first autocorrelation value as minimum error values from described coefficient of autocorrelation storer;
Described error calculation unit is used for obtaining the minimum error values of this iteration and being used for upgrading the minimum error values of last iteration in the described error amount register according to the minimum error values that described reflection coefficient is asked for the last iteration of the reflection coefficient of this iteration that module provides and described error amount register.
4. device as claimed in claim 3 is characterized in that, described error calculation unit comprises reflection coefficient mould square computing unit, first d type flip flop, multiplier B, second d type flip flop, subtracter and 3d flip-flop, wherein
The output terminal of reflection coefficient mould square computing unit links to each other with the first d type flip flop input end, and the output terminal of first d type flip flop links to each other with the input end of multiplier B;
Another input end of multiplier B links to each other with described error amount register, is used to receive the minimum error values of last iteration, and the output terminal of multiplier B links to each other with the second d type flip flop input end;
The second d type flip flop output terminal links to each other with an input end of subtracter, and another input end of subtracter links to each other with described error amount register, is used to receive the minimum error values of last iteration;
Subtracter is exported the minimum error values of this iteration, and the subtracter output terminal links to each other with the 3d flip-flop input end, and the 3d flip-flop output terminal links to each other with described error amount register, is used to export the minimum error values of this iteration.
5. device as claimed in claim 1, it is characterized in that, described reflection coefficient is asked for module and is comprised that multiplier C, four d flip-flop, first adder, the 5th d type flip flop, second get conjugate unit, divider, the 6th d type flip flop and reflection coefficient register, wherein
The input end of multiplier C links to each other with described coefficient of autocorrelation storer, and another input end links to each other with described filter coefficient storage;
The output terminal of multiplier C links to each other with the input end of four d flip-flop, and the output terminal of four d flip-flop links to each other with an input end of first adder;
The output terminal of first adder links to each other with the input end of the 5th d type flip flop, and the output terminal of the 5th d type flip flop links to each other with another input end of first adder and an input end of divider;
Second gets the conjugate unit input end asks for module with described error amount and links to each other, output terminal links to each other with another input end of divider, be used to provide the conjugation of the minimum error values of last iteration, divider carries out divide operations after receiving the divider enabling signal that described top layer control module sends, be used to export the reflection coefficient of this iteration;
The 6th d type flip flop input end receives the reflection coefficient of this iteration, and output terminal links to each other with described reflection coefficient register;
Described reflection coefficient register is used to preserve the reflection coefficient of this iteration.
6. device as claimed in claim 5 is characterized in that, described filter coefficient is asked for module and comprised that the 3rd gets conjugate unit, multiplier D, the 7th d type flip flop, second adder, selector switch and the 8th d type flip flop, wherein
The 3rd input end of getting conjugate unit links to each other with described filter coefficient storage, and output terminal links to each other with the input end of multiplier D;
Another input end of multiplier D is asked for module with described reflection coefficient and is linked to each other, and receives the reflection coefficient of this iteration, and output terminal links to each other with the input end of the 7th d type flip flop;
The output terminal of the 7th d type flip flop links to each other with an input end of second adder, and another input end of second adder links to each other with described filter coefficient storage, is used to receive the filter coefficient of last iteration;
0 input end of selector switch links to each other with the output terminal of second adder, and 1 input end is asked for module with described reflection coefficient and linked to each other, and control end receives the selection signal sel that described top layer control module sends, and exports the filter coefficient of this iteration;
The input end of the 8th d type flip flop links to each other with the output terminal of selector switch, and output terminal links to each other with filter coefficient storage.
7. device as claimed in claim 6 is characterized in that, described multiplier C and multiplier D can utilize a multiplexing multiplier to realize, described multiplexing multiplier is the time division multiplex multiplier, comprises a multiplication unit and two MUX, wherein
Described multiplication unit is a complex multiplier, is used to realize that complex multiplication or real number multiply each other;
Described two MUX are used to receive identical control signal, and export one road signal respectively to the input signal of described multiplication unit as described multiplication unit.
8. device as claimed in claim 1 is characterized in that, described filter coefficient is asked for module and comprised that the 3rd gets conjugate unit, multiplier D, the 7th d type flip flop, second adder, selector switch and the 8th d type flip flop, wherein
The 3rd input end of getting conjugate unit links to each other with described filter coefficient storage, and output terminal links to each other with the input end of multiplier D;
Another input end of multiplier D is asked for module with described reflection coefficient and is linked to each other, and receives the reflection coefficient of this iteration, and output terminal links to each other with the input end of the 7th d type flip flop;
The output terminal of the 7th d type flip flop links to each other with an input end of second adder, and another input end of second adder links to each other with described filter coefficient storage, is used to receive the filter coefficient of last iteration;
0 input end of selector switch links to each other with the output terminal of second adder, and 1 input end is asked for module with described reflection coefficient and linked to each other, and control end receives the selection signal sel that described top layer control module sends, and exports the filter coefficient of this iteration;
The input end of the 8th d type flip flop links to each other with the output terminal of selector switch, and output terminal links to each other with filter coefficient storage.
9. device as claimed in claim 1 is characterized in that, described filter coefficient storage comprises a selector switch, five reverse selector switchs, table tennis RAM and pang RAM, wherein
The control end of a described selector switch receives the first control signal pp_flag, and 0 input end receives the filter coefficient of table tennis RAM output or the filter coefficient that 1 input end receives pang RAM output;
Input is read enable signal and is received first control signal with the control end of importing two reverse selector switchs reading address signal respectively, and 0 output terminal is connected with table tennis RAM respectively or 1 output terminal is connected with pang RAM respectively;
Input filter coefficient, the input control end of three reverse selector switchs of writing enable signal and input writing address signal receives second control signal respectively, and 0 output terminal is connected with table tennis RAM respectively or 1 output terminal passes with pang RAM respectively and is connected; And
Described first control signal and second control signal be designature each other.
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