CN101154155A - Virtual hardware system and instruction executing method based on virtual hardware system - Google Patents
Virtual hardware system and instruction executing method based on virtual hardware system Download PDFInfo
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Abstract
The invention discloses a virtual hardware system comprising a father hardware and a virtual hardware, wherein, the father hardware reads instruction data from the virtual hardware, operates a processing flow corresponding to the instruction data and sends the processing result to the virtual hardware, and the virtual hardware stores instruction data with mapping relation to the preappointed instruction and receives the processing result from the father hardware. The invention also discloses an instruction execution method based on the virtual hardware. The invention is capable of reading and converting the instruction data of a virtual hardware via the father hardware, calling internal resources, such as performance function and various advanced resources according to the instruction, and utilizing the called internal resources to operate the processing flow corresponding to the instruction, thereby reducing instruction execution cycle and increasing instruction execution speed of the virtual hardware. Moreover, the invention does not need to store the same logic code for realizing the same function in the father hardware and the virtual hardware respectively, thus saving system resources.
Description
Technical field
The present invention relates to computer technology, particularly virtual hardware system reaches the instruction executing method based on virtual hardware system.
Background technology
In the computer system, comprise the processor that is used to carry out the particular system instruction set.Different types of processor only can be carried out the pairing instruction set of such processor, and promptly the instruction set of different processor is incompatible.Yet, by carrying out different instruction set, all types of processors can embody different performance advantages, and for example the instruction set of Intel80X86 CPU (central processing unit) (CPU) can realize complicated processing capacity based on complex instruction set computer (CISC) (CICS) form; And the instruction set of Motorola Power PC then based on Reduced Instruction Set Computer (RISC) form, can be carried out the simple process function at a high speed.
Prior art constitutes another kind of processor by the emulation logic unit by in a kind of processor, and the instruction operation process by emulation another kind processor, solves the incompatibility of different instruction collection.In the in esse processor, realize that the hardware resource of original function is called father's hardware, the hardware resource that is made of the emulation logic unit is called virtual hardware.In the virtual hardware system based on the virtual hardware technology, father's hardware can merge the performance advantage of different processor, has cross-platform independence, can guarantee the binary compatible of the code write for virtual hardware when father's hardware platform is changed; And, when the developing instrument of father's hardware is difficult for realizing, can enriches exploitative virtual hardware and compile by having, thereby reduce development difficulty.
Fig. 1 is based on the instruction executing method process flow diagram of virtual hardware system in the prior art.As shown in Figure 1, be that A processor, virtual hardware are that the B processor is an example with father's hardware, the instruction executing method based on virtual hardware system in the prior art may further comprise the steps:
Instruction after step 104, A processor carry out to transform, and the result that will instruct returns to the data memory space of B processor, returns step 102, the A processor continues to read next bar director data of B processor.
In the above-mentioned flow process, the A processor need read and change each bar instruction in the process of utilizing virtual hardware B processor operating instruction flow process, carry out the instruction of a B processor, may need the instruction of many A processors to realize.
This shows, in the existing virtual hardware system, father's hardware is simulated the execution process instruction of virtual hardware by the mode that reads, transforms instruction one by one, therefore, the instruction that father's hardware is carried out each bar virtual hardware all needs tens even up to a hundred instruction cycles, execution speed is slow, can't satisfy the calculation process process of high performance requirements.And, because father's hardware is simulated the execution process instruction of virtual hardware by the mode that reads, transforms instruction one by one, instruction is carried out and is only limited to the bottom instruction, thereby, existing virtual hardware also can't use the senior resource in father's hardware, the limited resources that only can use father's hardware to distribute make that the range of application of virtual hardware system is less.
Summary of the invention
In view of this, a fundamental purpose of the present invention is: a kind of virtual hardware system is provided, can executes instruction at a high speed.
Another fundamental purpose of the present invention is: a kind of instruction executing method based on virtual hardware system is provided, can executes instruction at a high speed based on virtual hardware.
A fundamental purpose according to above-mentioned the invention provides a kind of virtual hardware system, comprising: father's hardware and virtual hardware, wherein,
Father's hardware, reading command data from virtual hardware, the treatment scheme of the director data correspondence that operation is read; Send result to virtual hardware;
Virtual hardware is used to store and director data that the instruction of making an appointment has mapping relations; Reception is from the result of described father's hardware.
Described father's hardware comprises: main control unit, main with the location of instruction and resource transfer unit, wherein,
Main control unit is used to receive the instruction of described father's hardware of independently using the location of instruction, and reading command data from virtual hardware are converted into the instruction that father's hardware can be carried out with the director data that reads; According to the instruction after transforming, from virtual hardware, read the corresponding computing variable of this instruction; When the instruction after transforming is the external call instruction, call internal resource in the resource transfer unit by system call interfaces, described system call interfaces is the mapping relations table between various special instructions and the internal resource; The computing variable that utilization reads moves the internal resource from the resource transfer unit, and the result that obtains is sent to virtual hardware;
Main use the location of instruction, be used to store the instruction of described father's hardware, and when powering on, instruction is offered main control unit in system;
The resource transfer unit is used to store internal resource, and offers main control unit by system call interfaces.
Described main control unit is further used for, and when the instruction after the described conversion is ordinary instruction, carries out ordinary instruction, and the result of ordinary instruction is sent to described virtual hardware.
Described system further comprises: the master uses data storage cell, is used to store the corresponding computing variable of all instructions of father's hardware, and offers main control unit;
Main control unit is further used for the corresponding computing intermediate value of each bar instruction is sent to the main data storage cell of use, and when next bar instruction of operation, according to this instruction from the master with reading the computing intermediate value the data storage cell.
Described main control unit is electrically-erasable ROM (read-only memory) E
2PROM or random access memory ram;
Described master is a read only memory ROM with the location of instruction;
Described master is RAM with data storage cell;
Described resource transfer unit is E
2PROM.
Described virtual hardware comprises: fictitious order storage unit and virtual data storage unit, wherein,
The fictitious order storage unit is used to store the director data of described virtual hardware, and director data is offered described father's hardware;
The virtual data storage unit is used to receive the result from described father's hardware.
Described fictitious order storage unit is E
2PROM;
Described virtual data storage unit is RAM.
Described father's hardware is the XA2 processor, and described virtual hardware is 8051 processors.
According to another above-mentioned fundamental purpose, the invention provides a kind of instruction executing method based on virtual hardware system, may further comprise the steps:
A, father's hardware read the director data in the virtual hardware, according to the mapping relations of the agreement instruction that sets in advance with father's hardware internal resource, call the internal resource of the director data correspondence that reads;
The internal resource that B, the utilization of father's hardware are called, the treatment scheme of the instruction correspondence after operation transforms returns to virtual hardware with result.
Further comprise before the described steps A: give virtual hardware with the memory allocation of described father's hardware, as the instruction storage space and the data space of described virtual hardware;
The described director data that reads in the virtual hardware of steps A is: father's hardware is according to the instruction of storage inside, reading command data from the instruction storage space of virtual hardware.
Described steps A further comprises: father's hardware reads the computing variable of the described director data correspondence that reads from virtual hardware from the data space of virtual hardware.
Director data in the described conversion virtual hardware of steps A is: the instruction set rule according to the virtual hardware correspondence is converted into the instruction that father's hardware can be carried out with the director data that reads.
Described agreement instruction is the external call instruction;
The described internal resource that calls of steps A is: judge whether the instruction after transforming is the external call instruction, if then according to the external call instruction after transforming, by described mapping relations, call the power function of father's hardware storage inside.
Whether the instruction after described judgement transforms is that the external call instruction is: whether the subroutine address of judging the instruction calls after transforming is in the normal range, if not, judge again whether described instruction exists mapping relations with father's hardware internal resource, if judge that then the instruction after the described conversion is the external call instruction.
Whether the instruction after described judgement transforms is that the external call instruction is: judge whether the instruction after transforming is specific coding, and whether described instruction exist mapping relations with father's hardware internal resource, if the instruction after the then described conversion is the external call instruction.
Described steps A further comprises: the instruction after judging described conversion is not after the external call instruction, carries out the instruction after the described conversion, and result is returned to virtual hardware.
The treatment scheme of the instruction correspondence after the described operation of step B transforms is: according to the computing variable that reads, and the internal resource that operation is called.
Step B is described to return to virtual hardware with result and is: the data space that result is sent to virtual hardware.
As seen from the above technical solution, the present invention is by the director data of a virtual hardware of father's hardware reading and converting, according to this instruction calls internal resource, for example power function and multiple senior resource, and utilize the internal resource that calls, and move the corresponding treatment scheme of this instruction, substitute many instruction interaction processes with virtual hardware, reduce instruction execution cycle, thereby improved the instruction execution speed of virtual hardware.And the present invention need not store the identity logic code that is used to realize identical function respectively by calling the internal resource of father's hardware in father's hardware and virtual hardware, saved system resource.
Description of drawings
Fig. 1 is based on the instruction executing method process flow diagram of virtual hardware system in the prior art.
Fig. 2 is the exemplary block diagram of virtual hardware system among the present invention.
Fig. 3 among the present invention based on the exemplary process diagram of the instruction executing method of virtual hardware system.
Fig. 4 is the structural drawing of virtual hardware system in the embodiment of the invention.
Fig. 5 is based on the instruction executing method process flow diagram of virtual hardware system in the embodiment of the invention.
Embodiment
For making purpose of the present invention, technical scheme and advantage clearer, below with reference to the accompanying drawing embodiment that develops simultaneously, the present invention is described in more detail.
Basic thought of the present invention is: the director data of a virtual hardware of father's hardware reading and converting, according to this instruction calls internal resource, and utilize the internal resource that calls, and move the corresponding treatment scheme of this instruction.
Wherein, be used for the instruction that instruction that father's hardware calls internal resource is made an appointment for father's hardware and virtual hardware,, promptly between instruction of making an appointment and internal resource, have mapping relations as the external call instruction etc.Wherein, internal resource can be power function, also can be senior resources such as file system.
Fig. 2 is the exemplary block diagram of virtual hardware system among the present invention.As shown in Figure 2, virtual hardware system of the present invention comprises: father's hardware 201 and virtual hardware 202.
Father's hardware 201 is used for from virtual hardware 202 reading command data, the treatment scheme of the instruction correspondence that operation is read; Send result to virtual hardware 202;
Wherein, in the instruction set of virtual hardware 202, comprise the corresponding director data of external call instruction with father's hardware, also comprise the director data corresponding with the ordinary instruction of father's hardware, father's hardware 201 is only after reading the director data corresponding with the external call instruction, can call internal resource, as the power function etc. of storage.
Fig. 3 among the present invention based on the exemplary process diagram of the instruction executing method of virtual hardware system.As shown in Figure 3, the instruction executing method that the present invention is based on virtual hardware system may further comprise the steps:
Wherein, when the instruction after father's hardware transforms is ordinary instruction, can be according to the method for prior art, the instruction in the reading and converting instruction set one by one.
Below, in conjunction with specific embodiments, be elaborated to virtual hardware system of the present invention with based on the instruction executing method of virtual hardware system.
Present embodiment is high speed expansion structure microprocessor (the Smart eXtended Architecture 2nd generation of Philip (Philips Semiconductors) company with the physical hardware, SmartXA2) be example, SmartXA2 is called for short XA2, be one 16 microprocessor, be applicable to as Software Development Platform.
Fig. 4 is the structural drawing of virtual hardware system in the embodiment of the invention.As shown in Figure 4, be that virtual 8051 processors are example with virtual hardware, virtual hardware system of the present invention comprises: XA2 processor 401 and virtual 8051 processors 402.
Wherein, XA2 processor 401 comprises: main control unit 410, main with the location of instruction 411 and resource transfer unit 412; Main control unit 410 corresponding physical entities can be the electrically-erasable ROM (read-only memory) (E of physical hardware XA2
2PROM) any storage space in also can be any storage space in the random access memory (RAM); Main is the ROM (read-only memory) (ROM) of physical hardware XA2 with the location of instruction 411 corresponding physical entities; Resource transfer unit 412 corresponding physical entities are the E of physical hardware XA2
2The lower memory space of PROM.
Main control unit 410, be used to receive the instruction of the XA2 processor of independently using the location of instruction 411, reading command data from virtual 8051 processors 402, and, the director data that reads is converted into the instruction that XA2 processor 401 can be carried out according to the instruction set rule of virtual 8051 processors, 402 correspondences; According to the instruction after transforming, from virtual 8051 processors 402, read the corresponding computing variable of this instruction; When the instruction after transforming is the external call instruction, instruct according to external call, and call internal resource in the resource transfer unit 412 by system call interfaces, as power function, system call interfaces is the mapping relations table between various special instructions and the internal resource; The computing variable that utilization reads, operation is from the internal resource of resource transfer unit 412; The result that the operation internal resource is obtained sends to virtual 8051 processors 401.
Main be used for the instruction of storing X A2 processor 401, and when powering on, instruction offered main control unit 400 in system with the location of instruction 411.
Resource transfer unit 412 is used to store internal resource, and offers main control unit by system call interfaces.
Virtual 8051 processors 402 comprise fictitious order storage unit 421 and virtual data storage unit 422; Fictitious order storage unit 421 corresponding physical entities are the E of physical hardware XA2
2The higher memory space of PROM; Virtual data storage unit 422 corresponding physical entities are the higher memory space of the RAM of physical hardware XA2.
Fictitious order storage unit 421 is used for the director data of storing virtual 8051 processors 402, and director data is offered the main control unit 410 of XA2 processor 401;
Virtual data storage unit 422 is used for the corresponding computing variable of all instructions of storing virtual 8051 processors 402, and offers the main control unit 410 of XA2 processor 401; Reception is from the result of the main control unit 410 of XA2 processor 401.
In the practical application, main control unit 410 also is used for carrying out the ordinary instruction after transforming when the instruction after the conversion is ordinary instruction, and the result of ordinary instruction is sent to virtual 8051 processors 402.
XA2 processor 401 further comprises main with data storage cell 413, data space as XA2 processor 401, the corresponding physical entity is the lower memory space of the RAM of physical hardware XA2, be used for the corresponding computing variable of all instructions of storing X A2 processor 401, and offer main control unit 410.
In this case, main control unit 410 is further used for the corresponding computing intermediate value of each bar instruction is sent to main with data storage cell 413, and when next bar instruction of operation, according to this instruction from the master with reading the computing intermediate value the data storage cell 413.
The virtual hardware system of present embodiment is based on that XA2 realizes, system call interfaces is the mapping relations table between various special instructions and the internal resource; Resource transfer unit 412 and fictitious order storage unit 421 are respectively E among the XA2
2The lower memory space of PROM and higher memory space, the size in space can preestablish as required, also can be set to resource transfer unit 412 as fictitious order storage unit 421, higher memory space for virtual 8051 processors 402 the lower memory allocation of space; Main lower memory space and the higher memory space that is respectively RAM among the XA2 with data storage cell 413 and virtual data storage unit 422, the size in space can preestablish as required, and it is main with data storage cell 413 also to be set to the lower memory allocation of space can for virtual 8051 processors 402 as virtual data storage unit 422, higher memory space.
In the present embodiment, virtual hardware is virtual 8051 processors, with the storage space of RAM in the physical hardware as virtual data storage unit 422, when virtual hardware is the processor of other types, also can be with E
2The storage space of PROM receives the result from XA2 processor 401 as the data storage cell 422 of virtual hardware.
The virtual hardware system of present embodiment also can be based on other physical hardwares, and for example (Advanced RISC Machines ARM), realizes enhancement mode reduced instruction set computer single-chip microcomputer; Virtual hardware in the present embodiment also can be other processors such as AVR, can also be XA2 itself.
Below, the instruction executing method based on said system is elaborated.
Fig. 5 is based on the instruction executing method process flow diagram of virtual hardware system in the embodiment of the invention.As shown in Figure 5, the instruction executing method that the present invention is based on virtual hardware system may further comprise the steps:
Step 501 is virtual 8051 processor distribution resource spaces.
In the present embodiment, with E in the XA2 processor
2The higher memory allocation of space of PROM is given main control unit; With E
2The lower memory allocation of space of PROM is given virtual 8051 processors, as the fictitious order storage space of virtual 8051 processors; With E
2The residual memory space of PROM is distributed to the XA2 processor, as the resource transfer unit of XA2 processor; Give virtual 8051 processors with the higher memory allocation of space of RAM, as the data space of virtual 8051 processors; Give the XA2 processor with the lower memory allocation of space of RAM, as the data space of XA2 processor.
Step 502, the XA2 processor is the reading command data from virtual 8051 processors.
In the present embodiment, the XA2 processor is from E
2The higher memory space of PROM, be in the fictitious order storage space of virtual 8051 processors, read the command adapted thereto data of 8051 instruction set, the instruction set rule according to virtual 8051 processor correspondences is converted into the instruction that the XA2 processor can be carried out with the director data that reads; Simultaneously, from the data space of virtual 8051 processors, read the corresponding computing variable of this instruction.
In this step, store the mapping table of 8051 instruction set and XA2 instruction set in the XA2 processor, XA2 reads after 8051 instructions, searches inner mapping table, 8051 instructions can be converted into the XA2 instruction, also can transform by other modes.
Step 503, XA2 judges whether the instruction after transforming is the external call instruction, if then execution in step 504; If not, then execution in step 505.
In this step, the address of the pointed in the ordinary instruction is in the normal address scope of virtual 8051 processors, when the address of pointed is the special address of making an appointment, and there are mapping relations in this instruction and internal resource, judges that then this instruction is the external call instruction; Perhaps, when the order number that reads is the special instruction of A5, and there are mapping relations in this instruction and internal resource, judges that then this instruction is the external call instruction; Structure external call instruction also can be adopted other modes.
In the instruction set of virtual 8051 processors, the instruction of needs being carried out functional operation is set at above-mentioned special instruction, and stores the special instruction mapping table in the XA2 processor, can realize calling of power function.
For example, carry out the instruction of instruction for calling 2000H (16 system) address subroutine of sine function computing in virtual 8051 processors, and the normal address scope of virtual 8051 processors is 1400H, this instruction is special instruction.It is the special address of carrying out sinusoidal computing that XA2 and virtual 8051 processors can be arranged 2000H in advance, when virtual 8051 hardware are carried out the instruction of calling 2000H address subroutine, the address that the XA2 processor is judged earlier in this instruction does not belong in the normal range, search this address in the mapping table of storage internally again, after finding this address, according to the mapping relations of this address in mapping table, can judge the function that need call is sine function, and calls sine function.
In the prior art, the instruction of calling 2000H address subroutine is a disable instruction, carry out sine function and need call the subprogram segment of a hop count hundred even thousands of instructions, and thousands of instructions are converted to the instruction that father's hardware can be carried out one by one, arithmetic speed is obviously very slow; And among the present invention, the XA2 processor is judged the corresponding XA2 instruction of this instruction and is sine function according to the command mappings table of storage inside.
Step 504, according to the external call instruction after transforming, and by system call interfaces, the mapping relations between promptly various special instructions and the internal resource are called the internal resource of XA2 storage, as power function; According to the computing variable that reads, operation is from the internal resource of resource transfer unit, then result is sent to the virtual data storage space of virtual 8051 processors, and return step 502, the XA2 processor continues to read next bar director data of virtual 8051 processors.
In this step, because what carry out is the function of father's hardware XA2, do not need conversion, therefore speed is much higher than the speed that virtual hardware is carried out, also avoided simultaneously in the prior art must realizing the wasting of resources that two sections identical functions of logic cause in order on father's hardware and virtual hardware, to realize identical function, for virtual 8051 processors, execution in step 504 is not significantly distinguished with calling virtual 8051 processor built-in subroutines, influences the normal operation of virtual 8051 processors hardly; When the mapping result in the special instruction mapping table when calling senior resource, the XA2 processor then calls the upper strata resource in the computer system, for example file system or high-level functions storehouse.
Step 505 is carried out the ordinary instruction after transforming, and result is sent to the data space of virtual 8051 processors, and returns step 502, and the XA2 processor continues to read next bar instruction of virtual 8051 processors.
The implementation of this step can be same as the prior art, and the ordinary instruction after the conversion can be many XA2 instructions; When the instruction of the XA2 processor after the instruction according to virtual 8051 processors transforms is many, can be after carrying out each bar instruction, result is stored in the data space of XA2 processor, when carrying out next bar instruction, from the data space of XA2 processor, read the result of a last instruction again.
Resources allocation in the present embodiment also can be carried out according to other modes.
In the instruction executing method of present embodiment, also can be in the conversion process of step 502, judge the whether external call instruction of corresponding father's hardware of the director data read, determination methods is: earlier the director data that reads is transformed, if director data can transform according to the instruction rule of virtual hardware in the prior art, then conversion results is an ordinary instruction, and execution in step 505; If the director data that reads can't transform according to the instruction rule of virtual hardware in the prior art, then from external call command mappings table, search this director data, if find this director data, then the instruction that obtains according to mapping relations is the external call instruction, and execution in step 504, if do not comprise this director data in the mapping table, then father's hardware instruction of this director data correspondence is a disable instruction, and process ends.
In the present embodiment, the data space of virtual 8051 processors can be RAM, also can be the E that is assigned to
2The higher memory space of PROM.
Based on the instruction executing method of virtual hardware system, also be applicable to other in the present embodiment, for example based on the virtual hardware system of ARM based on other physical hardwares; Method in the present embodiment is applicable to that also virtual hardware is the virtual hardware system of other processors, for example AVR, XA2 etc.
The above is preferred embodiment of the present invention only, is not to be used to limit protection scope of the present invention.Within the spirit and principles in the present invention all, any modification of being done, be equal to and replace and improvement etc., all should be included within protection scope of the present invention.
Claims (18)
1. a virtual hardware system is characterized in that, comprising: father's hardware and virtual hardware, wherein,
Father's hardware, reading command data from virtual hardware, the treatment scheme of the director data correspondence that operation is read; Send result to virtual hardware;
Virtual hardware is used to store and director data that the instruction of making an appointment has mapping relations; Reception is from the result of described father's hardware.
2. the system as claimed in claim 1 is characterized in that, described father's hardware comprises: main control unit, main with the location of instruction and resource transfer unit, wherein,
Main control unit is used to receive the instruction of described father's hardware of independently using the location of instruction, and reading command data from virtual hardware are converted into the instruction that father's hardware can be carried out with the director data that reads; According to the instruction after transforming, from virtual hardware, read the corresponding computing variable of this instruction; When the instruction after transforming is the external call instruction, call internal resource in the resource transfer unit by system call interfaces, described system call interfaces is the mapping relations table between various special instructions and the internal resource; The computing variable that utilization reads moves the internal resource from the resource transfer unit, and the result that obtains is sent to virtual hardware;
Main use the location of instruction, be used to store the instruction of described father's hardware, and when powering on, instruction is offered main control unit in system;
The resource transfer unit is used to store internal resource, and offers main control unit by system call interfaces.
3. system as claimed in claim 2 is characterized in that described main control unit is further used for, and when the instruction after the described conversion is ordinary instruction, carries out ordinary instruction, and the result of ordinary instruction is sent to described virtual hardware.
4. system as claimed in claim 2 is characterized in that, described system further comprises: the master uses data storage cell, is used to store the corresponding computing variable of all instructions of father's hardware, and offers main control unit;
Main control unit is further used for the corresponding computing intermediate value of each bar instruction is sent to the main data storage cell of use, and when next bar instruction of operation, according to this instruction from the master with reading the computing intermediate value the data storage cell.
5. system as claimed in claim 4 is characterized in that, described main control unit is electrically-erasable ROM (read-only memory) E
2PROM or random access memory ram;
Described master is a read only memory ROM with the location of instruction;
Described master is RAM with data storage cell;
Described resource transfer unit is E
2PROM.
6. as any described system in the claim 2 to 5, it is characterized in that described virtual hardware comprises: fictitious order storage unit and virtual data storage unit, wherein,
The fictitious order storage unit is used to store the director data of described virtual hardware, and director data is offered described father's hardware;
The virtual data storage unit is used to receive the result from described father's hardware.
7. system as claimed in claim 6 is characterized in that, described fictitious order storage unit is E
2PROM;
Described virtual data storage unit is RAM.
8. the system as claimed in claim 1 is characterized in that, described father's hardware is the XA2 processor, and described virtual hardware is 8051 processors.
9. the instruction executing method based on virtual hardware is characterized in that, may further comprise the steps:
A, father's hardware read the director data in the virtual hardware, according to the mapping relations of the agreement instruction that sets in advance with father's hardware internal resource, call the internal resource of the director data correspondence that reads;
The internal resource that B, the utilization of father's hardware are called, the treatment scheme of the instruction correspondence after operation transforms returns to virtual hardware with result.
10. method as claimed in claim 9 is characterized in that, further comprises before the described steps A: give virtual hardware with the memory allocation of described father's hardware, as the instruction storage space and the data space of described virtual hardware;
The described director data that reads in the virtual hardware of steps A is: father's hardware is according to the instruction of storage inside, reading command data from the instruction storage space of virtual hardware.
11. as claim 9 or 10 described methods, it is characterized in that described steps A further comprises: father's hardware reads the computing variable of the described director data correspondence that reads from virtual hardware from the data space of virtual hardware.
12. method as claimed in claim 9 is characterized in that, the director data in the described conversion virtual hardware of steps A is: the instruction set rule according to the virtual hardware correspondence is converted into the instruction that father's hardware can be carried out with the director data that reads.
13. method as claimed in claim 9 is characterized in that, described agreement instruction is the external call instruction;
The described internal resource that calls of steps A is: judge whether the instruction after transforming is the external call instruction, if then according to the external call instruction after transforming, by described mapping relations, call the power function of father's hardware storage inside.
14. method as claimed in claim 13, it is characterized in that, whether the instruction after described judgement transforms is that the external call instruction is: whether the subroutine address of judging the instruction calls after transforming is in the normal range, if not, judge again whether described instruction exists mapping relations with father's hardware internal resource, if judge that then the instruction after the described conversion is the external call instruction.
15. method as claimed in claim 13, it is characterized in that, whether the instruction after described judgement transforms is that the external call instruction is: judge whether the instruction after transforming is specific coding, and whether described instruction exists mapping relations with father's hardware internal resource, if the instruction after the then described conversion is the external call instruction.
16. method as claimed in claim 13 is characterized in that, described steps A further comprises: the instruction after judging described conversion is not after the external call instruction, carries out the instruction after the described conversion, and result is returned to virtual hardware.
17. method as claimed in claim 11 is characterized in that, the treatment scheme of the instruction correspondence after the described operation of step B transforms is: according to the computing variable that reads, and the internal resource that operation is called.
18. method as claimed in claim 9 is characterized in that, step B is described to return to virtual hardware with result and is: the data space that result is sent to virtual hardware.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106775955A (en) * | 2017-01-12 | 2017-05-31 | 合肥杰美电子科技有限公司 | A kind of method and system of fictitious order calling system service |
| CN107103891A (en) * | 2017-01-20 | 2017-08-29 | 艾体威尔电子技术(北京)有限公司 | A kind of method that color/graphics is used in small internal memory embedded system |
| CN113297024A (en) * | 2020-02-21 | 2021-08-24 | 北京猎户星空科技有限公司 | Hardware management method, algorithm execution method, related device and robot |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1446718A2 (en) * | 2001-09-25 | 2004-08-18 | Koninklijke Philips Electronics N.V. | Software support for virtual machine interpreter (vmi) acceleration hardware |
| US20030192035A1 (en) * | 2002-04-09 | 2003-10-09 | Duesterwald Ald Evelyn | Systems and methods for implementing efficient execution transfers between successive translations of stack-based program code in a virtual machine environment |
| US20040193394A1 (en) * | 2003-03-24 | 2004-09-30 | Konstantin Levit-Gurevich | Method for CPU simulation using virtual machine extensions |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106775955A (en) * | 2017-01-12 | 2017-05-31 | 合肥杰美电子科技有限公司 | A kind of method and system of fictitious order calling system service |
| CN107103891A (en) * | 2017-01-20 | 2017-08-29 | 艾体威尔电子技术(北京)有限公司 | A kind of method that color/graphics is used in small internal memory embedded system |
| CN107103891B (en) * | 2017-01-20 | 2019-06-18 | 艾体威尔电子技术(北京)有限公司 | A method of using color/graphics in small memory embedded system |
| CN113297024A (en) * | 2020-02-21 | 2021-08-24 | 北京猎户星空科技有限公司 | Hardware management method, algorithm execution method, related device and robot |
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| CN100456229C (en) | 2009-01-28 |
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