CN101153891A

CN101153891A - Method for sync circuit implementing asynchronous matching and synchronous testing and its special test system

Info

Publication number: CN101153891A
Application number: CNA2006101165609A
Authority: CN
Inventors: 杜发魁; 王逸峰
Original assignee: Shanghai Hua Hong NEC Electronics Co Ltd
Current assignee: Shanghai Huahong Grace Semiconductor Manufacturing Corp
Priority date: 2006-09-27
Filing date: 2006-09-27
Publication date: 2008-04-02
Anticipated expiration: 2026-09-27
Also published as: CN100575974C

Abstract

The invention discloses a method for realizing synchronous measurement of synchronous circuit asynchronous match, wherein, a relay is adopted to connect a DUT pin with a tester channel; moreover, a DUT pin which needs to maintain up level or low level is connected with a power supply or the ground through a relay and a pull up resistor or a pull down resistor. Moreover, the invention also discloses a special test system for realizing the method. The invention extends separate test of product under the prior equipment conditions into synchronous measurement of multiple DUT pins, thereby making full of test resource and realizing maximum reduction in test time; moreover, the invention which increases test efficiency and furthest reduces test cost improves the competitive power of chips.

Description

The asynchronous coupling of realization synchronizing circuit is carried out with method and the special test system thereof surveyed

Technical field

The present invention relates to a kind of large scale integrated circuit parallel test method, relate in particular to a kind of asynchronous coupling of synchronizing circuit that realizes and carry out with the method for surveying; In addition, the invention still further relates to the special test system of realizing said method.

Background technology

When existing large test instrument carried out with survey, it was duplicate that the same pin (Pin) of all DUT (Device Under Test, detected element) is gone up the excitation of giving from Tester Channel (tester passage) end, as shown in Figure 1.

When synchronizing circuit carries out the electrification reset coupling with survey, the waveform position that coupling occurs is at random, the match is successful and only be only at certain appearance expection of fixing cycle waveform, as shown in Figure 2, have only Output (output) the 6th cycle behind Pin 1 rising edge waveform to occur and calculate just that the match is successful, and the position that this waveform occurs is at random, and is unfixed.As shown in Figure 3, Output waveform occurs the 6th cycle, even the expection waveform occurs, but not in the position of expection, also is that it fails to match.

Therefore, under present appointed condition, the DUT that matches can't be hung other DUT that do not match of wait and continue coupling, proceed to mate the circuit state that has just destroyed the DUT that has matched, so testing and singly to survey under the condition at present.

Summary of the invention

The technical problem to be solved in the present invention provides a kind of asynchronous coupling of synchronizing circuit that realizes and carries out with the method for surveying, this method has expanded to many DUT with surveying with the product that can only singly survey under the existing equipment condition, reduce the test duration to the full extent, improved testing efficiency.For this reason, the present invention also provides the special test system of realizing said method.

For solving the problems of the technologies described above, the invention provides a kind of asynchronous coupling of synchronizing circuit that realizes carries out with the method for surveying, adopt relay that the DUT pin is connected with the tester passage, adopt relay and pull-up resistor or pull down resistor will need to keep high level or low level DUT pin to link to each other with power supply or ground, the testing procedure of this method is as follows: step 1, the relay of closed all DUT pins carries out matching test; Step 2 is judged matching result, to the DUT that the match is successful, disconnects the relay that is connected on the tester passage, but the relay that is connected on pull-up resistor or the pull down resistor still remains closed, and it is constant to keep its high level or low level; The DUT that it fails to match is proceeded coupling, repeat above step; Step 3, when reaching the matching times of setting, coupling finishes, and the relay on all DUT pins that the match is successful is closed again, carries out ensuing test event, realizes that the DUT that it fails to match directly abandons with surveying.

When carrying out dc parameter test, all relays that link to each other with pull-up resistor or pull down resistor are disconnected, the relay closes that links to each other with the tester passage is to satisfy test request.

The present invention also provides a kind of special test system of realizing the asynchronous coupling simultaneous test method of above-mentioned synchronizing circuit, comprise by tester, the hardware testing system that probe station and probe constitute, and by operating system, the software testing system that special test program and special test vector constitute, this software testing system runs in the hardware testing system, described probe is provided with relay and pull-up resistor or pull down resistor, connect by relay between the passage of described tester and the DUT pin, need to keep between high level or low level DUT pin and power supply or the ground to be connected by relay and pull-up resistor or pull down resistor.

Compare with prior art, the present invention has following beneficial effect: this transformation peripheral circuit provided by the invention, adopt the method for designing of may command Relay (relay), test the time played will the match is successful the effect that makes a distinction of DUT and the DUT that the match is successful as yet, and the general DUT that the match is successful need keep the pin of high (low) level to draw the control of resistance to remain on height (low) level by Relay and last (descending), passage with pin and tester disconnects simultaneously, by such method, can make the DUT that the match is successful as yet proceed coupling, and can not influence the circuit state of the DUT that the match is successful.Use the inventive method can not exert an influence,, when the DC test needs to disconnect these Relay, can disconnect easily because these Relay all can freely control closed and disconnected to other DC (direct current) test event.In addition, the present invention has expanded to the individual DUT of n (n＞=2) with surveying with carrying out single product of surveying under the existing equipment condition, and for example 64 when surveying, and testing efficiency has been improved 64 times, produced considerable economic.

Description of drawings

Fig. 1 is that existing tester carries out when surveying, and the tester passage is exported to the synoptic diagram of DUT pin excitation;

Fig. 2 is that existing tester carries out when surveying the synoptic diagram that the match is successful;

Fig. 3 is that existing tester carries out when surveying the synoptic diagram that it fails to match;

Fig. 4 is the synoptic diagram that adds relay between tester passage of the present invention and the DUT pin;

Fig. 5 is the synoptic diagram that adds relay and pull-up resistor between DUT pin of the present invention and the power supply;

Fig. 6 is the special test system that the present invention realizes the asynchronous coupling simultaneous test method of synchronizing circuit.

Embodiment

The present invention is further detailed explanation below in conjunction with drawings and Examples.

In order to solve the technical matters of large scale integrated circuit at the asynchronous coupling concurrent testing of the enterprising horizontal-synchronizing circuit of large test instrument, a kind of method for designing of transforming peripheral circuit provided by the invention, by can use the investigation and the analysis of resource to tester table, channel C hannel at tester has increased may command relay R ELAYn1 between the DUT pin DUTy, promptly may command relay (as shown in Figure 4) go up to be installed, and have been increased the may command relay R ELAYm2 and the pull-up resistor R2 (as shown in Figure 5) of resistance necessarily between the DUT pin DUTy that keeps high level at needs and the power vd D in probe (Prober Card).Certainly, keep the DUT pin to maintain low level herein if desired, then should DUT pin and GND () between increase the pull down resistor of may command Relay and certain resistance.

Adopt method of the present invention that the multicore sheet is carried out the volume production concurrent testing, can adopt test macro as shown in Figure 6, this test macro comprises the hardware testing system 1 that is made of hardware such as tester, probe station and probe, and will be tested by software testing system 2 these hardware testing systems 1 of input that operating system, special test program and special test vector etc. constitute.Tested object is the volume production chip; The mode that the number of concurrent testing can be supported by tester determines that the single measuring head 2～32 of the inventive method support is with surveying, and two measuring heads 2～64 are with surveying.

The inventive method has adopted the method for drawing resistance to be installed on the probe may command Relay and last (descending) to realize, on every card the Relay that many DUT need is installed altogether.During concrete enforcement, at first in program, control all may command Relay closures, next carries out matching test, and the result of judgement coupling, and the may command Relay that DUT that will the match is successful is connected on the tester passage disconnects, and draws Relay continuation closure that resistance links to each other to satisfy test request with last (descend); Then the DUT that the match is successful is as yet proceeded coupling, and judge more than continuing and operation, when reaching the matching times of setting (such as 10 times, different product has different requirements to matching times), result to all DUT couplings carries out an overall judgement, as long as once the match is successful promptly is that the match is successful, the DUT that the match is successful is with the test of the closed continuation of Relay subsequent project in the middle of 10 couplings, and 10 couplings all the DUT of failure will be judged as that it fails to match, directly abandon.

When carrying out the DC parameter testing, with all and the Relay disconnection that last (descending) draws resistance to link to each other, the Relay closure that links to each other with the tester passage is to satisfy test request.

Claims

1. realize that the asynchronous coupling of synchronizing circuit carries out with the method for surveying for one kind, it is characterized in that, adopt relay that the DUT pin is connected with the tester passage, adopt relay and pull-up resistor or pull down resistor will need to keep high level or low level DUT pin to link to each other with power supply or ground, the testing procedure of this method is as follows: step 1, the relay of closed all DUT pins carries out matching test; Step 2 is judged matching result, to the DUT that the match is successful, disconnects the relay that is connected on the tester passage, but the relay that is connected on pull-up resistor or the pull down resistor still remains closed, and it is constant to keep its high level or low level; The DUT that it fails to match is proceeded coupling, repeat above step; Step 3, when reaching the matching times of setting, coupling finishes, and the relay on all DUT pins that the match is successful is closed again, carries out ensuing test event, realizes that the DUT that it fails to match directly abandons with surveying.

2. the asynchronous coupling of realization synchronizing circuit as claimed in claim 1 is carried out with the method for surveying, it is characterized in that, when carrying out dc parameter test, all relays that link to each other with pull-up resistor or pull down resistor are disconnected, the relay closes that links to each other with the tester passage is to satisfy test request.

3. special test system of realizing the asynchronous coupling simultaneous test method of synchronizing circuit, comprise by tester, the hardware testing system that probe station and probe constitute, and by operating system, the software testing system that special test program and special test vector constitute, this software testing system runs in the hardware testing system, it is characterized in that, described probe is provided with relay and pull-up resistor or pull down resistor, connect by relay between the passage of described tester and the DUT pin, need to keep between high level or low level DUT pin and power supply or the ground to be connected by relay and pull-up resistor or pull down resistor.