CN101149725B - Serial bus data transmission method and device - Google Patents
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- CN101149725B CN101149725B CN200710165943XA CN200710165943A CN101149725B CN 101149725 B CN101149725 B CN 101149725B CN 200710165943X A CN200710165943X A CN 200710165943XA CN 200710165943 A CN200710165943 A CN 200710165943A CN 101149725 B CN101149725 B CN 101149725B
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Abstract
The invention discloses a kind of method and device about transferring data of serial bus, the method about this invention includes: sending commands about frame head and data transmission from main transceiver to subordinate transceiver; accepting feedback commands about frame head and data transmission from subordinate transceiver to main transceiver, transferring data between main transceivers at the same time and accepting frame tail from main transceiver; accepting feedback frame tail from subordinate transceiver to main transceiver. In the method and device of the invention, when transferring data between main transceiver and subordinate transceiver, the main transceiver and subordinate transceiver which accept data will both feedback the data, then it assures normal work about data path. It is simple to realize the method and device in this invention about transferring data of serial bus, it is serial to transfer data, and it is easy to be extended and used in computer system.
Description
Technical field
The present invention relates to field of computer technology, be meant a kind of method and apparatus of universal serial bus data transmission especially.
Background technology
Along with development of computer, in every field such as Industry Control, generation, life, vehicle robotization controls bigger application is arranged all, particularly in vehicle robotization control, application more extensive.
In vehicle robotization control, can adopt multi-purpose computer highly reliable or that fail-safe calculates usually, this computing machine generally adopts redundant system architecture to realize.Between Central Processing Board and peripheral hardware plate, the redundant bus of highly reliable or fail-safe need be set, traditional parallel bus uses pin too much, carries out very difficulty of Redundancy Design, and the control protocol complexity.
In addition, because the multi-purpose computer employing of highly reliable or fail-safe calculating is not Peer to Peer Architecture, when expanding the peripheral hardware plate, can be subjected to the restriction of bus performance.Peripheral hardware plate of every increase, the performance of each peripheral hardware plate will descend thereupon, and Electro Magnetic Compatibility is poor.Because data line is two-way, is difficult to realize electrical isolation.
Though traditional serial core bus also can be realized data transmission, be partial to the higher telecommunications of performance more and use, and and be not suitable for highly reliable or the fail-safe computer application; And existing redundant bus highly reliable or fail-safe adopts parallel bus, and pin is more, realizes complicated.
Summary of the invention
In view of this, the invention reside in the method and apparatus that a kind of universal serial bus data transmission is provided, data transmission adopts parallel bus, baroque problem in the above-mentioned highly reliable or fail-safe computing machine to solve.
For addressing the above problem, the invention provides a kind of method of universal serial bus data transmission, comprising:
Main transceiver is to the order that sends frame head, data transmission from transceiver;
To the received frame head of main transceiver feedback, the order of data transmission, carry out data transmission and reception postamble from transceiver between while and the described main transceiver from main transceiver;
Feed back received postamble from transceiver to main transceiver.
Preferably, comprising: the order of described data transmission is the order that main transceiver sends data;
From transceiver to the received frame head of main transceiver feedback, the order of data transmission, simultaneously and carry out data transmission between the described main transceiver and the postamble process that receives from main transceiver comprises:
A1, from transceiver to the received frame head of main transceiver feedback;
A2, main transceiver feed back the order that the described main transceiver that receives sends data from transceiver after sending first byte of data from transceiver;
A3, main transceiver to last byte, feed back received byte from transceiver to second byte that sends data from transceiver;
A4, main transceiver are to sending postamble from transceiver.
Preferably, comprising: the order of described data transmission is the order that main transceiver receives data;
From transceiver to the received frame head of main transceiver feedback, the order of data transmission, simultaneously and carry out data transmission between the described main transceiver and the postamble process that receives from main transceiver comprises:
B1, from transceiver behind the received frame head of main transceiver feedback, feed back the order that described main transceiver receives data;
B2, from transceiver to sending out all bytes that device sends data from main, and receive the received byte of main transceiver feedback;
B3, main transceiver are to sending postamble from transceiver.
Preferably, in the described data transmission procedure, bits per inch is got 2 identical pulses as this bit data according to being 3 pulses.
Preferably, described main transceiver/from transceiver is that active and standby double transceiver is worked simultaneously;
This method further comprises comparer, when described active and standby transceiver sends data, compares, and when comparative result is inconsistent, transmission again; Or after the described active and standby transceiver reception data, compare, when comparative result is inconsistent, transmission again.
The present invention also provides a kind of device of universal serial bus data transmission, comprising: main transceiver and from transceiver;
Described main transceiver comprises: first serial encoder, the first serial decode device, first controller;
Described first serial encoder is used under the control of described first controller, sends frame head, the order of data transmission, data, postamble to described from transceiver;
The described first serial decode device is used under the control of described first controller, receives the described data that send from transceiver; Or receive described from received frame head, data transfer command, data, the postamble of transceiver feedback;
Described first controller, be used to control described first serial encoder to described send the order of frame head, data transmission from transceiver after, control the described first serial decode device or first serial encoder and described, control the described first serial decode device and receive next postamble since transceiver from carrying out data transmission between the transceiver;
Describedly comprise: second serial encoder, the second serial decode device, second controller from transceiver;
Described second serial encoder is used under the control of described second controller, to received frame head, the order of data transmission, data, the postamble of described main transceiver feedback; Or to described main transceiver transmission data;
The described second serial decode device is used under the control of described second controller, receives frame head, the order of data transmission, data, postamble that described main transceiver sends;
Described second controller, be used to control described second serial encoder after the order of the received frame head of described main transceiver feedback, data transmission, control between the described second serial decode device or second serial encoder and the described main transceiver and carry out data transmission, second serial encoder is to the received postamble of described main transceiver feedback under the control.
Preferably, described main transceiver comprises active and standby two first serial encoders/first serial decode device, and redundancy of effort each other simultaneously; Describedly comprise active and standby two second serial encoders/second serial decode device from transceiver, and redundancy of effort each other simultaneously.
Preferably, described main transceiver/further comprise comparer from transceiver is used for comparing when described active and standby first serial encoder/second serial encoder sends data, when comparative result is inconsistent, and transmission again; Or after the described active and standby first serial decode device/second serial decode device reception data, compare, when comparative result is inconsistent, transmission again.
Preferably, when described first serial encoder/second serial encoder sent data, the bits per inch certificate was 3 pulses; When the described first serial decode device/second serial decode device receives data, in 3 received pulses, get 2 identical pulses as this bit data.
Method and apparatus of the present invention, when carrying out data transmission at main transceiver with between transceiver, receive the main transceiver of data/all received data can be fed back from transceiver, thereby guarantee the operate as normal of the path of data, and when transmission/reception data, all adopt active and standby redundancy of effort, and when transmission/reception data, carry out primary, spare comparison, and when inconsistent, transmission again.The method of serial data transmission of the present invention, device are realized simple, data transmission security, and in computer system, promote easily, use.
Description of drawings
Fig. 1 is the process flow diagram of the embodiment of the invention one;
Fig. 2 is the process flow diagram of the embodiment of the invention two;
Fig. 3 is the process flow diagram of the embodiment of the invention three;
Fig. 4 is the synoptic diagram of data bit in the embodiment of the invention;
Fig. 5 is the structure drawing of device of the embodiment of the invention five.
Embodiment
For clearly demonstrating method and apparatus of the present invention, provide the preferred embodiments of the present invention below and be described with reference to the accompanying drawings.
At first describe embodiment one in detail, embodiment one is method embodiment of the present invention.Referring to Fig. 1, Fig. 1 is the process flow diagram of the embodiment of the invention one, comprising:
Step 101: main transceiver is to the order that sends frame head, data transmission from transceiver;
Step 102: to the received frame head of main transceiver feedback, the order of data transmission, carry out data transmission and reception postamble between while and the described main transceiver from main transceiver from transceiver;
Step 103: feed back received postamble to main transceiver from transceiver.
In the process of above-mentioned data transmission, no matter be that main transceiver sends data/reception data, the initiation of data transmission is all controlled by main transceiver.In data transmission procedure, after no matter main transceiver/from transceiver receives data, all can be with received data feedback.
Describe in detail by embodiment two, embodiment three respectively below.Embodiment two is that main transceiver is to the embodiment that sends data from transceiver.Main transceiver is to from transceiver sends data procedures, and the data content of each byte can be referring to table 1,
| Byte | Byte feedback direction | Main transceiver sends | Send from transceiver |
| 1 | There is not feedback | Frame head | Idle |
| 2 | Up | The downlink transfer command word | Frame head |
| 3 | Up | The 1st byte of downlink data | The downlink transfer command word |
| 4～2+ data length | Up | The 2nd of downlink data arrives last 1 byte | Downlink data the 1st byte is to preceding 1 byte of last 1 byte |
| 2+ data length～3+ data length | Up | Postamble | Last 1 byte of downlink data |
| 3+ data length～4+ data length | Up | Idle | Postamble |
Table 1
Wherein, the scope of data in the byte representation byte in the table 1, last line display is from the sending direction of transceiver to main transceiver.
Main transceiver can comprise referring to Fig. 2 to the process that sends data from transceiver:
Step 201: main transceiver is to sending frame head from transceiver;
Step 202: main transceiver is to sending the downlink transfer command word from transceiver, and the downlink transfer command word is represented main transceiver to sending data from transceiver, simultaneously from the received frame head of transceiver feedback;
Step 203: main transceiver is in the time of the 1st byte from transceiver transmission data, from the received downlink transfer command word of transceiver feedback;
Step 204: main transceiver is to the 2nd byte that sends data from transceiver to the end byte the time, from received the 1st byte of transceiver feedback preceding 1 byte of byte to the end;
Step 205: main transceiver is to sending postamble from transceiver, feeds back last 1 byte the received data from transceiver;
Step 206: feed back postamble to main transceiver from transceiver.
Top embodiment two describes main transceiver in detail to the process that sends data from transceiver, for describing by the following examples three to the process that main transceiver sends data from transceiver.
Embodiment three is the embodiment that sends data from transceiver to main transceiver.To main transceiver sent data procedures, the data content of each byte can be referring to table 2 from transceiver,
| Byte | Byte feedback direction | Main transceiver sends | Send from transceiver |
| 1 | There is not feedback | Frame head | Idle |
| 2 | Up | The uplink transmission order word | Frame head |
| 3 | Up | Idle | The uplink transmission order word |
| 4 | There is not feedback | Idle | Upstream data the 1st byte |
| 5～3+ data length | Descending | Upstream data the 1st byte is to preceding 1 byte of last 1 byte | Upstream data the 2nd is to last 1 byte |
| 3+ data length～4+ data length | Descending | Last 1 byte of upstream data | Idle |
| 4+ data length～5+ data length | There is not feedback | Postamble | Idle |
| 5+ data length～6+ data length | Up | Idle | Postamble |
Table 2
Wherein, the scope of data in the byte representation byte in the table 2, last line display is from the sending direction of transceiver to main transceiver.
Can comprise referring to Fig. 3 to the process that main transceiver sends data from transceiver:
Step 301: main transceiver is to sending frame head from transceiver;
Step 302: main transceiver is to sending the uplink transmission order word from transceiver, and the uplink transmission order word table shows that main transceiver receives the data that send from transceiver, simultaneously from the received frame head of transceiver feedback;
Step 303: feed back received uplink transmission order word to main transceiver from transceiver;
Step 304: from 1st byte of transceiver to main transceiver transmission data;
Step 305: the 2nd byte that sends data to main transceiver from transceiver is to the end byte the time, and received the 1st byte of main transceiver feedback is preceding 1 byte of byte to the end;
Step 306: main transceiver is to last 1 byte from the transceiver feedback data;
Step 307: main transceiver feeds back postamble from transceiver to main transceiver to sending postamble from transceiver.
Top embodiment three describes main transceiver in detail and receives the process that sends data from transceiver.
In the above among three embodiment, main transceiver/also can adopt active and standby double transceiver to work simultaneously from transceiver, promptly adopt two main transceivers, two from transceiver, it is one main one setting fully, and adding comparer, if relatively more two main transceivers/whether consistent from data that transceiver received inconsistent, then transmit data again; If relatively more two main transceivers/whether consistent from data that transceiver sent inconsistent, then transmit data again.
Among superincumbent three embodiment, the transmission of bits per inch certificate can be referring to Fig. 4, and wherein, B0, B1, B2 or B3 represent 1 bit data.In the data transmission procedure, the transmission of any one byte is initiated by main transceiver and is provided time clock synchronous, per 1 data bit is in last 1 time clock negative edge saltus step of a last data bit, the output before clock begins to drive of the 1st data bit, three rising edge clocks (t2, t3 of each data bit, t4) locate, main transceiver is sampled to upstream data, from transceiver downlink data is sampled, and 2 identical pulses of sampling are as the logical value of this bit data position from 3 pulses.Every byte is transmitted with 10 data bit, and wherein least-significant byte is valid data, and high 2 is control bit.High 2 is to represent that this byte was data at 00 o'clock; High 2 is 01,10,11 o'clock, in conjunction with least-significant byte, can be combined into 768 kinds of control commands and status information.For example, the order implication that is combined into is as shown in table 3,
| The sign abbreviation | Title | Implication | Numerical value (16 system) |
| SNP： | Start?of?New?Packet | Frame head | 155 |
| SOP： | Start?of?Old?Packet | Retransmit | 168 |
| MTS： | Master?To?Slave | Main end is to sending data from end | 15f |
| MFS： | Master | Main end is from receiving data from termination | 1f2 |
| EGP： | End | End-of-packet is correct | 2f2 |
| EBP： | End | End-of-packet, |
206 |
| IDLE1： | Idle state 1 | 10f | |
| IDLE2： | Idle state 2 | 10c | |
| NULL： | Empty | 3ff |
Table 3
Wherein, in three above-mentioned embodiment, whenever receive the IDLE1 that main transceiver is sent from transceiver, all should return IDLE2 in next byte, follow-up transmitting step is postponed.If main transceiver 1 byte after sending IDLE1 is received IDLE2, illustrate that then current circuit is normal, noiseless.Otherwise line out of service, circuit interference or one or more situations from transceiver lost efficacy might take place.
Describe each embodiment of the inventive method above in detail, the device for realizing the inventive method can have multiple way of realization, provides preferred device embodiment below.Referring to Fig. 5, comprising: main transceiver and from transceiver, main transceiver is installed on the Central Processing Board, is installed on the peripheral hardware plate from transceiver.
Described main transceiver comprises: the first serial encoder A1, the first serial decode device A1, first controller;
The described first serial encoder A1 is used under the control of described first controller, sends frame head, the order of data transmission, data, postamble to described from transceiver;
The described first serial decode device A1 is used under the control of described first controller, receives the described data that send from transceiver; Or receive described from received frame head, data transfer command, data, the postamble of transceiver feedback;
Described first controller, be used to control the described first serial encoder A1 to described send the order of frame head, data transmission from transceiver after, control the described first serial decode device A1 or the first serial encoder A1 and described, control the described first serial decode device A1 and receive next postamble since transceiver from carrying out data transmission between the transceiver;
Described first controller also is connected with central cpu by buffer memory (FIFO-A).
Describedly comprise: the second serial encoder B1, the second serial decode device B1, second controller from transceiver;
The described second serial encoder B1 is used under the control of described second controller, to received frame head, the order of data transmission, data, the postamble of described main transceiver feedback; Or to described main transceiver transmission data;
The described second serial decode device B1 is used under the control of described second controller, receives frame head, the order of data transmission, data, postamble that described main transceiver sends;
Described second controller, be used to control the described second serial encoder B1 after the order of the received frame head of described main transceiver feedback, data transmission, control between the described second serial decode device B1 or the second serial encoder B1 and the described main transceiver and carry out data transmission, second serial encoder is to the received postamble of described main transceiver feedback under the control.
Described second controller also is connected with peripheral hardware CPU by buffer memory (FIFO-B).
Preferably, described main transceiver/from transceiver is an active and standby double transceiver redundancy of effort each other simultaneously, as shown in Figure 5, have also in the main transceiver that the first serial decode device A2, the first serial encoder A2 also can realize and from carrying out data transmission between the transceiver, thereby constitute primary, spare relation, and redundancy of effort each other with the first serial decode device A1, the first serial encoder A1.Adopting the second serial encoder B1, the second serial encoder B1 and the second serial decode device B2, the second serial decode device B2 from transceiver is primary, spare relation, and redundancy of effort each other.
Between active and standby transceiver, further comprise comparer A, be used for when the first serial encoder A1/A2 of described active and standby transceiver sends data or the first serial decode device A1/A2 when receiving data, compare, when comparative result is inconsistent, transmission again; Further comprise comparer B, be used for when the first serial encoder B1/B2 of described active and standby transceiver sends data or the first serial decode device B1/B2 when receiving data, compare, when comparative result is inconsistent, transmission again.
Preferably, when the described first serial encoder A1/A2 or the second serial encoder A1/A2 sent data, the bits per inch certificate was 3 pulses; When the described first serial decode device B1/B2 or the second serial decode device B1/B2 receive data, in 3 received pulses, get 2 identical pulses as this bit data.
In the said apparatus course of work, the clock source 1 on the Central Processing Board, clock source 2 are used for providing clock on the peripheral hardware plate.
Describe the preferred embodiment of apparatus of the present invention above in detail, the method for data transmission all can realize by the device among the embodiment among the present invention.For the method and apparatus of being set forth among each embodiment of the present invention, within the spirit and principles in the present invention all, any modification of being done, be equal to replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (6)
1. the method for a universal serial bus data transmission is characterized in that, comprising:
Main transceiver by serial data bus to the order that sends frame head, data transmission from transceiver;
Feed back received frame head, the order of data transmission by serial data bus to main transceiver from transceiver, carry out data transmission and reception postamble between while and the described main transceiver from main transceiver;
Feed back received postamble by serial data bus to main transceiver from transceiver;
Described main transceiver and all comprise active and standby double transceiver from transceiver and work simultaneously;
When described active and standby transceiver sends data, compare, when comparative result is inconsistent, transmission again; Or after the described active and standby transceiver reception data, compare, when comparative result is inconsistent, transmission again.
2. method according to claim 1 is characterized in that, comprising: the order of described data transmission is the order that main transceiver sends data;
From transceiver to the received frame head of main transceiver feedback, the order of data transmission, simultaneously and carry out data transmission between the described main transceiver and the postamble process that receives from main transceiver comprises:
A1, from transceiver to the received frame head of main transceiver feedback;
A2, main transceiver feed back the order that the described main transceiver that receives sends data from transceiver after sending first byte of data from transceiver;
A3, main transceiver to last byte, feed back received byte from transceiver to second byte that sends data from transceiver;
A4, main transceiver are to sending postamble from transceiver.
3. method according to claim 1 is characterized in that, comprising: the order of described data transmission is the order that main transceiver receives data;
From transceiver to the received frame head of main transceiver feedback, the order of data transmission, simultaneously and carry out data transmission between the described main transceiver and the postamble process that receives from main transceiver comprises:
B1, from transceiver behind the received frame head of main transceiver feedback, feed back the order that described main transceiver receives data;
B2, from transceiver to sending out all bytes that device sends data from main, and receive the received byte of main transceiver feedback;
B3, main transceiver are to sending postamble from transceiver.
4. method according to claim 1 is characterized in that, in the described data transmission procedure, bits per inch is got 2 identical pulses as this bit data according to being 3 pulses.
5. the device of a universal serial bus data transmission is characterized in that, comprising: main transceiver and from transceiver;
Described main transceiver, be positioned at the two ends of serial data bus from transceiver, by the serial data bus Data transmission;
Described main transceiver comprises: first serial encoder, the first serial decode device, first controller;
Described first serial encoder is used under the control of described first controller, sends frame head, the order of data transmission, data, postamble to described from transceiver;
The described first serial decode device is used under the control of described first controller, receives the described data that send from transceiver; Or receive described from received frame head, data transfer command, data, the postamble of transceiver feedback;
Described first controller, be used to control described first serial encoder to described send the order of frame head, data transmission from transceiver after, control the described first serial decode device or first serial encoder and described, control the described first serial decode device and receive next postamble since transceiver from carrying out data transmission between the transceiver;
Describedly comprise: second serial encoder, the second serial decode device, second controller from transceiver;
Described second serial encoder is used under the control of described second controller, to received frame head, the order of data transmission, data, the postamble of described main transceiver feedback; Or to described main transceiver transmission data;
The described second serial decode device is used under the control of described second controller, receives frame head, the order of data transmission, data, postamble that described main transceiver sends;
Described second controller, be used to control described second serial encoder after the order of the received frame head of described main transceiver feedback, data transmission, control between the described second serial decode device or second serial encoder and the described main transceiver and carry out data transmission, control described second serial encoder to the received postamble of described main transceiver feedback;
Described main transceiver comprises active and standby two first serial encoders and active and standby two first serial decode devices, and redundancy of effort each other simultaneously; Describedly comprise active and standby two second serial encoders and active and standby two second serial decode devices from transceiver, and redundancy of effort each other simultaneously;
Described main transceiver/further comprise comparer from transceiver is used for comparing when described active and standby first serial encoder/second serial encoder sends data, when comparative result is inconsistent, and transmission again; Or after the described active and standby first serial decode device/second serial decode device reception data, compare, when comparative result is inconsistent, transmission again.
6. device according to claim 5 is characterized in that, when described first serial encoder/second serial encoder sent data, the bits per inch certificate was 3 pulses; When the described first serial decode device/second serial decode device receives data, in 3 received pulses, get 2 identical pulses as this bit data.
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