CN101140872A - Metallic silicide forming method - Google Patents
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- CN101140872A CN101140872A CNA2006100308107A CN200610030810A CN101140872A CN 101140872 A CN101140872 A CN 101140872A CN A2006100308107 A CNA2006100308107 A CN A2006100308107A CN 200610030810 A CN200610030810 A CN 200610030810A CN 101140872 A CN101140872 A CN 101140872A
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Abstract
A forming method of the metal silicide is disclosed, which comprises steps as follows: providing the underlay with silicide material, forming a metal layer on the said underlay; forming a barrier layer on the said metal layer; forming an active layer on the said barrier layer; heat-processing the said underlay; rusting and eliminating the said metal layer in reaction with the said silicide material. The forming method provided in the invention can efficiently improve the forming quality of the metal silicide, decrease drain current of the device and improve the device performance.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, the formation method of metal silicide in particularly a kind of semiconductor device.
Background technology
Along with developing rapidly of very lagre scale integrated circuit (VLSIC) (ULSI), the integrated level of device is more and more higher, and size is more and more littler.When device dimensions shrink during, can correspondingly produce many problems, as the corresponding increase of device resistance value to time micron dimension.In order to overcome this type of problem, introduced the process of a kind of self aligned metal silicide (Salicide), this metal silicide is a kind of metallic compound with thermal stability, has lower resistivity, each electrode at device, form this metal silicide as source, leakage and grid place or electrical connection place, can significantly reduce the film resistor and the contact resistance of electrical connection place.At present, the technology of metal silicide is produced in the silicon chip manufacturing industry and has occupied consequence, and its research has also been become one of key issue in the field of semiconductor manufacture.
So-called metal silicide technology, be by depositing a kind of can closing with silication, but can not with other materials, the metal that reacts as silica, silicon nitride or silicon oxynitride, as cobalt (Co), nickel (Ni) or titanium (Ti) etc., by heat treatment this metal level and silicon are fully reacted again, generate the CoSi of low-resistivity
2, NiSi or TiSi
2Deng silicide, to improve the technology of device electrical performance.
With the MOS transistor is example, the forming process of the existing self-aligned metal silicate of simple declaration.Figure 1A to 1D is the formation method schematic diagram of existing self aligned metal silicide.Wherein, Figure 1A is the device profile schematic diagram after formation source/drain doping region.Shown in Figure 1A, on silicon substrate 101, deposited pad silicon oxide layer 103 (Pad Oxide), and substrate has been carried out etching fill, between each device, form isolated groove 102; Deposit spathic silicon then, etching forms grid 104; Then on each gate lateral wall, formed gate lateral wall layer 105, realized good protection polysilicon gate.Next, be mask with grid structure and side wall layer, in mode formation source/ drain doping region 107 and 108 between grid of injecting with ion on the substrate.
Figure 1B is the device architecture schematic diagram behind the depositing metal layers.Shown in Figure 1B, form silicide, need usually earlier refractory metal 110 to be deposited on the silicon chip, as cobalt (Co), nickel (Ni) or titanium (Ti) etc.
In order to form metal silicide, need carry out The high temperature anneal.Fig. 1 C is the device architecture schematic diagram after the heat treatment.Shown in Fig. 1 C, after the annealing, be the zone of silicon materials on the surface, metal and pasc reaction form the silicide 120 of low-resistivity, as CoSi
2, NiSi or TiSi
2Deng, not silicon materials on the surface, be the gate lateral wall layer of silica as the surface, metal can not react, and does not form silicide.
Fig. 1 D is the device architecture schematic diagram behind the wet etching.Shown in Fig. 1 D, remove the metal level 110 that does not react by the method for selective wet etching, only stay metal silicide 120, so just formed self aligned metal suicide structure.
The technology that integrated level is different, it is different that the formation of metal silicide is required, and in the practical application, at first will select different metal silicides according to the technological requirement of device.For greater than 0.25 micron technology, adopt the TiSi that forms by metal Ti that early occurs usually
2, but it is bigger because of particle, required annealing temperature higher (about 800 ℃), for the technology below 0.18 micron, still on resistance characteristic, all can not meet the demands in live width, thereby for the device below 0.18 micron, the CoSi that particle size is less
2Substituted TiSi gradually as new metal silicide
2The status, yet when technological development after 65nm, it is more and more littler that size of devices becomes, more and more higher to the requirement of shallow junction, the application of metallic cobalt has at this moment also run into new problem, on the one hand its consumption to silicon is bigger, has reduced dynamic area useful in the shallow junction; Its required annealing temperature higher (about 700 ℃) on the other hand, heat budget is still bigger, and these all are unacceptable for the MOS technology of advanced person's 65 nanometers.So, for the technology of 65nm, normally replacing cobalt by metallic nickel now becomes the optimal selection that forms metal silicide, and the silicon consumption of the silicide NiSi of its formation low-resistance is lower, and only about 350 ℃, heat budget can obviously reduce the required annealing temperature of formation NiSi.
Except that the selection of material, in the forming process of metal silicide, be also noted that the influence of silicon surface oxidation layer, if having oxide layer, can make that the formation of metal silicide is second-rate at silicon face, cause device resistance to raise, leakage current strengthens.Yet, in the manufacture process of chip, silicon chip can be exposed in the air inevitably, forms natural oxidizing layer (native oxide), how to eliminate of the influence of this natural oxidizing layer to device performance, also be form high-quality metal silicide one of the problem that must pay close attention to.
The method of existing removal silicon surface oxidation layer influence mainly contains two: the one, and utilize argon plasma bombardment silicon face to remove its surface oxide layer, but this method easy damaged silicon chip cause the increase of leakage current; The 2nd, on metal level, cover one deck active layer again, as titanium, but this titanium layer can react with the metal level of lower floor, consumes lower metal layer, and the result causes the formation thickness of metal silicide wayward, may increase the resistance of device on the contrary.
Application number is that 200310103321.6 Chinese patent discloses a kind of method that forms metal silicide, this method forms natural oxidizing layer in order to solve because of silicon chip surface contacts with air, and the problem that the device performance that causes descends, after forming the MOS structure, deposited one deck active layer Ti earlier, utilize its good deoxygenation ability to remove the natural oxidizing layer of silicon chip surface, and then depositing metal layers thereon, and form metal silicide CoSi
2This method has solved the influence of silicon chip surface oxide layer to device performance to a certain extent, but the active layer Ti in this method is isolated between metal Co and the silicon materials, reduced the quality of the cobalt silicide of final formation, for the technology below 0.18 micron, the introducing of this Ti layer is unfavorable on the contrary to the performance that improves device, the problem that the device performance that the actual inreal autoxidation that solves because of silicon chip surface causes descends.In addition, this method same existence because of Ti layer and Co layer react produces the problem of consumption.
Summary of the invention
The invention provides a kind of formation method of metal silicide, this method can improve the formation quality of metal silicide, improves device performance.
The formation method of a kind of metal silicide provided by the invention comprises step:
Provide a surface to have the substrate of silicon materials;
On described substrate, form a metal level;
On described metal level, form a barrier layer;
On described barrier layer, form an active layer;
Described substrate is heat-treated the formation metal silicide;
The described metal level that erosion removal does not react with described silicon materials.
Wherein, described metal level is cobalt or nickel dam, and thickness is between 50 to 200 ; Described barrier layer is a titanium nitride layer, and thickness is between 100 to 300 ; Described active layer is a titanium layer, and thickness is between 30 to 150 .
Wherein, described metal level, barrier layer and active layer are to utilize the mode of physical vapour deposition (PVD) to form, and used depositing temperature is all between 15 to 50 ℃.
Wherein, described heat treatment is quick thermal annealing process, and treatment temperature is between 200 to 500 ℃.The metal silicide that the annealing back forms is CoSi
2Or NiSi.
Wherein, the substrate that described surface has silicon materials has the silicon substrate of a plurality of grid structures and source, drain electrode for the surface, and described grid structure is the polysilicon gate with side wall layer.
Compared with prior art, the present invention has the following advantages:
The formation method of metal silicide of the present invention, by on metal level, depositing one deck barrier layer earlier, deposit the method for one deck active layer again, utilize the strong deoxygenation ability of this active layer, the oxide of silicon chip surface is removed, with airborne oxygen shielding outside, improved the formation quality of metal silicide, reduce the leakage current of device, improved device performance.
The formation method of metal silicide of the present invention because of the active layer that is increased does not directly contact with silicon materials, can not cause the degeneration of metal suicide interface performance, applicable to the technological requirement of various live widths, is particularly useful for the technological requirement below 0.18 micron.
The formation method of metal silicide of the present invention has the barrier layer to isolate between active layer and metal, has prevented the direct reaction of this active layer and metal, can control the formation thickness of metal silicide preferably.
Description of drawings
Figure 1A to 1D is the formation method schematic diagram of existing self aligned metal silicide;
Fig. 2 is the flow chart of the formation method of self-aligned metal silicate of the present invention;
Fig. 3 A to 3F is the formation method schematic diagram of self aligned metal silicide of the present invention;
Fig. 4 is for adopting the experimental data figure of the inventive method front and back device creepage situation.
Embodiment
For above-mentioned purpose of the present invention, feature and advantage can be become apparent more, the specific embodiment of the present invention is described in detail below in conjunction with accompanying drawing.
Processing method of the present invention can be widely applied in many application; and can utilize many suitable material; be to be illustrated below by preferred embodiment; certainly the present invention is not limited to this specific embodiment, and the known general replacement of one of ordinary skilled in the art is encompassed in protection scope of the present invention far and away.
Secondly, the present invention utilizes schematic diagram to describe in detail, when the embodiment of the invention is described in detail in detail, for convenience of explanation, the profile of expression semiconductor structure can be disobeyed general ratio and be done local the amplification, should be with this as limitation of the invention, in addition, in the making of reality, should comprise the three dimensions size of length, width and the degree of depth.
The formation method of metal silicide of the present invention, at first utilize the method for physical vapour deposition (PVD) or chemical vapour deposition (CVD) to have deposition layer of metal layer on the substrate of silicon materials on the surface, (, be generally cobalt for 0.18 micron technology, for 65nm technology, be generally nickel); Deposit a barrier layer more thereon, generally can be titanium nitride layer, can prevent that upper and lower interlayer from directly reaction taking place; And then on this barrier layer, deposit an active layer, as titanium coating; Then, this substrate is heat-treated, make to react, generate metal silicide (CoSi with contacted metal level of silicon materials (cobalt or nickel) and silicon materials
2Or NiSi), and this metal level (cobalt or nickel) with contacted other zones of silicon materials does not still remain unchanged; Utilize the method for selective wet etching with the titanium layer on surface, titanium nitride layer and metal level (cobalt or the nickel) erosion removal that do not react with silicon materials at last, only the metal silicide that will link to each other with silicon materials remains.
In this forming process, increased the titanium active layer that one deck has strong deoxygenation ability, this layer can be realized:
1, because Titanium is one to have the metal of quite high activity, it has good deoxygenation ability, in heat treatment process, Titanium diffusion downwards reacts with the native oxide of silicon face, original oxide layer is reduced, reach the purpose of removing the silicon materials oxide on surface, improved the formation quality of silicide.
2, because the densification of titanium layer material, have the ability that stops the oxygen diffusion, can effectively stop oxygen in the extraneous air to the infiltration of device inside, prevented the performance degradation that device causes because of inside is oxidized.
3, prevent that the barrier layer titanium nitride is oxidized, can be difficult to after titanium nitride layer is oxidized remove, can cause after corrosion, still can being difficult to remove clean residue at the silicon chip surface residual fraction, even and titanium layer also can be removed after oxidized totally easily, do not have the problem of residue.
In addition, in the forming process of the metal silicide that adopts nickel,, slow down the NiSi of the NiSi of low-resistance to high resistant because of the titanium of this active layer can be diffused in the interface of silicon and nickel
2Change,, guarantee that its low-resistance characteristic is constant so the existence of this titanium layer can also effectively improve the thermal stability of nickel silicide.Wherein, the raising of this nickel silicide thermal stability can obviously improve the leakage current performance of device, and this is very crucial for 65nm technology.
In addition, also utilize a barrier layer that metal level and active layer are separated among the present invention, can prevent to cause consumption because of two kinds of metals directly react, the NiSi thickness that causes forming is difficult to determine.
Fig. 2 is the flow chart of the formation method of self-aligned metal silicate of the present invention, and Fig. 3 A to 3F is the formation method schematic diagram of self aligned metal silicide of the present invention.Introduce a specific embodiment of the formation method of metal silicide of the present invention in detail below in conjunction with Fig. 2 and Fig. 3 A to 3F.
At first, the substrate (S201) that provides a surface to have silicon materials.Substrate in the present embodiment is the silicon chip with a plurality of MOS structures.Fig. 3 A is the device profile schematic diagram with a plurality of MOS structures, as shown in Figure 3A, have a plurality of MOS device architectures on the silicon substrate 101, utilize isolated groove 102 to isolate between each device, each device has a polysilicon gate 104, this grid below is pad silicon oxide layer 103 (PadOxide), and has formed gate lateral wall layer 105 on each gate lateral wall, and it can form the good protection to polysilicon gate; In addition, in the grid both sides of each device, be mask with grid structure and side wall layer, between grid, formed source/ drain doping region 107 and 108 in the mode of injecting with ion on the substrate.
Then, deposition layer of metal layer (S202) on this silicon chip.Metal silicide in the present embodiment is applied to the 65nm technology, so adopt metallic nickel to generate silicide.Fig. 3 B is the device architecture schematic diagram behind the depositing metal layers.Shown in Fig. 3 B, utilize the method for the physical vapour deposition (PVD) layer of metal nickel dam 110 of on this silicon chip, having grown, its growth thickness can be between 50 to 200 , as are 100 , and growth temperature is between 15 to 50 ℃, as getting final product under the room temperature.
Then, deposition one deck barrier layer (S203).Fig. 3 C is the device architecture schematic diagram behind the deposited barrier layer.Shown in Fig. 3 C, utilize the method for the physical vapour deposition (PVD) one deck barrier layer 310 of on this silicon chip, having grown, that adopt in the present embodiment is TiN, and its growth thickness can be between 100 to 300 , as are 200 , and growth temperature also can be between 15 to 50 ℃.Barrier layer in the present embodiment can prevent that metal level under it and the active layer on it from reacting.
Follow deposition one deck active layer (S204) on this barrier layer again.Fig. 3 D is the device architecture schematic diagram after the active layer deposited.Shown in Fig. 3 D, utilize the method for the physical vapour deposition (PVD) one deck active layer 320 of on this silicon chip, having grown, that adopt in the present embodiment is Ti, its growth thickness can be between 30 to 150 , as be 200 , growth temperature also can be between 15 to 50 ℃, as room temperature.
In the present embodiment, metal level nickel 110, barrier layer titanium nitride 310 and active layer titanium 320, be to utilize method one secondary growth of physical chemistry vapour deposition to finish, its growth temperature all gets final product about room temperature, in other embodiments of the invention, the above-mentioned three layers of method that can also utilize chemistry or physical vapour deposition (PVD) are grown respectively and are formed.
After growth is finished, this substrate is heat-treated, generate metal silicide (S205).Fig. 3 E is the device architecture schematic diagram after the heat treatment.Shown in Fig. 3 E, utilize quick thermal annealing process to form metal silicide 330 at silicon materials and the contacted zone of metal level, other zones on substrate are on the side wall layer of silica as the surface, metal can not react, and can not form metal silicide.The temperature that rapid thermal annealing adopts in the present embodiment as is 300 ℃ between 200 to 500 ℃.
Form high-quality metal silicide, to guarantee that at first the silicide that forms has the low-resistance characteristic, the NiSi silicide of in the following technology of 65nm, using always that adopts in the present embodiment, this point will especially be noted, because the NiSi of low-resistance is a kind of intermediateness, easily change the NiSi of high resistant into
2So, how to stop NiSi to NiSi
2Conversion be one of key issue of nickel silicide technology.In the present embodiment, because the existence of active layer titanium is arranged, in heat treatment process, the titanium diffusion downwards that the deoxygenation ability is strong, the oxygen on silicon materials surface can be removed on the one hand, improve the formation quality of silicide, also can stop the NiSi at contact interface place to be condensed into the NiSi of high resistant on the other hand
2, the thermal stability of raising NiSi.
At last, can utilize wet etching optionally to remove the metal silicide that does not react, form self aligned metal suicide structure (S206).Fig. 3 F is the device architecture schematic diagram after the active layer deposited.Shown in Fig. 3 F, after heat treatment, need be with Ti layer 320, titanium nitride layer 310 erosion removals on surface, then, utilize the selectivity of corrosive liquid again, the metal Ni that does not react is removed, only stay the metal silicide NiSi that reacts and afterwards form with silicon materials, it has lower resistance.
In addition, after the method processing by present embodiment, the quality of the metal silicide of formation is higher, can reduce device creepage, effectively improves the electrical characteristics of device.Fig. 4 is for adopting the experimental data figure of the inventive method front and back device creepage situation.Wherein, abscissa is the element leakage current density that test obtains, and ordinate is corresponding device distribution percentage (%).As shown in Figure 4, curve group 401 is not adopt the test results of devices of active layer of the present invention among the figure, and curve group 402 is to adopt the test results of devices of active layer of the present invention, by can obviously seeing among the figure, after adopting technology of the present invention, device has had significant improvement aspect leakage current.
In addition, for titanium nitride, if it be exposed to can be by partial oxidation in the air, (especially for long silicon chip of the time of shelving, the oxidation situation can be even more serious), titanium nitride difficult removal the when corrosion after oxidized, easy residual fraction residue influences the rate of finished products of device.In the etching process of present embodiment, because this barrier layer surface covered one deck active layer titanium, it can prevent that the barrier layer titanium nitride is oxidized, even and this titanium layer oxidized after, in wet corrosion technique, also be easy to be removed clean, so can improve the problem of corrosion residue effectively.
What describe in the present embodiment is that contact electrode on the silicon chip with MOS structure is sentenced the method that self-aligned manner forms metal silicide, in other embodiments of the invention, can also utilize method of the present invention to have and form high-quality metal silicide on the substrate slice of silicon materials on any surface.
Though the present invention with preferred embodiment openly as above; but it is not to be used for limiting the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; can make possible change and modification, so protection scope of the present invention should be as the criterion with the scope that claim of the present invention was defined.
Claims (14)
1. the formation method of a metal silicide is characterized in that, comprising:
Provide a surface to have the substrate of silicon materials;
On described substrate, form a metal level;
On described metal level, form a barrier layer;
On described barrier layer, form an active layer;
Described substrate is heat-treated the formation metal silicide;
The described metal level that erosion removal does not react with described silicon materials.
2. formation method as claimed in claim 1 is characterized in that: described metal level is cobalt or nickel dam.
3. formation method as claimed in claim 1 or 2 is characterized in that: described metal layer thickness is between 50 to 200 .
4. formation method as claimed in claim 1 is characterized in that: described barrier layer is a titanium nitride layer.
5. as claim 1 or 4 described formation methods, it is characterized in that: described barrier layer thickness is between 100 to 300 .
6. formation method as claimed in claim 1 is characterized in that: described active layer is a titanium layer.
7. as claim 1 or 6 described formation methods, it is characterized in that: described active layer thickness is between 30 to 150 .
8. formation method as claimed in claim 1 is characterized in that: described metal level, described barrier layer and described active layer are to utilize the mode of physical vapour deposition (PVD) to form.
9. as claim 1 or 8 described formation methods, it is characterized in that: the temperature of described deposition is all between 15 to 50 ℃.
10. formation method as claimed in claim 1 is characterized in that: described heat treatment is quick thermal annealing process.
11. formation method as claimed in claim 10 is characterized in that: the temperature of described quick thermal annealing process is between 200 to 500 ℃.
12. formation method as claimed in claim 1 is characterized in that: described metal silicide is CoSi
2Or NiSi.
13. formation method as claimed in claim 1 is characterized in that: the substrate that described surface has silicon materials has the silicon substrate of a plurality of grid structures and source, drain electrode for the surface.
14. formation method as claimed in claim 13 is characterized in that: described grid structure is the polysilicon gate with side wall layer.
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102446744A (en) * | 2011-10-12 | 2012-05-09 | 上海华力微电子有限公司 | Method for removing excessive nickel after formation of nickel silicide |
| CN102456560A (en) * | 2010-10-29 | 2012-05-16 | 中芯国际集成电路制造(上海)有限公司 | Method for generating nickel alloy self-aligned silicide |
| CN105762069A (en) * | 2016-02-04 | 2016-07-13 | 浙江大学 | Method for performing selective growth of metal on surface of semiconductor substrate by using electrochemical deposition |
| CN108987249A (en) * | 2017-06-01 | 2018-12-11 | 无锡华润上华科技有限公司 | The forming method of silicon cobalt substrate in semiconductor device |
-
2006
- 2006-09-04 CN CNA2006100308107A patent/CN101140872A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102456560A (en) * | 2010-10-29 | 2012-05-16 | 中芯国际集成电路制造(上海)有限公司 | Method for generating nickel alloy self-aligned silicide |
| CN102456560B (en) * | 2010-10-29 | 2014-11-05 | 中芯国际集成电路制造(上海)有限公司 | Method for generating nickel alloy self-aligned silicide |
| CN102446744A (en) * | 2011-10-12 | 2012-05-09 | 上海华力微电子有限公司 | Method for removing excessive nickel after formation of nickel silicide |
| CN105762069A (en) * | 2016-02-04 | 2016-07-13 | 浙江大学 | Method for performing selective growth of metal on surface of semiconductor substrate by using electrochemical deposition |
| CN108987249A (en) * | 2017-06-01 | 2018-12-11 | 无锡华润上华科技有限公司 | The forming method of silicon cobalt substrate in semiconductor device |
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