Embodiment
As shown in Figure 1, use EZUSB single-chip microcomputer and upper machine communication among the present invention, a boot is arranged in the single-chip microcomputer, host computer is by being similar to the interface of JATG, the working routine of single-chip microcomputer is downloaded in the single-chip microcomputer, single-chip microcomputer is carried out the working routine of single-chip microcomputer under the control of boot, carry out secondary after being finished and reset.Dispose FPGA circuitry needed file in single-chip microcomputer by the host computer dynamic download then, Single-chip Controlling FPGA dynamic-configuration hardware circuit.To the process of single-chip microcomputer, can dispose the FPGA hardware circuit from host computer download configuration FPGA circuitry needed file simultaneously; After can waiting until that also the circuit file download finishes, dispose the FPGA hardware circuit again.
As shown in Figure 2, the signals of underlying computer passage has program control ground connection to be provided with, when not having useful signal to flow through passage, programmed switch closes, and by resistance, electric capacity or inductance are with passage ground connection, certain time before useful signal arrives, programmed switch disconnects, and recovers the normal channel signal processing function, and the setting of this function can effectively prevent to accumulate on the cable electromagnetic oscillation interference that electric field may cause.
Shown in Figure 3, be the synoptic diagram of first embodiment of the invention, total system adopts the dual-computer redundancy configuration, and two cover computing machines can carry out data acquisition simultaneously, also can gather by a cover, another set of explanation, dual system also can backup each other, the system reliability height.It comprises:
(1) dual signal pretreatment unit case
Each pretreatment unit case comprises a standard signal and gathers slot, two AC/DC (Switching Power Supply of ± 12V ± 5V), the degree of depth tension display unit that one cover works alone, (10~50Hz is adjustable for the electrode frequency for an electrode supply modulator, 0~300Vp-p is adjustable for electric current 0~300mA voltage, the belt current curve), a hole diameter constant-current supply (5mA/2mA12V); A capacitance matching disc.
(2) duplex computer system
All join P4CPU/2.8G, 512MB internal memory, 80G hard disk, DVD recording optical driver (R/W), front and back USB interface, 15 cun LCD of opening door; Duplex computer is put LAN (Local Area Network) mutually, printer is shared and is provided with.
(3) two reference power supply casees
(4) 820 printer box
(5) dual trace oscilloscope casees
(6) general supply control UPS casees, the online UPS of 2000VA pauses on configuration machine cabinet type mountain.
(7) system software: UNILOG2000 numerical control well logging software one cover
SK2004 numerically controlled perforating software one cover
Individual system adopts master-slave mode observing and controlling structure, and computer system (host computer) is passed through USB (universal serial bus) (USB) communication with Signal Pretreatment Cell (slave computer).Host computer utilizes USB interface, logging program and control command that following biography slave computer is carried out, and gather, write down, show the log data that slave computer is uploaded.In each image data bag that slave computer is uploaded depth mark and time tag are arranged all, give the accurately foundation of location of packet during as software processes, the delay of packet can not influence the software processes result.The core of slave computer adopts the extensive high speed field programmable logic module (SRAM-FPGA) based on SRAM, has highly versatile.For different well logging projects, by host computer dynamic download different logging program and control command, slave computer is finished logging tasks according to the program that passes under the host computer and the mini system hardware circuit of the corresponding well logging function of control command dynamic-configuration.The dynamic-configuration of mini system hardware circuit has realized the flexible combination of well logging function, solved the slave computer resource occupation too much, the too huge problem of system, avoided many unpredictable hidden danger that cause because of system is huge.
Standard signal in the described Signal Pretreatment Cell is gathered slot, and as the core of digital control system, it is made up of analog channel plate, pulse passage plate, FPGA plate, signal simulation plate, negative several sections.Respectively several sections is described below.
On the analog board He on the pulse plate programmable amplifying circuit is arranged all, it is made up of digital regulation resistance and operational amplifier, and host computer is controlled digital regulation resistance by FPGA.
Analog board (anlog1.pcb) has 8 road simulating signal amplification filtering passages, and AD1 (SP)/AD6 (CCL)/AD7 (TEN)/AD8 (MMD) is a designated lane, and its parametric filtering has certain specific aim; AD2/AD3/AD4/AD5 is a general channels, can do the acquisition channel of 4m, 2.5m, 0.5m electrode and signals such as electrode current, hole diameter in conventional electrodes.8 tunnel 64 stages of digital pot X9241 control is adopted in the simulating signal gain, gain step units 1/3,21 times of maximum programme-controlled gains.In the well logging, 16 special-purpose high-speed a/d chips are arranged on the FPGA plate, it adopts the formula of cruising uninterruptedly to gather to 8 road simulating signals.
Pulse plate (puls1.pcb) has 4 autolytes towards signal amplification filtering passage, 4 positive 4 negative totally 8 autolytes are towards logic level passage relatively, and these 4 basic pulse passages all can be finished separating of normal pulsed signal, sound wave class signal, various coded signals and be in harmonious proportion the high-speed a/d collection.The gain control of 4 pulse passages is the same with analog board, and 8 program control settings of comparative level D/A all reach 4096 grades, are finished by AD7568; 8 comparative level results directly enter FPGA, so FPGA can finish the demodulation of 4 road coded signals simultaneously in theory; In the well logging process, 16 high-speed a/d conversions are done in a road in the program control selection 4 tunnel.
The FPGA plate has the fpga chip of a core, the high-speed a/d of two symmetries (AD7723) passage, and USB medium chip (AN2131) etc.This plate is as the core of slave computer, employing is based on the FPGA programming of SRAM, programming information reads in from external memory storage SRAM, earlier in this storer, search and read required circuit during well logging, if do not store required circuit in the storer, circuit is downloaded in the storer by USB by host computer again, this storer the reading speed that has improved circuit in the well logging process is set.The setting of two-way symmetry AD makes the switching between data acquisition high speed signal and the low speed signal more flexible.In addition, also have the combination of a slice generic storage chip and fpga chip to realize the function of push-up storage (FIFO) on this plate, image data is done caching process, image data can not lost yet when this was provided with and guarantees that host computer has slight obstruction.
Signal simulation plate (em3.pcb) can be finished positive negative pulse stuffing signal, modulation and the non-modulation acoustic signals of program control emulation depth signal, frequency adjustable, programmable original graceful sign indicating number and the graceful coded signal of differential, make zero with non return to zero AMI coded signal, 3502,3506,3508 simulate signal, gyrostatic simulate signal, and the various applied in any combination between them.Simultaneously, the emulation delivery outlet also is the driving mouth that the down-hole instrument issues logic, transmitting order to lower levels, and by FPGA control, it is from two approach, be OTL bipolar driving and transformer differential driving, the transmission of compatible with single core electric cable capacitance coupling two-way, the transmission of polycore cable differential transformers coupling two-way.
Special oscillograph output interface is arranged on the base plate, some signal of interests can be delivered on the oscillograph and be observed.In the numerical control well logging, the two track signal input parts of oscillograph, by the program-controlled electronic switch, can all kinds of simulate signals of real-time monitored, the entry signal of each passage of observation pulse, amplifying signal, 8 channel ratios than level, 8 channel ratios than the demodulation synchronization signal of consequential signal, each channel coding signal and FPGA inside to the acquisition logic signal of high-speed a/d slice, thin piece etc.And oscillograph can selectively add brightness, synchronous to signal.The oscillograph electronic switch, MAX333A forms by multi-disc, and main switch is responsible for the signal of conversion from emulation board, pulse plate, FPGA plate on analog circuit board, and inferior one-level switch is at pulse plate etc.
The special online 1KWUPS power supply in described general supply control UPS case configuration machine posture mountain, on the well logging scene, when the unexpected power down of system, UPS can guarantee that on-the-spot instrument data and well logging information can not lose because of power down suddenly, and handled easily person preserves the related logging file.
Described oscillograph adopts GW GOS-6112 100MHz dual trace oscilloscope, and oscillograph " CH1 " connects slave computer channel oscilloscope 1, is used for the signal (comprising sound wave and graceful sign indicating number) that the watchdog pulse plate amplifies output; Oscillograph " CH2 " connects slave computer channel oscilloscope 2, is used for comparative result or other FPGA internal signal of watchdog pulse plate passage, and wherein the address of pulse passage and FPGA internal signal are by the program control decision of software; Oscillograph Z axle input termination slave computer oscillograph adds brightness; Oscillograph external trigger input termination slave computer oscillograph external trigger.
Described system software adopts VC/MFC to write based on Windows2000/XP multiple task operating system platform; Friendly interface, easy and simple to handle.Device driver is write standard development by Microsoft's DDK/WDM driver, and Microsoft 98 and above operating system are suitable for entirely, do not have compatibility issue.Program structure adopts OO hierarchy, and modular design has good instrument and articulates expansion and function expansion.Owing to adopt the multilayer diagnostic system, can monitor each link state of well logging, can locate by software when breaking down in system, the System Fault Tolerance performance is good.Can export the data and the chart of various forms by user's application request combination in any, can store playback of data, and have the real time print function.The lower computer hardware function is downloaded by the usb bus program by host computer, and the hardware parameter setting is finished by the upper computer software window operation.Software has online help function.
As shown in Figure 4, be the synoptic diagram of second embodiment of the invention, system need be used with notebook computer as a kind of portable logging system.Total system adopts master-slave mode observing and controlling structure, and notebook computer (host computer) passes through USB (universal serial bus) (USB) communication with portable logging system (slave computer).Host computer utilizes USB interface, program and steering order that following biography slave computer is carried out, and gather, write down, show the log data that slave computer is uploaded.For different well logging projects, by host computer dynamic download different logging program and steering order, slave computer is finished logging tasks according to the program that passes under the host computer and the mini system hardware circuit of the corresponding well logging function of steering order dynamic-configuration.The dynamic-configuration of mini system hardware circuit has realized the flexible combination of well logging function, solved the slave computer resource occupation too much, the too huge problem of system, avoided the huge unpredictable hidden danger that causes of many systems.