CN101136374A - Process for manufacturing nonvolatile semiconductor memory - Google Patents
Process for manufacturing nonvolatile semiconductor memory Download PDFInfo
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- CN101136374A CN101136374A CNA2006101263419A CN200610126341A CN101136374A CN 101136374 A CN101136374 A CN 101136374A CN A2006101263419 A CNA2006101263419 A CN A2006101263419A CN 200610126341 A CN200610126341 A CN 200610126341A CN 101136374 A CN101136374 A CN 101136374A
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 53
- 238000000034 method Methods 0.000 title claims description 103
- 239000004065 semiconductor Substances 0.000 title 1
- 239000000758 substrate Substances 0.000 claims abstract description 50
- 239000004020 conductor Substances 0.000 claims abstract description 45
- 238000003860 storage Methods 0.000 claims abstract description 43
- 239000000463 material Substances 0.000 claims description 27
- 230000015572 biosynthetic process Effects 0.000 claims description 25
- 239000008393 encapsulating agent Substances 0.000 claims description 19
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 12
- 125000006850 spacer group Chemical group 0.000 claims description 10
- 239000000377 silicon dioxide Substances 0.000 claims description 6
- 238000003701 mechanical milling Methods 0.000 claims description 5
- 239000000126 substance Substances 0.000 claims description 5
- 239000002184 metal Substances 0.000 claims description 3
- 229910052751 metal Inorganic materials 0.000 claims description 3
- 230000014759 maintenance of location Effects 0.000 abstract 1
- 238000005229 chemical vapour deposition Methods 0.000 description 5
- 238000000926 separation method Methods 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 4
- 238000005530 etching Methods 0.000 description 4
- 238000001312 dry etching Methods 0.000 description 3
- 238000005468 ion implantation Methods 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 239000003989 dielectric material Substances 0.000 description 2
- 239000007769 metal material Substances 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000007599 discharging Methods 0.000 description 1
- 238000011065 in-situ storage Methods 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 238000012797 qualification Methods 0.000 description 1
- 238000000547 structure data Methods 0.000 description 1
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 description 1
- 229910021342 tungsten silicide Inorganic materials 0.000 description 1
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Abstract
This invention discloses a manufacturing method for non-volatile storages, which first of all provides a substrate and forms multiple storage devices on it with a first open-end on each side between two adjacent storage devices and then forms a first dielectric layer on the side wall and bottom of the first open-end, then forms a square stack structure on the first dielectric layer of either side wall of the first open-end including a conductor layer and a filling layer from the bottom to up, and after that forms a clearance wall on the side wall of one side of each square stack structure in each of the first open-end and forms a first doped region in the substrate exposed by the clearance wall in each of the first open-end.
Description
Technical field
The present invention relates to a kind of manufacture method of nonvolatile memory, particularly relate to the manufacture method of a kind of grids flash memory separation (Split Gate Flash Memory).
Background technology
Nonvolatile memory (Nonvolatile memory) now is applied in the use of various electronic installations, as memory structure data, routine data and other can repeated access data.And on programmable non-volatile memory, more emphasize recently as flash memory structure wipe and programmable read only memory (ErasableProgrammable Read-Only Memory, EPROM) or the application of electro-erasable programmable read-only memory (Electrically Erased Programmable ROM).
Typical flash memory device is to make floating grid (Floating Gate) and control grid (Control Gate) with the polysilicon that mixes.And, be separated by with dielectric layer between floating grid and the control grid, and be separated by with tunnel oxide (Tunnel Oxide) between floating grid and substrate.When flash memory being carried out the operation of write/erase (Write/Erase) data, apply bias voltage by giving control grid and source/drain regions, so that electronics injects floating grid or electronics is pulled out from floating grid.And during the data in reading flash memory, be on the control grid, to apply operating voltage, this moment, the electriferous state of floating grid can influence the ON/OFF of its lower channel (Channel), and the ON/OFF of this raceway groove is the foundation of interpretation data value " 0 " or " 1 ".
When above-mentioned flash memory when carrying out the wiping of data because the electron amount of discharging from floating grid is wayward, so easily make floating grid discharge polyelectron and have positive charge, this is called over-erasure (Over-erase).When this over-erasure phenomenon is too serious, in addition the raceway groove that can make the floating grid below grid is undressed when making voltage in control, promptly continue to be conducting state, and cause the erroneous judgement of data.
For the problem of solving device over-erasure, this area proposes a kind of grids flash memory separation at present.The profile of existing grids flash memory separation that Fig. 1 is shown as.Please refer to Fig. 1, in this flash memory, stacked gate architectures 102 is by 100 of substrates, be followed successively by dielectric layer 108 between tunnel dielectric layer 104, floating grid 106, grid (Inter-gate Dielectric), control grid 110 and cap layer 112, the selection grid 114 that is the clearance wall shape is positioned on the sidewall of stacked gate architectures 102, selects to be separated by with dielectric layer 116 between grid 114 and stacked gate architectures 102, the substrate 100.Source area 118 is arranged in the substrate 100 of stacked gate architectures 102 1 sides, and 120 of drain regions are arranged in the substrate 100 of selecting grid 114 1 sides.Thus, too serious when excessively wiping phenomenon, and make floating grid 106 below raceway grooves in that control grid 110 is undressed when doing promptly to continue to open under the voltage status, select the raceway groove of grid 114 belows still can keep closed condition, make that source area 118 and drain region 120 can't conductings, and can prevent the erroneous judgement of data.
Yet, because in the structure of above-mentioned grids flash memory separation, select grid 114 and clearance wall 122 to present the clearance wall shape, therefore the process margin (Process Window) of the self-aligned contact hole that is electrically connected with drain region 120 in follow-up formation is less, make formed contact hole easily with the phenomenon of selection grid 114 generation short circuits.
Summary of the invention
Given this, one object of the present invention just provides a kind of manufacture method of nonvolatile memory, can improve the process margin of nonvolatile memory.
A further object of the present invention provides a kind of manufacture method of nonvolatile memory, can avoid selecting grid and contact hole to produce short circuit.
The present invention proposes a kind of manufacture method of nonvolatile memory, and substrate at first is provided, and has been formed with a plurality of storage arrangements on the substrate, have first opening in a side of each storage arrangement, and each first opening is between adjacent two storage arrangements.Then, form first dielectric layer at first opening sidewalls and bottom.Then, form a square shape stacked structure respectively on first dielectric layer of each first opening both sides sidewall, each square shape stacked structure from bottom to top comprises conductor layer and packed layer.Next, in each first opening, form clearance wall on the sidewall of each square shape stacked structure one side.Afterwards, in the substrate that each first opening intermediate gap wall is exposed, form first doped region.
Described according to the preferred embodiments of the present invention, in the manufacture method of above-mentioned nonvolatile memory, the formation method of square shape stacked structure at first forms conformal first dielectric layer and overlaying memory device on substrate.Then, on first dielectric layer, form conformal conductor layer.Then, form second dielectric layer on conductor layer, second dielectric layer fills up first opening.Next, remove part second dielectric layer, segment conductor layer and part of first dielectric layer, to expose storage arrangement.Afterwards, remove the segment conductor layer that is positioned on each first opening both sides sidewall, and between each storage arrangement and second dielectric layer, respectively form one second opening.Continue it, in second opening, form the packed layer that fills up second opening.Subsequently, remove second dielectric layer that is arranged in first opening, and expose the segment conductor layer.Moreover, remove the conductor layer that is exposed.
Described according to the preferred embodiments of the present invention, in the manufacture method of above-mentioned nonvolatile memory, in second opening, form the method for the packed layer that fills up this second opening, at first on substrate, form encapsulant layer, encapsulant layer fills up second opening.Then, remove second opening encapsulant layer in addition.
Described according to the preferred embodiments of the present invention, in the manufacture method of above-mentioned nonvolatile memory, the method that removes of the encapsulant layer beyond second opening is chemical mechanical milling method or etch-back method.
Described according to the preferred embodiments of the present invention, in the manufacture method of above-mentioned nonvolatile memory, the material of packed layer comprises metal.
Described according to the preferred embodiments of the present invention, in the manufacture method of above-mentioned nonvolatile memory, the material of packed layer comprises silica.
Described according to the preferred embodiments of the present invention, in the manufacture method of above-mentioned nonvolatile memory, the formation method of clearance wall at first forms spacer material layer, overlaying memory device and square shape stacked structure on substrate.Then, the spacer material layer is carried out an etch back process.
Described according to the preferred embodiments of the present invention, in the manufacture method of above-mentioned nonvolatile memory, memory device is changed to stacked gate architectures, and stacked gate architectures from bottom to top comprises wears dielectric layer and control grid between dielectric layer, floating grid, grid then.
Described according to the preferred embodiments of the present invention, in the manufacture method of above-mentioned nonvolatile memory, stacked gate architectures also comprises cap layer, is configured on the control grid.
Described according to the preferred embodiments of the present invention, in the manufacture method of above-mentioned nonvolatile memory, opposite side at each storage arrangement has one the 3rd opening, and the 3rd opening is between adjacent two storage arrangements, and the width of the 3rd opening is less than the width of first opening.
Described according to the preferred embodiments of the present invention, in the manufacture method of above-mentioned nonvolatile memory, also be included in the substrate of the 3rd opening below and form second doped region.
The present invention proposes the manufacture method of another kind of nonvolatile memory, substrate at first is provided, be formed with a plurality of storage arrangements that are configured in respectively in a plurality of grooves in the substrate, storage arrangement protrudes in substrate surface, and has first opening between adjacent two storage arrangements.Then, form first dielectric layer at first opening sidewalls and bottom.Then, form a square shape stacked structure respectively on first dielectric layer of each first opening both sides sidewall, each square shape stacked structure from bottom to top comprises conductor layer and packed layer.Next, in each first opening, form clearance wall on the sidewall of each square shape stacked structure one side.Afterwards, in the substrate that each first opening intermediate gap wall is exposed, form first doped region.
Described according to the preferred embodiments of the present invention, in the manufacture method of above-mentioned nonvolatile memory, memory device is changed to the plough groove type structure, and the plough groove type structure comprises second doped region, the 3rd dielectric layer, two floating grids, column source electrode line and the 4th dielectric layers.Second doped region is configured in the substrate of channel bottom.The 3rd dielectric layer is configured on trenched side-wall and the bottom.Two floating grids are configured in the groove two side respectively, and are positioned on the 3rd dielectric layer.The column source electrode line is configured in the groove and is connected on second doped region, and the top of column source electrode line is higher than the surface of substrate.The 4th dielectric layer is configured in the groove, and between floating grid and column source electrode line.
Described according to the preferred embodiments of the present invention, in the manufacture method of above-mentioned nonvolatile memory, each plough groove type structure also comprises cap layer, is configured on the column source electrode line.
Based on above-mentioned, because in the nonvolatile memory produced according to the manufacture method of nonvolatile memory proposed by the invention, select grid structure to be to use the square shape stacked structure that presents the square shape, the process margin in the time of therefore can increasing follow-up formation contact hole.
In addition, the manufacture method of nonvolatile memory proposed by the invention can form clearance wall in a side of square shape stacked structure, therefore can prevent to select formed contact hole generation short circuit in grid and the subsequent technique.
On the other hand, when forming square shape stacked structure, can utilize packed layer, not need additionally to form mask layer, can simplify technology and reduce manufacturing cost as mask layer.
For above and other objects of the present invention, feature and advantage can be become apparent, preferred embodiment cited below particularly, and in conjunction with the accompanying drawings, be described in detail below.
Description of drawings
The profile of existing grids flash memory separation that Fig. 1 is shown as.
The manufacturing process profile of the nonvolatile memory of Fig. 2 A to Fig. 2 embodiment of the invention that D is shown as.
The manufacturing process profile of the nonvolatile memory of Fig. 3 A to Fig. 3 embodiment of the invention that B is shown as.
The simple symbol explanation
100,200,300: substrate
102: stacked gate architectures
104,204: tunnel dielectric layer
106,206,312: floating grid
108,208: dielectric layer between grid
110,210: the control grid
112,212,318: cap layer
122,232,328: clearance wall
114: select grid
116,218,222,310,316,320: dielectric layer
118: source area
120: the drain region
202: storage arrangement
214,216,224,226,306: opening
220,324: conductor layer
228,326: packed layer
230,322: square shape stacked structure
234,236,308,330: doped region
304: groove
314: the column source electrode line
Embodiment
The manufacturing process profile of the nonvolatile memory of Fig. 2 A to Fig. 2 embodiment of the invention that D is shown as.
At first, please refer to Fig. 2 A, substrate 200 at first is provided, be formed with a plurality of storage arrangements 202 on the substrate 200.Storage arrangement 202 for example is a stacked gate architectures, and this stacked gate architectures is from bottom to top for example formed by wearing then between dielectric layer 204, floating grid 206, grid dielectric layer 208, control grid 210 and cap layer 212.Yet the structure of above-mentioned storage arrangement 202 is not in order to restriction the present invention.
In addition, side at each storage arrangement 202 has opening 214, opposite side at each storage arrangement 202 has opening 216, and opening 214 and opening 216 lay respectively between adjacent two storage arrangements 202, and the width of opening 214 is greater than the width of opening 216.
Then, on substrate 200, form conformal dielectric layer 218 and overlaying memory device 202, the sidewall of opening 214 and the sidewall and the bottom of bottom and opening 216, use mask layer that the dielectric layer 218 of opening 216 bottoms is removed subsequently, and with ion implantation definition doped region 236, and doped region 236 is connected with the conductor layer 220 that deposits subsequently.The material of dielectric layer 218 for example is a silica, and its formation method for example is a chemical vapour deposition technique.
Then, on dielectric layer 218, form conformal conductor layer 220.Conductor layer 220 is formed by the material with different etching selectivities with cap layer 210.Because the width of opening 214 is bigger, the conductor layer 220 that therefore is arranged in opening 214 can form recess; Because the width of opening 216 is less, the conductor layer 220 that therefore is arranged in opening 214 can fill up opening 216.The material of conductor layer 220 for example is a doped polycrystalline silicon, and its formation method for example is to carry out chemical vapor deposition method and form in the mode of doped in situ.
Next, form dielectric layer 222 on conductor layer 220, dielectric layer 222 fills up opening 214.Dielectric layer 222 is formed by the material with different etching selectivities with cap layer 210.The material of dielectric layer 222 for example is a silicon nitride, and its formation method for example is a chemical vapour deposition technique.
Afterwards, please refer to Fig. 2 B, next, remove part dielectric layer 222, segment conductor layer 220 and part dielectric layer 218, to expose storage arrangement 202.Part dielectric layer 222, segment conductor layer 220 for example are chemical mechanical milling methods with the method that removes of part dielectric layer 218.
Continue it, remove the segment conductor layer 220 that is positioned on the opening 214 both sides sidewalls, and between each storage arrangement 202 and dielectric layer 222, respectively form an opening 224.Removing the method that is positioned at the segment conductor layer 220 on the opening 214 both sides sidewalls for example is the dry-etching method.In the segment conductor layer 220 on removing opening 214 both sides sidewalls, can remove the segment conductor layer 220 in the opening 216 simultaneously, and form opening 226.
Subsequently, in opening 224 and opening 226, form the packed layer 228 that fills up opening 224 and opening 226.Packed layer 228 is formed by the material with different etching selectivities with conductive material layer 220.The formation method of packed layer 228 for example is to form earlier encapsulant layer (showing) on substrate 200, and encapsulant layer fills up opening 224 and opening 226, then removes the encapsulant layer beyond opening 224 and the opening 226 and forms.Wherein, the method that removes the encapsulant layer beyond opening 224 and the opening 226 for example is chemical mechanical milling method or etch-back method.The material of encapsulant layer for example is dielectric materials such as metal materials such as tungsten silicide or silica.When the material of encapsulant layer was metal material, its formation method for example was a physical vaporous deposition.When the material of encapsulant layer was dielectric material, its formation method for example was a chemical vapour deposition technique.
Moreover, please refer to Fig. 2 C, remove the dielectric layer 222 that is arranged in opening 224, and expose segment conductor layer 220.The method that removes of the dielectric layer 222 in the opening 224 for example is the dry-etching method.
Then, remove the conductor layer 220 that is come out, and on the dielectric layer 218 of opening 224 both sides sidewalls, form a square shape stacked structure 230 respectively, to use as the selection grid structure.Square shape stacked structure 230 from bottom to top comprises conductor layer 220 and packed layer 228.The method that removes the conductor layer 220 that is come out for example is the dry-etching method.
Then, please refer to Fig. 2 D, form clearance wall 232 on the sidewall of square shape stacked structure 230 1 sides in opening 224.The formation method of clearance wall 232 for example is to form spacer material layer (not showing) earlier on substrate 200, overlaying memory device 202 and square shape stacked structure 230, then the spacer material layer is carried out etch back process and form, the material of clearance wall for example is a silicon nitride.
Next, form doped region 234 in the substrate 200 that opening 224 intermediate gap walls 232 are exposed, doped region 234 for example is as the drain region.The formation method of doped region 234 for example is an ion implantation.
In the formed nonvolatile memory of the foregoing description, be the square shape stacked structure 230 that presents the square shape owing to select grid structure, therefore can improve the process margin when forming contact hole in the subsequent technique effectively.
In addition, at the side formation clearance wall 232 of square shape stacked structure 230, can prevent that therefore the contact hole that forms in square shape stacked structure 230 and the subsequent technique from producing short circuit.
On the other hand, because packed layer 228, cap layer 210 have different etching selectivities with dielectric layer 222, conductor layer 220, therefore in removing dielectric layer 222 and segment conductor layer 220 etch process with formation square shape stacked structure 230, packed layer 228, cap layer 210 can be used as mask layer and use, and do not need additionally to form mask layer.Therefore, can simplify technology and reduce manufacturing cost.
The manufacturing process profile of the nonvolatile memory of Fig. 3 A to Fig. 3 embodiment of the invention that B is shown as.
At first, please refer to Fig. 3 A, substrate 300 is provided, be formed with a plurality of storage arrangements 302 that are configured in respectively in a plurality of grooves 304 in the substrate 300, storage arrangement 302 protrudes in substrate 300 surfaces, and has opening 306 between adjacent two storage arrangements 302.
Then, on opening 306 sidewalls and bottom, form dielectric layer 320.The material of dielectric layer 320 for example is a silica, and its formation method for example is a chemical vapour deposition technique.
Then, form a square shape stacked structure 322 respectively on the dielectric layer 320 of opening 306 both sides sidewalls, each square shape stacked structure 320 from bottom to top comprises conductor layer 324 and packed layer 326.Wherein, the formation method of square shape stacked structure 230 is roughly the same among the formation method of square shape stacked structure 322 and Fig. 2 A to Fig. 2 C, so repeat no more in this.
Next, please refer to and form clearance wall 328 on the sidewall of square shape stacked structure 322 1 sides of Fig. 3 B in opening 306.The formation method of clearance wall 328 for example is to form earlier spacer material layer (not shown) on substrate 300, and overlaying memory device 302 and square shape stacked structure 322 then carry out etch back process to the spacer material layer and form.
Afterwards, form doped region 330 in the substrate 300 that the clearance wall 328 in opening 306 is exposed, doped region 330 is in order to as the drain region.The formation method of doped region 330 for example is an ion implantation.
In the formed nonvolatile memory of the foregoing description, owing to be the square shape as the square shape stacked structure 322 of selecting grid structure, the process margin in the time of therefore can making formation contact hole in the subsequent technique improves effectively.
In addition,, therefore can isolate the contact hole that forms in square shape stacked structure 322 and the subsequent technique, avoid producing the situation of short circuit at the clearance wall 328 that a side of square shape stacked structure 322 forms.
In sum, the present invention has following advantage at least:
1. utilizing the nonvolatile memory of nonvolatile memory manufacturing process made of the present invention, is square shape stacked structure owing to select grid structure, the process margin in the time of therefore can increasing follow-up formation contact hole significantly.
2. in utilizing nonvolatile memory manufacturing process of the present invention, can form clearance wall, therefore can avoid selecting formed contact hole generation short circuit in grid structure (square shape stacked structure) and the subsequent technique in a side of square shape stacked structure.
3. nonvolatile memory manufacturing process of the present invention can utilize packed layer as mask layer when forming square shape stacked structure, can simplify technology and reduce manufacturing cost.
Though the present invention discloses as above with preferred embodiment; yet it is not in order to qualification the present invention, any those skilled in the art, without departing from the spirit and scope of the present invention; can carry out a little change and modification to it, so protection scope of the present invention is with being as the criterion that claim was defined.
Claims (20)
1. the manufacture method of a nonvolatile memory comprises:
Substrate is provided, has been formed with a plurality of storage arrangements on this substrate, have first opening, and each first opening is between adjacent two storage arrangements in a side of each storage arrangement;
Form first dielectric layer at this first opening sidewalls and bottom;
Form square shape stacked structure respectively on this first dielectric layer of each first opening both sides sidewall, the block stacked structure of each side from bottom to top comprises conductor layer and packed layer;
In each first opening, form clearance wall on the sidewall of block stacked structure one side of each side; And
Form first doped region in this substrate that this clearance wall exposed in each first opening.
2. the manufacture method of nonvolatile memory as claimed in claim 1, the formation method of this square shape stacked structure wherein comprises:
On this substrate, form this conformal first dielectric layer and cover this storage arrangement;
On this first dielectric layer, form this conformal conductor layer;
Form second dielectric layer on this conductor layer, this second dielectric layer fills up this first opening;
Remove this second dielectric layer of part, this conductor layer of part and this first dielectric layer of part, to expose this storage arrangement;
Remove this conductor layer of part that is positioned on each first opening both sides sidewall, and between each storage arrangement and this second dielectric layer, respectively form second opening;
In this second opening, form this packed layer that fills up this second opening;
Remove second dielectric layer that is arranged in this first opening, and expose this conductor layer of part; And
Remove this conductor layer that is exposed.
3. the manufacture method of nonvolatile memory as claimed in claim 2 wherein forms the method for this packed layer that fills up this second opening in this second opening, comprising:
Form encapsulant layer on this substrate, this encapsulant layer fills up this second opening; And
Remove this second opening this encapsulant layer in addition.
4. the manufacture method of nonvolatile memory as claimed in claim 3, wherein the method that removes of this encapsulant layer beyond this second opening is chemical mechanical milling method or etch-back method.
5. the manufacture method of nonvolatile memory as claimed in claim 1, wherein the material of this packed layer comprises metal.
6. the manufacture method of nonvolatile memory as claimed in claim 1, wherein the material of this packed layer comprises silica.
7. the manufacture method of nonvolatile memory as claimed in claim 1, the formation method of this clearance wall wherein comprises:
On this substrate, form the spacer material layer, cover this storage arrangement and this square shape stacked structure; And
This spacer material layer is carried out etch back process.
8. the manufacture method of nonvolatile memory as claimed in claim 1, wherein each memory device is changed to stacked gate architectures, and each stacked gate architectures from bottom to top comprises wears dielectric layer and control grid between dielectric layer, floating grid, grid then.
9. the manufacture method of nonvolatile memory as claimed in claim 8, wherein each stacked gate architectures also comprises cap layer, is configured on this control grid.
10. the manufacture method of nonvolatile memory as claimed in claim 1, wherein the opposite side at each storage arrangement has the 3rd opening, each the 3rd opening is between adjacent two storage arrangements, and the width of the 3rd opening is less than the width of this first opening.
11. the manufacture method of nonvolatile memory as claimed in claim 10 also is included in this substrate of the 3rd opening below and forms second doped region.
12. the manufacture method of a nonvolatile memory comprises:
Substrate is provided, has been formed with a plurality of storage arrangements that are disposed at respectively in a plurality of grooves in this substrate, this storage arrangement protrudes in this substrate surface, and has first opening between adjacent two these storage arrangements;
Form first dielectric layer at this first opening sidewalls and bottom;
Form square shape stacked structure respectively on this first dielectric layer of each first opening both sides sidewall, the block stacked structure of each side from bottom to top comprises conductor layer and packed layer;
In each first opening, form clearance wall on the sidewall of block stacked structure one side of each side; And
Form first doped region in this substrate that this clearance wall exposed in each first opening.
13. the manufacture method of nonvolatile memory as claimed in claim 12, the formation method of this square shape stacked structure wherein comprises:
On this substrate, form this conformal first dielectric layer and cover this storage arrangement;
On this first dielectric layer, form this conformal conductor layer;
Form second dielectric layer on this conductor layer, this second dielectric layer fills up this first opening;
Remove this second dielectric layer of part, this conductor layer of part and this first dielectric layer of part, to expose this storage arrangement;
Remove this conductor layer of part that is positioned on each first opening both sides sidewall, and between each storage arrangement and this second dielectric layer, respectively form second opening;
In this second opening, form this packed layer that fills up this second opening;
Remove second dielectric layer that is arranged in this first opening, and expose this conductor layer of part; And
Remove this conductor layer that is exposed.
14. the manufacture method of nonvolatile memory as claimed in claim 13 wherein forms the method for this packed layer fill up this second opening in this second opening, comprising:
Form encapsulant layer on this substrate, this encapsulant layer fills up this second opening; And
Remove this second opening this encapsulant layer in addition.
15. the manufacture method of nonvolatile memory as claimed in claim 14, wherein the method that removes of this encapsulant layer beyond this second opening is chemical mechanical milling method or etch-back method.
16. the manufacture method of nonvolatile memory as claimed in claim 12, wherein the material of this packed layer comprises metal.
17. the manufacture method of nonvolatile memory as claimed in claim 12, wherein the material of this packed layer comprises silica.
18. the manufacture method of nonvolatile memory as claimed in claim 12, the formation method of this clearance wall wherein comprises:
On this substrate, form the spacer material layer, cover this storage arrangement and this square shape stacked structure; And
This spacer material layer is carried out etch back process.
19. the manufacture method of nonvolatile memory as claimed in claim 12, wherein each memory device is changed to the plough groove type structure, and each plough groove type structure comprises:
Second doped region is configured in this substrate of this channel bottom;
The 3rd dielectric layer is configured on this trenched side-wall and the bottom;
Two floating grids are configured in this groove two side respectively, and are positioned on the 3rd dielectric layer;
The column source electrode line is configured in this groove and is connected to this second doped region, and the top of this column source electrode line is higher than the surface of this substrate; With
The 4th dielectric layer is configured in this groove, and between this floating grid and this column source electrode line.
20. the manufacture method of nonvolatile memory as claimed in claim 12, wherein each plough groove type structure also comprises cap layer, is configured on this column source electrode line.
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| Application Number | Priority Date | Filing Date | Title |
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| CNA2006101263419A CN101136374A (en) | 2006-08-30 | 2006-08-30 | Process for manufacturing nonvolatile semiconductor memory |
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| CNA2006101263419A CN101136374A (en) | 2006-08-30 | 2006-08-30 | Process for manufacturing nonvolatile semiconductor memory |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106158872A (en) * | 2015-03-31 | 2016-11-23 | 物联记忆体科技股份有限公司 | Nonvolatile memory |
| CN106952925A (en) * | 2014-02-25 | 2017-07-14 | 北京芯盈速腾电子科技有限责任公司 | A kind of manufacture method of existing fringing field source electrode erasing nonvolatile memory unit |
-
2006
- 2006-08-30 CN CNA2006101263419A patent/CN101136374A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106952925A (en) * | 2014-02-25 | 2017-07-14 | 北京芯盈速腾电子科技有限责任公司 | A kind of manufacture method of existing fringing field source electrode erasing nonvolatile memory unit |
| CN106952925B (en) * | 2014-02-25 | 2020-03-17 | 北京芯盈速腾电子科技有限责任公司 | Method for manufacturing low electric field source electrode erasing non-volatile memory unit |
| CN106158872A (en) * | 2015-03-31 | 2016-11-23 | 物联记忆体科技股份有限公司 | Nonvolatile memory |
| CN106158872B (en) * | 2015-03-31 | 2019-06-11 | 物联记忆体科技股份有限公司 | Nonvolatile memory |
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