CN101135790A - Liquid crystal display driver with multiple row addressing - Google Patents
Liquid crystal display driver with multiple row addressing Download PDFInfo
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- CN101135790A CN101135790A CNA2007100868688A CN200710086868A CN101135790A CN 101135790 A CN101135790 A CN 101135790A CN A2007100868688 A CNA2007100868688 A CN A2007100868688A CN 200710086868 A CN200710086868 A CN 200710086868A CN 101135790 A CN101135790 A CN 101135790A
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Abstract
The LCD display driver comprises: a counter; a decoder; a display memory; a scrambler; a logic gate circuit; and a voltage selector. Said counter uses a block as a unit to make counting, and sends the counting result to the decoder; said block comprises n display rows, 1 is less than or equal to n < M; the M is total amount of the display rows; said decoder is used to decode the blocks, and according to the counting result, outputs the memory word pointer; said memory word pointer is used to control the output of the memory; said memory saves the color value of all display rows, and according to the indication from the memory word pointer, outputs the block color value to the scrambler; said scrambler calculates the color value, and sends it to the logic gate circuit; said voltage selector drives the row electrode and column electrode according to t he output result from the logic gate circuit.
Description
Technical field
The present invention relates to liquid crystal display and drive the field, particularly based on the LCD driver of multi-line addressing mode.
Background technology
Use the LCD driver of multi-line addressing mode to drive a plurality of column electrodes simultaneously according to predefined voltage, the voltage of row electrode is then selected from a plurality of voltages (generally being that the column electrode number that drives simultaneously adds) according to display gray scale, thereby reduces the response time that shows.
The structure of the LCD driver of traditional multi-line addressing mode comprises a linage-counter 1 as shown in Figure 1, line decoder 2, display-memory 3.This driver can drive 4 column electrodes simultaneously, and the row that each and RGB (Red is red, and Green is green, Blue indigo plant) are corresponding also comprise capable register 4, scrambler 5, XOR gate 6, totalizer 7, voltage mask register 8 and voltage selector 9.
In driver shown in Figure 1, linage-counter 1 adopts CLK to count, its result gives line decoder 2 and generates memory word pointer W[4n+m], this pointer and row are number corresponding and sequentially activate when each counting, this moment display-memory 3 just output correspondences gradation data words.
In display-memory shown in Figure 13, a horizontal line is represented a gradation data word, has stored the color-values of these all row of delegation in this gradation data word, and the color-values of each pixel is organized according to the mode of R/G/B gray scale.For example the R in display-memory 3 upper left corners (4n+0,0), G (4n+0,0), B (4n+0,0) have just represented the color-values of the 0th row the 0th row pixel of each viewing area (viewing area of per 4 behaviors); And R (4n+0,0), R (4n+1,0), R (4n+2,0), R (4n+3,0) have then represented in each viewing area the 0th gray-scale value that lists the R part of 0 to 4 row respectively; By that analogy, the numerical value of G and B part is also stored by similar mode.
As shown in Figure 1 and Figure 2, the video data in the territory, 4 line display range that is driven simultaneously is by clock CLK output from display-memory 3 sequentially, when clock CLK0 with R, G, the B data latching of the 0th row in row register 0, during clock CLK1 with R, G, the B data latching of first row in row register 1, during clock CLK2 with R, G, the B data latching of second row in row register 2, and the gray-scale value of the R of the third line, G, B, part just needn't latch by the row register again, will deliver to together in the corresponding scrambler 5 with first three rows R, G, B.CLK0, CLK1, CLK2 are the clocks of row register, and they help the row register to latch the data of display-memory, and the address of flip-flop storage adds 1 simultaneously.
Gradation conversion data among Fig. 1 are according to FRC (Frame Rate Control, the frame rate control) data by the time serial that modulation system generates, and represent the ratio that each pixel need be opened and close.Under the FRC modulating mode,,, reach other effect of demonstration particular gray level then according to a certain proportion of subframe of grey level gating by demonstration being divided into a plurality of subframes.
Scrambler 5 is given XOR gate 6 with the gray-scale value and the gradation conversion data of input through after the computing, another input of this XOR gate 6 is that corresponding column electrode is selected template, the result of XOR is through totalizer 7 additions then, use clock CLK3 addition and be latched in the voltage mask register 8.
It is column element in the capable selection matrix of a quadrature that column electrode is selected template, and the example of a capable selection matrix is provided below:
Column element in the matrix has been represented 4 column electrodes that driven simultaneously.Under the multi-line addressing mode, the column element in the capable selection matrix of the color data of each row on each column electrode that is driven simultaneously and correspondence carries out XOR, and the result through the arithmetic addition is used for selecting suitable column voltage to drive corresponding row electrode then.
Voltage mask register 8 usefulness clock CLK3 latch the result of totalizer 7 computings and get off to give voltage selector 9, and voltage selector 9 is selected corresponding level and driven the row electrode from some level then.The number that the selectable voltage number of voltage selector equals to drive simultaneously column electrode adds one.For example, drive the lcd driver of 4 column electrodes simultaneously, its exportable V0～V4 of column voltage selector switch is totally 5 kinds of voltages.
In traditional multi-line addressing driver, the color data of pixel reads out from display-memory 3 serially line by line, shows in order to drive 4 row simultaneously, just needs to use 3 capable registers 4 that the color data latching of preceding 3 circumstances in which people get things ready for a trip is lived at least.For the STN-LCD screen of one 128 row 256 looks (8bits), just need 128 (row) x8 (bits) x3 (OK)=3072 row registers so.In addition, the every column voltage selector switch of each color needs 3 bits to select voltage, just needs 3 (kind color) x128 (row) x3 (bits)=1152 register to latch voltage so altogether and selects data.Add above-mentioned 3072 capable registers, just need 3072+1152=4224 register altogether.
Inherit in the circuit design at CMOS, a register is made up of 20 transistors usually, and these registers will cause area of chip to enlarge markedly, thereby cause the increase of cost.In addition, because the clock frequency that register uses is four times that row is selected frequency, therefore also can cause the increase of chip power-consumption.
Summary of the invention
The technical problem to be solved in the present invention provides a kind of LCD driver of multi-line addressing, reduces chip area and power consumption, reduces cost.
In order to address the above problem, the invention provides a kind of LCD driver of multi-line addressing, comprise counting unit, decoding unit, demonstration storage unit, scrambler, logic gates and voltage selector, it is characterized in that,
Described counting unit is that unit counts with the piece, and the result that will count sends into decoding unit, and described is n display line, 1≤n＜M, and wherein M is total line number of display line;
Described decoding unit is that unit is deciphered with the piece, and according to the count results output memory word pointer of block count unit, described memory word pointer control shows the output of storage unit;
Described demonstration cell stores has the color-values of all display lines, is that unit output color-values is to scrambler with the piece according to the indication of memory word pointer;
Described scrambler is sent into described logic gates with the color-values of input through after the computing;
Described voltage selector drives column electrode and row electrode according to the output voltage as a result of described logic gates.
Further, described logic gates comprises XOR gate and totalizer, and described XOR gate receives the data of described scrambler output, and itself and column electrode selection template are carried out input summer as a result behind the XOR, input voltage selector switch after the totalizer addition.
Further, another of described scrambler is input as the gradation conversion data, described scrambler with the color-values of input and gradation conversion data through input logic gate circuit after the computing.
Further, described n is 4, and promptly each piece is four display lines.
Further, in described demonstration storage unit, each storage line stores the color-values of adjacent two all row of row, exports the color-values of 4 display lines simultaneously at every turn.
Further, the clock period of described voltage selector was delayed time in the clock period of described counting unit.
Adopt the method for the invention, needed clock frequency only be traditional multi-line addressing lcd driver clock frequency 1/4, the present invention also no longer needs row register and voltage mask register in addition, so can significantly reduce the power consumption of driver.
In addition, in the present invention, color data is stored according to color component, as shown in Figure 4, the R/G/B grey level of the corresponding four lines of every row pixel all is stored together respectively, they can directly be connected with corresponding scrambler, and needn't use a large amount of intersection lines, thereby have reduced area of chip effectively.
Description of drawings
Fig. 1 is the schematic diagram of traditional multi-line addressing lcd driver;
Fig. 2 is the sequential chart of traditional multi-line addressing lcd driver;
Fig. 3 is the schematic diagram of present embodiment multi-line addressing lcd driver;
Fig. 4 is the sequential chart of present embodiment multi-line addressing lcd driver.
Embodiment
The present invention is described in further detail below in conjunction with the drawings and specific embodiments.
Fig. 3 is the schematic diagram of present embodiment multi-line addressing lcd driver, comprises block counter 10, Block decoder 11, display-memory 12, scrambler 13, XOR gate 14, totalizer 15 and voltage selector 16.
Described block counter 10 is that unit counts with the piece, and counting adopts CLK to finish, and its result sends into Block decoder 11; In the present embodiment, each 4 display line as a piece, is about to each viewing area as a piece.
Described Block decoder 11 is that unit is deciphered with the piece, the output of output memory word pointer control display-memory;
The result of block counter 10 gives Block decoder 11 and generates memory word pointer W[n], the displaying block of storing in this pointer and the display-memory is corresponding and sequentially activate when counting at every turn.
Display-memory 12, the color-values that is used to store all pieces, according to the color-values of every of the indication of memory word pointer output to scrambler;
In display-memory shown in Figure 3 12, a horizontal line is represented a gradation data word, that is to say that each piece has comprised two gradation data words, stored the color-values of adjacent two all row of row in each gradation data word, each memory word pointer W[n] can both choose 2 gradation data words simultaneously, therefore each display-memory 12 can both be exported the data of 4 display lines simultaneously.In other words, the width of the gradation data word of the display-memory in the present embodiment 12 is 4 times of display-memory 3 of traditional lcd driver.Fig. 3 only provided a signal of display-memory, the total data of territory, 4 line display range the 0th row of only having drawn and the partial data of the 1st row, not the drawing of back.
In another embodiment, also can be arranged in the display-memory 12 color-values of all row in the storing one row only in each gradation data word, the color-values of perhaps storing all row in the adjacent multirow.
In display-memory 12, the color-values of each pixel is organized according to the mode of R, G, B gray scale, the color data of the capable j row of i in the four lines viewing area that C (4n+iJ) representative drives simultaneously.For example R (4n+0,0), G (4n+0,0), B (4n+0,0) represent R, the G of the 0th row the 0th row pixel, the gray-scale value of B respectively; And R (4n+0,0), R (4n+1,0), R (4n+2,0), R (4n+3,0) then represent the gray-scale value of the 0th～3 row the 0th row pixel R respectively.
Scrambler 13 is used for the color-values of input is sent into XOR gate 14 through after the computing;
Present embodiment equally also can support FRC (frame rate control) to show modulating mode, and scrambler 13 is given XOR gate 14 with the gray-scale value and the gradation conversion data of input through after the computing.
Another input of XOR gate 14 is that corresponding column electrode is selected template, and the result of XOR is through totalizer 15 additions then, and voltage selector 16 is selected the corresponding corresponding row electrode of driven according to the result of totalizer 15 from 5 voltages.The number that the exportable voltage number of row electrode equals to drive simultaneously column electrode adds one.
Fig. 4 has described the sequential of the lcd driver among Fig. 4, can see, therefore the color data in the territory, 4 line display range that is driven simultaneously outputs to from display-memory 12 in the corresponding scrambler 13 synchronously by clock CLK, does not need to design capable register 4 and color data kept in by voltage mask register 8.
When it should be noted that data, owing to will carry out the data assembly unit from display-memory 12 outputs, the variation of signal is a lot, therefore in order to guarantee to use stabilizing effective data, the clock that voltage selector uses should be delayed time CLK a period of time clock DELAY CLK as shown in Figure 4.
In the present embodiment, this driver can drive 4 column electrodes simultaneously.In other embodiments, change the clock period of CLK, (1≤n＜M is counted and deciphered to block counter and Block decoder to n piece, M is total line number of display line), the width of corresponding adjustment display-memory of while, during as n=6 or n=8, display-memory can be stored the more color data of multirow simultaneously, like this when output data, this display-memory can be selected the more color data output of multirow simultaneously, and lcd driver also can drive a plurality of column electrodes simultaneously, but the line number that drives is many more, the voltage progression that the row electrode need provide is also high more, and it is complicated that the logic of corresponding scrambler also can correspondingly become.
In sum, because the data in territory, 4 line display range are to export from display-memory 12 simultaneously among the present invention, because block counter adds 1 and all can drive 4 line data at every turn, so the clock period that needs is original 4 times, therefore needed clock frequency only be traditional multi-line addressing lcd driver in the accompanying drawing 1 clock frequency 1/4, the present invention also no longer needs row register and voltage mask register in addition, therefore can significantly reduce the power consumption of driver.
In addition, traditional multi-line addressing lcd driver among Fig. 1 uses pixel to store color data as storage unit, with 256 looks is example, each pixel adopts 8 bits to represent, represent R for the highest 3, represent G for ensuing 3, represent B for minimum 2, that is to say that the data of R/G/B color component are alternately deposited; But in the present invention, color data is but stored according to color component, as shown in Figure 4, the R/G/B grey level of the corresponding four lines of every row pixel all is stored together respectively, thus, they can directly be connected with corresponding scrambler, and needn't use a large amount of intersection lines, thereby have reduced area of chip effectively.
Claims (6)
1. the LCD driver of a multi-line addressing is characterized in that, comprises counting unit, decoding unit, demonstration storage unit, scrambler, logic gates and voltage selector,
Described counting unit is that unit counts with the piece, and the result that will count sends into decoding unit, and described is n display line, 1≤n＜M, and wherein M is total line number of display line;
Described decoding unit is that unit is deciphered with the piece, and according to the count results output memory word pointer of block count unit, described memory word pointer control shows the output of storage unit;
Described demonstration cell stores has the color-values of all display lines, is that unit output color-values is to scrambler with the piece according to the indication of memory word pointer;
Described scrambler is sent into described logic gates with the color-values of input through after the computing;
Described voltage selector drives column electrode and row electrode according to the output voltage as a result of described logic gates.
2. LCD driver as claimed in claim 1, it is characterized in that, described logic gates comprises XOR gate and totalizer, described XOR gate receives the data of described scrambler output, itself and column electrode are selected input summer as a result after template is carried out XOR, input voltage selector switch after the totalizer addition.
3. LCD driver as claimed in claim 1 is characterized in that another of described scrambler is input as the gradation conversion data, described scrambler with the color-values of input and gradation conversion data through input logic gate circuit after the computing.
4. LCD driver as claimed in claim 1 is characterized in that, described n is 4, and promptly each piece is four display lines.
5. LCD driver as claimed in claim 4 is characterized in that, in described demonstration storage unit, each storage line stores the color-values of adjacent two all row of row, exports the color-values of 4 display lines simultaneously at every turn.
6. LCD driver as claimed in claim 1 is characterized in that the clock period of described voltage selector was delayed time in the clock period of described counting unit.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2007100868688A CN100510869C (en) | 2007-03-21 | 2007-03-21 | Liquid crystal display driver with multiple row addressing |
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| Application Number | Priority Date | Filing Date | Title |
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| CNB2007100868688A CN100510869C (en) | 2007-03-21 | 2007-03-21 | Liquid crystal display driver with multiple row addressing |
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| CN101135790A true CN101135790A (en) | 2008-03-05 |
| CN100510869C CN100510869C (en) | 2009-07-08 |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102982768A (en) * | 2012-12-19 | 2013-03-20 | 四川虹视显示技术有限公司 | Partition method, addressing method and circuit of gate drive of AMOLED |
| CN110827741A (en) * | 2019-11-19 | 2020-02-21 | 京东方科技集团股份有限公司 | Output buffer circuit, drive circuit and display device |
-
2007
- 2007-03-21 CN CNB2007100868688A patent/CN100510869C/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102982768A (en) * | 2012-12-19 | 2013-03-20 | 四川虹视显示技术有限公司 | Partition method, addressing method and circuit of gate drive of AMOLED |
| CN110827741A (en) * | 2019-11-19 | 2020-02-21 | 京东方科技集团股份有限公司 | Output buffer circuit, drive circuit and display device |
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| Publication number | Publication date |
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| CN100510869C (en) | 2009-07-08 |
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Effective date of registration: 20151125 Address after: 518057 Nanshan District Guangdong high tech Industrial Park, South Road, science and technology, ZTE building, Ministry of Justice Patentee after: ZTE Corp. Patentee after: SANECHIPS TECHNOLOGY Co.,Ltd. Address before: 518057 Nanshan District high tech Industrial Park, Guangdong, South Road, science and technology, ZTE building, legal department Patentee before: ZTE Corp. |
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Granted publication date: 20090708 |