CN101131915A - Packaging structure with protection layer and packaging structure thereof - Google Patents
Packaging structure with protection layer and packaging structure thereof Download PDFInfo
- Publication number
- CN101131915A CN101131915A CNA2006101115741A CN200610111574A CN101131915A CN 101131915 A CN101131915 A CN 101131915A CN A2006101115741 A CNA2006101115741 A CN A2006101115741A CN 200610111574 A CN200610111574 A CN 200610111574A CN 101131915 A CN101131915 A CN 101131915A
- Authority
- CN
- China
- Prior art keywords
- protective layer
- chip
- wafer
- breach
- structure according
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
Landscapes
- Dicing (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
Abstract
The present invention discloses a package structure with protective layer and its packaging method. A protective layer is made on the surface of the wafer and the pre-cutting channel, in order to provide chip-to-chip protection in the process of wafer polishing, and could also avoid collision damage during the delivery process of the wafer and will increase the mechanical strength wafer chip which is useful for the follow-up package process.
Description
Technical field
The present invention relates to a kind of encapsulating structure and method for packing thereof, particularly a kind of encapsulating structure and method for packing thereof with protective layer.
Background technology
Disk can produce radial grinding indentation in the grinding and polishing process, these how much polishing scratch comprise countless minute cracks and scratch, often causes the residual stress place and causes the disk fracture.In addition, the minute crack that produces in the chip cutting process can produce along the chip edge place in the cutting, causes the increase of residual stress and the phenomenon that stress is concentrated.Unsuitable chip cutting program can cause structure defective to occur, and these chip defects also are the reasons that causes chip fracture and intensity to reduce.
For reducing the breakage problem of disk in encapsulation process, develop at present and grind manufacture process (Dicing Before Grinding after cutting, DBG), at first utilize the cutting blade fluting at chip back, penetraction depth is about last chip and finishes thickness more deeply, utilizes grinder that chip is ground to chip separately then.Its advantage is to grind manufacture process and is placed at last, all is to handle thicker chip so transmit in the whole manufacturing process chips, so can reduce because transmit the fragmentation rate that error is taken place.When though the DBG manufacture process can reduce direct cutting thinning disk cause the disk back side to burst apart situation, in the DBG manufacture process, still can't avoid fully cutting or problem that process of lapping chips edge bursts apart.
(it is the object of encapsulation process with the disk for Wafer-Level Packag, WLP) manufacture process, but not is editing objective as conventional package with one chip (Die) with regard to wafer level packaging.Because the WLP manufacture process does not need filler (Underfill) and substrate, can significantly save material cost and time.But the WLP bare chip pick and place with assembling manufacture process in, bare chip is subjected to brokenly easily hitting and produces slight crack, influences the reliability of follow-up assembling.
In addition, with regard to flush type encapsulation (Chip in Substrate Package, CiSP) manufacture process, it is a kind of encapsulation technology that does not need routing and cover chip lug, can directly in the support plate manufacture process, finish chip simultaneously and connect,, make package area dwindle significantly by burying in the assembly, and make unnecessary space can add more high functionality assemblies, for this reason to improve the packaging density of product integral body.But in interior process of burying chip, in bury in the picking and placeing of chip, the fixing and pressing process, be very easy to cause chip rupture.
Moreover the modular construction of current chip adopts advanced low-k materials to reduce the effect of the online middle time delay of multiple layer metal more.In order to reach low-dielectric matter, advanced low-k materials mostly is to be organized loosely, and the unfavorable structure of mechanical strength so the framework of the multiple layer metal lead that advanced low-k materials is formed is subject to the stress extruding and produces fracture, causes breaking and destroys the running of assembly.
Be the chip in the protection packaging process; in No. 6187615 patent case of the U.S., disclose a kind of wafer-level encapsulation method; provide strengthening layer with around the coating tin ball; and form protective layer in chip edge; wherein protective layer is formed in the surface of top, precut seam road, and therefore the not complete protected seam of chip edge coats after cutting is finished.
In addition; be the chip edge in the protection cutting; in U.S. Patent Publication No. the 2005/0110156th Al case, disclose a kind of protection chip edge mode of wafer level packaging; disk is bonded on the fiber strengthened synthetic resin substrate; cut disk again and form otch; form polymeric layer with the protection chip edge in incision, disk is cut off fully forming several chips again.Polymer as protective layer in this case only is formed at chip edge, and does not provide protective effect to the part beyond the chip edge.
Yet; above-mentioned chip easily causes damages such as chip fracture or advanced low-k materials be impaired in various encapsulation process; therefore a kind of comprehensive safeguard measure is provided; make chip in encapsulation process, be difficult for produce chip fracture and improve intensity, and the integrality of keeping advanced low-k materials is an important topic in fact.
Summary of the invention
Because the existing in prior technology problem the invention provides a kind of encapsulating structure and method for packing thereof with protective layer, filling or protective mulch are to strengthen the mechanical strength of chip edge and sidewall around chip.In addition, in disk surfaces and precut road, fill this protective layer, can be used as the resilient coating of mechanical stress, the chip and the chip protection of chip process of lapping are provided.
According to the wafer-level encapsulation method with protective layer of the present invention, at first, provide disk, this disk has first surface and second surface.Form several breach again in first surface, form then first protective layer on first surface with each breach in.Then, use so that first protective layer in each breach is exposed to second surface at second surface thinning disk.Cut each breach at last again to form several chips.Wherein, be arranged in first protective layer that first protective layer on the first surface connects each breach.And be positioned at the part area that first protective layer on the first surface covers first surface at least.In addition, the present invention also can form second protective layer with before forming several chips in each breach of cutting.Second protective layer is on second surface and connect first protective layer in each breach.Second protective layer covers the part area of second surface at least.
With the wafer-level package structure with protective layer that said method is made, it includes the disk and first protective layer.This disk has first surface, second surface and several breach, and first protective layer is arranged on the first surface and each breach, and first protective layer is exposed to second surface by each breach.Wherein, be arranged in first protective layer that first protective layer on the first surface connects each breach.And be positioned at the part area that first protective layer on the first surface covers first surface at least.In addition, the wafer-level package structure with protective layer also can comprise second protective layer, and it is positioned on the second surface, and second protective layer connects first protective layer by each breach.Second protective layer covers the part area of second surface at least.
In addition, the chip grade packaging structure that forms behind the cutting wafer-level package structure with protective layer, it includes the chip and first protective layer.This chip has first surface and second surface, and first protective layer is positioned on the first surface at least one edge with chip, and this edge connects first surface and second surface.First protective layer that wherein is positioned on the first surface connects first protective layer that is positioned at the edge.And first protective layer on the first surface covers the part area of first surface at least.In addition, the chip grade packaging structure with protective layer also can comprise second protective layer, and it is positioned on the second surface, and second protective layer connects first protective layer that is positioned at the edge.Second protective layer covers the part area of second surface at least.
Above-mentioned first protective layer and second protective layer are all high polymer layer.In addition, the first surface of disk also has several lead connection pads, can form several electrical channels on each lead connection pad, forms several tin balls again on each electrical channel.
The protective layer that utilizes the present invention to make can be filled in the precut road or cover chip edge and surface; the chip and the chip protection of wafer grinding process can be provided; and can avoid disk in the process of transporting, to be collided and damage, the mechanical strength that can increase disk and chip again is in order to follow-up canned program.
Below in execution mode, be described in detail detailed features of the present invention and advantage, its content is enough to make any related art techniques person of haveing the knack of to understand technology contents of the present invention and implements according to this, and according to the disclosed content of this specification, claim and graphic, any related art techniques person of haveing the knack of can understand purpose and the advantage that the present invention is correlated with easily.
Describe the present invention below in conjunction with the drawings and specific embodiments, but not as a limitation of the invention.
Description of drawings
Fig. 1 is the encapsulating structure figure of the first embodiment of the present invention;
Fig. 2 A to Fig. 2 G is the method for packing schematic flow sheet of the first embodiment of the present invention;
Fig. 3 A and Fig. 3 B are the schematic diagram of the second embodiment of the present invention;
Fig. 4 A and Fig. 4 B are the schematic diagram of the third embodiment of the present invention;
Fig. 5 A and Fig. 5 B are the schematic diagram of the fourth embodiment of the present invention;
Fig. 6 A and Fig. 6 B are the schematic diagram of the fifth embodiment of the present invention;
Fig. 7 A and Fig. 7 B are the schematic diagram of the sixth embodiment of the present invention; And
Fig. 8 A and Fig. 8 B are the schematic diagram of the seventh embodiment of the present invention.
Wherein, Reference numeral
10 substrate 10a breach
10b, 10c lead connection pad 10d passivation layer
11 protective layer 11a, first protective layer
11b second protective layer
The electrical channel of 20 carrier 30 as one kind
31 tin balls
101 first surfaces, 102 second surfaces
103 edges
Embodiment
For making purpose of the present invention, structure, feature and function thereof there are further understanding, cooperate embodiment to be described in detail as follows now.Above about content of the present invention explanation and the explanation of following execution mode in order to demonstration with explain principle of the present invention, and provide patent claim of the present invention further to explain.
See also the encapsulating structure figure of Fig. 1 for the first embodiment of the present invention.As shown in FIG., this chip grade packaging structure includes a substrate 10 and a protective layer 11.Substrate 10 has a first surface 101 and a second surface 102, and protective layer 11 is positioned on several edges 103 of first surface 101 and substrate 10, and edge 103 connects first surfaces 101 and second surfaces 102.And the protective layer 11 on the first surface 101 covers the part area of first surface 101.Protective layer 11 of the present invention is made with high molecular polymer, but protective substrate 10 and to avoid it to break impaired also can be protected the contained advanced low-k materials of first surface 101 simultaneously.In addition, first surface 101 has several lead connection pads 10b.Lead connection pad 10b is that lead heavily distributes and is formed at the conductive region of first surface 101 after (redistribution).On each lead connection pad 10b, be formed with several electrical channels 30.And on each electrical channel 30, be formed with several tin balls 31.Therefore, the protective layer on the first surface 101 11 also provides the function of passivation layer (passivation 1ayer) simultaneously.In addition, tin ball 31 can provide the usefulness of canned programs such as follow-up chip bonding.
See also Fig. 2 A to Fig. 2 G to describe the method for packing of first embodiment in detail.Shown in Fig. 2 A, the substrate 10 of wafer level is provided earlier, it has first surface 101 and second surface 102.Substrate 10 is a silicon wafer, and first surface 101 has the wiring (not shown).Next shown in Fig. 2 B, form several breach 10a in first surface 101, the degree of depth of breach 10a slightly is deeper than the thickness that last chip is finished.Then shown in Fig. 2 C and Fig. 2 D, formation protective layer 11 on first surface 101 with each breach 10a in.Utilize modes such as deposition, printing or coating that high molecular polymer is covered on the first surface 101 earlier; and be filled among each breach 10a; and formation protective layer 11 (shown in Fig. 2 C); the crack of causing when cutting breach 10a that makes like this can be filled up by high molecular polymer, avoids the crack to continue to enlarge and the effect of realization protection chip in follow-up canned program.Then protective layer 11 is carried out an etch process, to expose several lead connection pads 10b (shown in Fig. 2 D) of first surface 101.Protective layer 11 patterns of Xing Chenging are the protective layer 11 that the protective layer 11 on the first surface 101 connects among the breach 10a at last, and protective layer 11 covers the area of first surface 101 except lead connection pad 10b.
Next shown in Fig. 2 E, the second surface 102 of thin substrate 10 is used so that the protective layer 11 among the breach 10a is exposed to second surface 102.Utilize the first surface 101 of carrier 20 absorption substrates 10 earlier, come thin substrate 10 by second surface 102 with grinding or etched mode again, the protective layer 11 after thinning is finished among the breach 10a just can be exposed to second surface 102.Because protective layer 11 has been filled up the crack that breach 10a produces when cutting, and covers partly first surface 101, the effect of strengthening chip surface and edge is provided, make in process of lapping substrate 10 be difficult for breaking impaired, also be difficult for the generation crack.
Remove carrier 20 after finishing the second surface 102 of thin substrate 10.Then shown in Fig. 2 F, form several electrical channels 30 on each lead connection pad 10b.In this enforcement profit, electrically channel 30 can be metallized multilayer film, utilizes methods such as evaporation or sputter to be formed on the lead connection pad 10b.Therefore, the protective layer 11 on the first surface 101 is also as the usefulness of passivation layer.Shown in Fig. 2 G, form several tin balls 31 on each electrical channel 30 then.Electrically forming soldering-tin layer in modes such as evaporation, plating or print processes on the channel 30 earlier, the step of process backflow is to grow up to spherical tin ball 31 again.Electrically channel 30 can strengthen and tin ball 31 and lead connection pad 10b between tackness, and can avoid generating Jie's metallic compound (intermetallic compound) of fragility.And tin ball 31 is the usefulness as follow-up chip package program.At last cut the substrate 10 of each breach 10a again, as shown in Figure 1 to form several chip-scale.
In first embodiment, have several lead connection pads 10b, electrically channel 30 and tin ball 31 on the chip-scale substrate 10 after the cutting, but the present invention is not limited to several, also can be have single lead connection pad 10b, electrically channel 30 and tin ball 31.In addition, the wafer-level package structure of first embodiment can be consulted Fig. 2 G to be described in detail as follows, and it includes wafer level substrate 10 and protective layer 11.Substrate 10 has first surface 101, second surface 102 and several breach 10a, and protective layer 11 is arranged on the first surface 101 and each breach 10a, and protective layer 11 is exposed to second surface 102 by each breach 10a.In addition, be arranged in the protective layer 11 of protective layer 11 each the breach 10a of connection on the first surface 101, and the protective layer on the first surface 101 11 covers the area of first surfaces 101 except lead connection pad 10b.In addition, the wafer-level package structure of first embodiment also comprises electrical channel 30, be positioned on each lead connection pad 10b, and tin ball 31, be positioned on each electrical channel 30.
In addition, the chip grade packaging structure of first embodiment can be applicable in the flush type package fabrication process, because of the coating of protective layer 11 can provide preferable anti-stressed, avoids imbedding in the manufacture process or during the deformation of encapsulation ectosome, stress causes the inside chip fracture.At this moment, flush type chip grade packaging structure of the present invention also includes a supporting body (not shown), with so that be coated with the chip 10 of protective layer 11 and be embedded in the supporting body, and has plain conductor that the signal of chip 10 is directed into outside the supporting body.
Then, see also Fig. 3 A and Fig. 3 B to describe the method for packing of the second embodiment of the present invention in detail.As shown in Figure 3A, provide the substrate 10 of wafer level earlier, it has first surface 101 and second surface 102.Afterwards, form several breach 10a in first surface 101, and form the first protective layer 11a on first surface 101 with each breach 10a in.The lasting effect that enlarges and reach the protection chip in crack can be avoided in the crack that the first protective layer 11a has caused when having filled up cutting breach 10a in follow-up canned program.Then, the etching first protective layer 11a is to expose several lead connection pads 10b of first surface 101.Next the second surface 102 of thin substrate 10 is so that the first protective layer 11a among the breach 10a is exposed to second surface 102.Because the first protective layer 11a has filled up the crack that breach 10a produces when cutting, and covers partly first surface 101, the effect of strengthening chip surface and edge is provided, make in process of lapping substrate 10 be difficult for breaking impaired, also be difficult for the generation crack.Above-mentioned step can be with reference to the method for narrating among first embodiment.
Then, form the second protective layer 11b on second surface 102, the second protective layer 11b connects the first protective layer 11a among each breach 10a.In present embodiment, the first protective layer 11a and the second protective layer 11b are all high polymer layer.The first protective layer 11a that form this moment and the pattern of the second protective layer 11b are that the first protective layer 11a on the first surface 101 is connected the first protective layer 11a among each breach 10a; and the first protective layer 11a on the first surface 101 covers the area of first surface 101 except lead connection pad 10b, and the second protective layer 11b covers second surface 102 fully.At last cut the substrate 10 of each breach 10a again, shown in Fig. 3 B to form several chip-scale.
The wafer-level package structure of second embodiment as shown in Figure 3A, includes wafer level substrate 10, the first protective layer 11a and the second protective layer 11b.The first protective layer 11a on the first surface 101 connects the first protective layer 11a among each breach 10a.And the first protective layer 11a on the first surface covers the area of first surface 101 except lead connection pad 10b.The second protective layer 11b is positioned on the second surface 102, and the second protective layer 11b connects the first protective layer 11a by each breach 10a, and the second protective layer 11b covers second surface 102 fully again.Therefore, fill up because chip structure can be strengthened in the cutting breach 10a and the slit of causing when grinding second surface 102 by the first protective layer 11a and the second protective layer 11b, avoid disk crack in the process of transporting to enlarge or because of collision impaired.In addition; the chip grade packaging structure that cutting forms behind the wafer-level package structure, shown in Fig. 3 B, the first protective layer 11a is positioned on the first surface 101 and edge 103; and the second protective layer 11b is positioned on the second surface 102, and the first protective layer 11a of the second protective layer 11b adjoining edge 103.The area of chip-scale substrate 10 except lead connection pad 10b all coated by the first protective layer 11a and the second protective layer 11b at this moment; under the minimum situation of substrate 10 thickness; when being subjected to the external force deflection; because of the coating of the first protective layer 11a and the second protective layer 11b can provide preferable anti-stressed, and avoid the crack to enlarge because of the external force deflection.Therefore, assembling chip grade packaging structure of the present invention in the pliability electronic module, in the time of making the deflection of pliability electronic module, chip grade packaging structure is deflection thereupon.
In addition, can form electrical channel again and tin ball (not shown) is used for follow-up canned program as first embodiment on the lead connection pad 10b among second embodiment, so the first protective layer 11a on the first surface 101 also provides the purposes of passivation layer.
In addition; the chip grade packaging structure of second embodiment can be applicable to the flush type encapsulation and makes in the journey; because of the coating of the first protective layer 11a and the second protective layer 11b can provide preferable anti-stressed, avoid imbedding in the manufacture process or during the deformation of encapsulation ectosome, stress causes inside chip to rupture.In addition; flush type chip grade packaging structure of the present invention also includes a supporting body (not shown); with so that be coated with the chip 10 of the first protective layer 11a and the second protective layer 11b and be embedded in the supporting body, and there is plain conductor that the signal of chip 10 is directed into outside the supporting body.
See also Fig. 4 A and Fig. 4 B with the explanation third embodiment of the present invention.Shown in Fig. 4 A, in the first surface 101 of wafer level substrate 10 and breach 10a, form the first protective layer 11a as aforesaid method, and on second surface 102, form the second protective layer 11b.In present embodiment; the second protective layer 11b only is formed on the breach 10a second surface 102 on every side; its formation method is to deposit and be coated with high polymer layer earlier on second surface 102; form the pattern of the second protective layer 11b again in modes such as etchings; also can directly print or the spray printing high polymer layer on second surface 102, form the pattern of the second protective layer 11b.At last cut the substrate 10 of each breach 10a again, shown in Fig. 4 B to form several chip-scale.The wafer-level package structure of the 3rd embodiment is shown in Fig. 4 A, and the first protective layer 11a on the first surface 101 connects the first protective layer 11a among each breach 10a.And the first protective layer 11a on the first surface covers the area of first surface 101 except lead connection pad 10b.The second protective layer 11b is positioned on the second surface 102, and the second protective layer 11b connects the first protective layer 11a by each breach 10a, and the second protective layer 11b only covers the second surface 102 around the breach 10a again.But this moment first protective layer 11a and second protective layer 11b fill up the gap 10a slit on every side; near and the slit of causing because of grinding second surface 102 the protection breach 10a; the face of so can keeping away causes the expansion in crack when substrate 10 is cut into chip by disk; strengthen chip edge, and avoid chip edge to damage because of cutting.In addition; the chip grade packaging structure that forms behind the cutting wafer-level package structure; shown in Fig. 4 B; in this embodiment; second surface 102 only has the second protective layer 11b in 103 places that keep to the side; not only can protect chip edge to avoid damage, also can be applicable on the high power assembly, make things convenient for second surface 102 to dispel the heat.In addition, can form electrical channel again and the tin ball is used for follow-up canned program as first embodiment on the lead connection pad 10b among the 3rd embodiment, so the first protective layer 11a on the first surface 101 also provides the purposes of passivation layer.The chip grade packaging structure with protective layer of the 3rd embodiment can be applicable in the flush type package fabrication process.
See also Fig. 5 A and Fig. 5 B with the explanation fourth embodiment of the present invention.Shown in Fig. 5 A, the first surface 101 of wafer level substrate 10 has several lead connection pad 10c and several passivation layers 10d (its quantity is in this purposes as an illustration only, and the present invention is not as limit).11 of protective layers are formed among the breach 10a and first surface 101 around the breach 10a, because first surface 101 has had passivation layer 10d, 11 of protective layers need to cover around the breach 10a so that the protection purposes to be provided.In addition, cutting substrate 10 forms chip with disk, shown in Fig. 5 B, chip-scale substrate 10 have only edge 103 with its near first surface 101 on matcoveredn 11, can fill up the slit at edge 103, strengthen chip edge to avoid damage.Can utilize the pattern of little shadow manufacture process design protection layer 11 in this embodiment earlier, on desired location, be coated with high molecular polymer again.In this embodiment, only protective layer 11 need be formed at around the breach 10a, the method is integrated in original manufacture process, will not influence substrate 10 original circuit and distribute.In addition, can form electrical channel again and the tin ball is used for follow-up canned program as first embodiment on the lead connection pad 10c among the 4th embodiment.The chip grade packaging structure with protective layer of the 4th embodiment can be applicable in the flush type package fabrication process.
See also Fig. 6 A and Fig. 6 B with the explanation fifth embodiment of the present invention.As shown in Figure 6A, the first surface 101 of wafer level substrate 10 has several lead connection pad 10c and several passivation layers 10d.The first protective layer 11a only is formed among the breach 10a and first surface 101 around the breach 10a, because first surface 101 has had passivation layer 10d, 11 of protective layers need to cover around the breach 10a so that the protection purposes to be provided.The second protective layer 11b covers second surface 102 fully, and connects the first protective layer 11a by breach 10a.Under the minimum situation of substrate 10 thickness, when being subjected to the external force deflection,, and avoid the crack to enlarge because of the external force deflection because of the coating of the first protective layer 11a and the second protective layer 11b can provide preferable anti-stressed.Therefore, assembling chip grade packaging structure of the present invention in the pliability electronic module shown in Fig. 6 B, in the time of making the deflection of pliability electronic module, chip grade packaging structure is deflection thereupon.In addition, in the flush type package fabrication process,, avoid imbedding in the manufacture process or during the deformation of encapsulation ectosome, stress causes the inside chip fracture because of the coating of the first protective layer 11a and the second protective layer 11b can provide preferable anti-stressed.The first protective layer 11a is formed at around the breach 10a, does not then influence substrate 10 original circuit and distribute.In addition, can form electrical channel again and tin ball (not shown) is used for follow-up canned program as first embodiment on the lead connection pad 10c among the 5th embodiment.
See also Fig. 7 A and Fig. 7 B with the explanation sixth embodiment of the present invention.Shown in Fig. 7 A, the first surface 101 of wafer level substrate 10 has several lead connection pad 10c and several passivation layers 10d.The first protective layer 11a only is formed among the breach 10a and first surface 101 around the breach 10a, because first surface 101 has had passivation layer 10d, 11 of protective layers need to cover around the breach 10a so that the protection purposes to be provided.The second protective layer 11b only covers the second surface 102 around the breach 10a.But this moment first protective layer 11a and second protective layer 11b fill up the gap 10a slit on every side; near and the slit of causing because of grinding second surface 102 the protection breach 10a; the face of so can keeping away causes the expansion in crack when substrate 10 is cut into chip by disk; strengthen chip edge, and avoid chip edge to damage because of cutting.In addition, shown in Fig. 7 B, second surface 102 only has the second protective layer 11b in 103 places that keep to the side, and not only can protect chip edge to avoid damage, also can be applicable on the high power assembly, makes things convenient for second surface 102 to dispel the heat.The first protective layer 11a is formed at around the breach 10a, does not then influence substrate 10 original circuit and distribute.In addition, can form electrical channel again and the tin ball is used for follow-up canned program as first embodiment on the lead connection pad 10c among the 6th embodiment.The chip grade packaging structure with protective layer of the 6th embodiment can be applicable in the flush type package fabrication process.
See also Fig. 8 A and Fig. 8 B with the explanation seventh embodiment of the present invention.Shown in Fig. 8 A; the maximum difference of present embodiment and above embodiment is the not coating first protective layer 11a on first surface 101 of present embodiment; that is after the first surface 101 of wafer level substrate 10 forms several breach 10a (shown in 2B figure); utilize the first surface 101 of carrier 20 absorption substrates 10 earlier, come thin substrate 10 by second surface 102 with grinding or etched mode again.Shown in Fig. 8 B, when grind or etching second surface 102 when several breach 10a is exposed to it outside, the second protective layer 11b is coated on the second surface 102 also filling fully in several breach.So, the second protective layer 11b of present embodiment can fill up crack that breach 10a produced when cutting and second surface 102 in grind or etching process in the defective that caused.Certainly, the wafer-level package structure of present embodiment can be applicable in the flush type package fabrication process as the foregoing description, also can cut breach 10a and forms chip grade packaging structure, and the step of repetition is promptly no longer added to give unnecessary details in this.
In sum, encapsulating structure and the method for packing thereof with protective layer of the present invention can be at the protective layer that chip is filled on every side or overlie polymer forms, to strengthen the mechanical strength of chip edge and sidewall.In addition, filled polymer can provide the chip and the chip protection of chip process of lapping to form protective layer in precut road.When this protective layer makes the stressed deflection of the chip after the thinning, have preferable anti-stressed.Moreover filling or overlie polymer can make chip obtain preferable protection in flush type encapsulation (CiSP) to form protective layer around chip.In addition, assembling chip grade packaging structure of the present invention on the substrate of pliability electronic module, in the time of can making the deflection of pliability electronic module, the deflection thereupon of the chip after the thinning.According to the required purposes of chip, can form different protective layer patterns, so that optimal protected mode to be provided.
Certainly; the present invention also can have other various embodiments; under the situation that does not deviate from spirit of the present invention and essence thereof; those of ordinary skill in the art work as can make various corresponding changes and distortion according to the present invention, but these corresponding changes and distortion all should belong to the protection range of the appended claim of the present invention.
Claims (36)
1. a wafer-level encapsulation method is characterized in that, comprising:
One disk is provided, and this disk has a first surface and a second surface;
Form at least one breach in this first surface;
Form one first protective layer on this first surface with this breach respectively in; And
This second surface of thinning is so that respectively this first protective layer in this breach is exposed to this second surface.
2. wafer-level encapsulation method according to claim 1 is characterized in that, also comprises:
The cutting respectively this breach to form at least one chip.
3. wafer-level encapsulation method according to claim 2 is characterized in that, also comprises:
Carry out a flush type package fabrication process with this chip respectively.
4. wafer-level encapsulation method according to claim 1 is characterized in that, also comprises:
Before the step of this second surface of thinning, this first protective layer is carried out an etch process, make this first protective layer form several electrical channels.
5. wafer-level encapsulation method according to claim 4 is characterized in that, also comprises:
With several tin ball solderings on this several electrical channel.
6. wafer-level encapsulation method according to claim 1 is characterized in that, this second surface of thinning is for grinding or the etching mode execution.
7. wafer-level encapsulation method according to claim 1 is characterized in that, this first protective layer is a high polymer layer.
8. wafer-level encapsulation method according to claim 1 is characterized in that, also comprises:
Form one second protective layer on this second surface, this second protective layer connects this first protective layer in this breach respectively.
9. wafer-level encapsulation method according to claim 8 is characterized in that, also comprises:
The cutting respectively this breach to form at least one chip.
10. wafer-level encapsulation method according to claim 9 is characterized in that, also comprises:
Carry out a flush type package fabrication process with this chip respectively.
11. wafer-level encapsulation method according to claim 1 is characterized in that, this second protective layer is a high polymer layer.
12. a wafer-level encapsulation method is characterized in that, comprising:
One disk is provided, and this disk has a first surface and a second surface;
Form at least one breach in this first surface;
Provide a carrier to adsorb this first surface;
This second surface of thinning is so that respectively this breach layer is exposed to this second surface; And
Form a protective layer on this second surface with this breach respectively in.
13. wafer-level encapsulation method according to claim 12 is characterized in that, also comprises:
The cutting respectively this breach to form at least one chip.
14. wafer-level encapsulation method according to claim 13 is characterized in that, also comprises:
Carry out a flush type package fabrication process with this chip respectively.
15. wafer-level encapsulation method according to claim 12 is characterized in that, this second surface of thinning is for grinding or the etching mode execution.
16. wafer-level encapsulation method according to claim 12 is characterized in that, this protective layer is a high polymer layer.
17. a wafer-level package structure is characterized in that, includes:
One disk, this disk have a first surface, a second surface and at least one breach; And
One first protective layer, this first protective layer are arranged on this first surface and this breach respectively, and this first protective layer is exposed to this second surface by this breach respectively.
18. wafer-level package structure according to claim 17 is characterized in that, this first protective layer that is arranged on this first surface connects respectively this first protective layer of this breach.
19. wafer-level package structure according to claim 17 is characterized in that, is positioned at the part area that this first protective layer on this first surface covers this first surface at least.
20. wafer-level package structure according to claim 17 is characterized in that, this first surface has at least one lead connection pad.
21. wafer-level package structure according to claim 20 is characterized in that, also comprises at least one electrical channel, is positioned at respectively on this lead connection pad.
22. wafer-level package structure according to claim 21 is characterized in that, also comprises at least one tin ball, is positioned at respectively on this electrical channel.
23. wafer-level package structure according to claim 17 is characterized in that, this first protective layer is a high polymer layer.
24. wafer-level package structure according to claim 17 is characterized in that, also comprises one second protective layer, be positioned on this second surface, and this second protective layer connects this first protective layer by this breach respectively.
25. wafer-level package structure according to claim 24 is characterized in that, this second protective layer covers the part area of this second surface at least.
26. wafer-level package structure according to claim 24 is characterized in that, this second protective layer is a high polymer layer.
27. a chip grade packaging structure is characterized in that, includes:
One chip, this chip have a first surface and a second surface; And
One first protective layer, this first protective layer are positioned at least one edge of this first surface and this chip, and this edge connects this first surface and this second surface.
28. chip grade packaging structure according to claim 27 is characterized in that, also comprises a supporting body, with so that to be coated with this of this first protective layer chip buried in this supporting body.
29. chip grade packaging structure according to claim 27 is characterized in that, this first surface has at least one lead connection pad.
30. chip grade packaging structure according to claim 29 is characterized in that, also comprises at least one electrical channel, is positioned on this lead connection pad.
31. chip grade packaging structure according to claim 30 is characterized in that, also comprises at least one tin ball, is positioned at respectively on this electrical channel.
32. chip grade packaging structure according to claim 27 is characterized in that, this first protective layer is a high polymer layer.
33. chip grade packaging structure according to claim 27 is characterized in that, also comprises one second protective layer, be positioned on this second surface of this chip, and this second protective layer connects this first protective layer that is positioned at this edge.
34. chip grade packaging structure according to claim 33 is characterized in that, also comprises a supporting body, with so that to be coated with this of this first protective layer and this second protective layer chip buried in this supporting body.
35. chip grade packaging structure according to claim 33 is characterized in that, this second protective layer covers the part area of this second surface at least.
36. chip grade packaging structure according to claim 33 is characterized in that, this second protective layer is a high polymer layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA2006101115741A CN101131915A (en) | 2006-08-23 | 2006-08-23 | Packaging structure with protection layer and packaging structure thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA2006101115741A CN101131915A (en) | 2006-08-23 | 2006-08-23 | Packaging structure with protection layer and packaging structure thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN101131915A true CN101131915A (en) | 2008-02-27 |
Family
ID=39129122
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNA2006101115741A Pending CN101131915A (en) | 2006-08-23 | 2006-08-23 | Packaging structure with protection layer and packaging structure thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN101131915A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102034721A (en) * | 2010-11-05 | 2011-04-27 | 南通富士通微电子股份有限公司 | Method for encapsulating chip |
| US8883627B2 (en) | 2010-11-05 | 2014-11-11 | Nantong Fujitsu Microelectronics Co., Ltd. | Method for chip packaging |
| CN105242491A (en) * | 2014-07-11 | 2016-01-13 | 株式会社迪思科 | Method for manufacturing exposure mask |
| CN108122789A (en) * | 2016-11-30 | 2018-06-05 | 先进科技新加坡有限公司 | The method for manufacturing wafer level semiconductor package |
-
2006
- 2006-08-23 CN CNA2006101115741A patent/CN101131915A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102034721A (en) * | 2010-11-05 | 2011-04-27 | 南通富士通微电子股份有限公司 | Method for encapsulating chip |
| US8883627B2 (en) | 2010-11-05 | 2014-11-11 | Nantong Fujitsu Microelectronics Co., Ltd. | Method for chip packaging |
| US9362173B2 (en) | 2010-11-05 | 2016-06-07 | Nantong Fujitsu Microelectronics Co., Ltd. | Method for chip package |
| CN105242491A (en) * | 2014-07-11 | 2016-01-13 | 株式会社迪思科 | Method for manufacturing exposure mask |
| CN108122789A (en) * | 2016-11-30 | 2018-06-05 | 先进科技新加坡有限公司 | The method for manufacturing wafer level semiconductor package |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7727875B2 (en) | Grooving bumped wafer pre-underfill system | |
| KR100594669B1 (en) | Manufacturing method of semiconductor device, semiconductor device, circuit substrate and electronic equipment | |
| US20170098628A1 (en) | Semiconductor package structure and method for forming the same | |
| EP2291858B1 (en) | Packaged semiconductor product and method for manufacture thereof | |
| CN104409422A (en) | Low-thickness and low-cost chip size package with cavity | |
| US10229870B2 (en) | Packaged semiconductor device with tensile stress and method of making a packaged semiconductor device with tensile stress | |
| JP2002368160A (en) | Wafer level package and manufacturing method therefor | |
| CN104538318A (en) | Fan-out wafer level chip packaging method | |
| CN108511401A (en) | Packaging structure and packaging method of semiconductor chip | |
| US8785297B2 (en) | Method for encapsulating electronic components on a wafer | |
| CN101131915A (en) | Packaging structure with protection layer and packaging structure thereof | |
| CN105304585A (en) | Chip packaging structure with insulation protection on side wall and back surface and method | |
| US20080014679A1 (en) | Packaging structure with protective layers and packaging method thereof | |
| CN107078068A (en) | The method for packing and packaging body of wafer stage chip | |
| US20230245984A1 (en) | Protection of integrated circuits | |
| US8912653B2 (en) | Plasma treatment on semiconductor wafers | |
| JP2007123719A (en) | Semiconductor chip and its manufacturing method as well as semiconductor device | |
| CN104952720A (en) | Method for forming height-controllable exposure of electric-conducting poles from back | |
| KR20100107543A (en) | Method of enhancing the sticking strength of an embedded chip for embedded printed circuit board | |
| KR100817050B1 (en) | Method of manufacturing package of wafer level semiconductor chip | |
| US20120061830A1 (en) | Back side protective structure for a semiconductor package | |
| US7687923B2 (en) | Semiconductor device package having a back side protective scheme | |
| US20090039532A1 (en) | Semiconductor device package having a back side protective scheme | |
| CN104409429A (en) | Chip package structure with stress sacrifice structure and package method | |
| CN1414618A (en) | Crystal plate grade chip size encapsulating structure and its technology |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C02 | Deemed withdrawal of patent application after publication (patent law 2001) | ||
| WD01 | Invention patent application deemed withdrawn after publication |