CN101131806A - Charge pump clock generating circuit and method thereof - Google Patents
Charge pump clock generating circuit and method thereof Download PDFInfo
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- CN101131806A CN101131806A CNA2006101099289A CN200610109928A CN101131806A CN 101131806 A CN101131806 A CN 101131806A CN A2006101099289 A CNA2006101099289 A CN A2006101099289A CN 200610109928 A CN200610109928 A CN 200610109928A CN 101131806 A CN101131806 A CN 101131806A
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- charge pump
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- replacement signal
- pump clock
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Abstract
This invention relates to a kind of charge time pulse produce circuit and method, it includes coincidence counter, comparer, and the time pulse produce circuit. The coincidence counter receives one clock time pulse and a replacement signal, according to the accumulation counter of the clock time pulse, when the replacement signal can, reset the counter to the start value. The comparer receives counter, when the counter is larger than the preset value, outputs the replacement signal. The time pulse circuit receives display time pulse and the replacement signal, output charge time pulse, when the replacement can, transform the logic state of the charge time pulse, when the display time pulse change the first state to the second state, sets the charge time pulse to the first preset logic state.
Description
Technical field
The invention relates to a kind of clock generating circuit, and particularly relevant for a kind of charge pump clock generating circuit and method in display.
Background technology
In the circuit of display driving, for example the source electrode driver of LCD, gate pole driver all can need electric charge pump circuit, to produce non-specified supply voltage and the required voltage of driving circuit.
In general, charge pump need receive a time pulse signal so that the charge pump charging to be provided.With the source electrode driver is example, and it has two time pulse signals, and one is clock pulse (dot clock) signal, and another is a horizontal synchronization signal.General charge pump can't use a time pulse signal, because the some time pulse signal is used for showing, its frequency is at 10MHz～hundreds of MHz, for charge pump, power component in the charge pump can't operate in so high frequency, in addition, if this charge pump of design may operate in so high frequency, also cause the dynamic power consumption of this charge pump too high easily.
In general existing known charge pump clock generating circuit is directly to pass through frequency eliminator with the some time pulse signal, does to obtain behind the frequency elimination.Fig. 1 shown existing known charge pump clock signal and level, vertical, put clock pulse three's clock pulse figure.In this Fig. 1, on behalf of horizontal synchronization signal, Vsync, Hsync represent vertical synchronizing signal, DOTCLK representative point time pulse signal, CPCK1 and CPCK2 to represent the charge pump clock signal respectively.Charge pump clock signal CPCK1 or charge pump clock signal CPCK2 via frequency elimination in Fig. 1 clock pulse figure can't aim at horizontal synchronization signal.Appearing from clock pulse figure can be not influential to charge pump.Yet charge pump usually can produce noise in driving circuit, and also thereby can produce the noise of similar water ripple, this kind noise is charge pump clock signal and horizontal synchronization signal, vertical synchronizing signal is asynchronous causes on display.
Therefore, need a charge pump clock generation device, the noise that charge pump is produced, can be average drop in for example horizontal time pulse signal of each display synchronization signal.
Summary of the invention
Purpose of the present invention is to provide a kind of charge pump clock generating circuit exactly, and in order to the noise that charge pump produced, can be average drop in each display synchronization signal makes that further the demonstration of display is more perfect.
Another object of the present invention is to provide a kind of charge pump clock production method exactly, and in order to avoiding in the prior art, the noise that charge pump produced disturbs display frame, makes that further the demonstration of display is more perfect.
The present invention proposes a kind of charge pump clock generating circuit, and this circuit comprises first synchronous counter, first comparer and clock generating circuit.First synchronous counter receives some clock pulses and a replacement signal, in order to first count value that adds up according to a clock pulse, when the activation of replacement signal, count value is reset to the first initial value.First comparer receives first count value, output replacement signal, when first count value more than or equal to first preset value, activation replacement signal.Clock generating circuit receives and shows clock pulse and replacement signal, the output charge pump clock, when the activation of replacement signal, the logic state of conversion charge pump clock, when showing that clock pulse transfers second state to by first state, it is the first logic of propositions state that charge pump clock is set.
According to the described charge pump clock generating circuit of preferred embodiment of the present invention, above-mentioned synchronous counter more comprises the demonstration clock pulse that reception is above-mentioned.
According to the described charge pump clock generating circuit of preferred embodiment of the present invention, more comprise display cycle circuit for detecting and pulsewidth counting circuit.Display cycle circuit for detecting acceptance point clock pulse and show clock pulse, in order to the number of the pulse of calculating the some clock pulse during showing clock pulse as a pulse value.Pulsewidth counting circuit received pulse value, in order to pulse value divided by a frequency elimination value, calculate preset value.
According to the described charge pump clock generating circuit of preferred embodiment of the present invention, more comprise a counter initialization control circuit, receive this replacement signal, remove controlling value more than or equal to one, export a charge pump clock replacement signal when the number of times of replacement signal activation.
The present invention proposes a kind of charge pump clock production method, and the method comprises the following steps: to receive one and shows clock pulse; When showing the clock pulse activation, according to a clock pulse first count value that adds up; When first count value more than or equal to first preset value, first count value is reset to the first initial value, and the conversion charge pump clock logic state; When showing that clock pulse transfers second state to by first state, setting charge pump clock is the first logic of propositions state.
According to the described charge pump clock production method of preferred embodiment of the present invention, wherein work as first count value more than or equal to first preset value, first count value is reset to the first initial value, and the step of the logic state of conversion charge pump clock comprises: provide a replacement signal; When this first count value more than or equal to one first preset value, activation should the replacement signal; When this replacement signal activation, this count value is reset to a first initial value, and changes the logic state of this charge pump clock.
According to the described charge pump clock production method of preferred embodiment of the present invention, wherein this demonstration clock pulse is a horizontal synchronization signal, and in embodiments of the present invention, this first initial value, this second initial value are 0.
The present invention is because of adopting the numerical digit logical circuit, and charge pump clock and horizontal cycle signal is synchronous, therefore can be with the noise that charge pump produced, and average drops in each display synchronization signal, makes that further the demonstration of display is perfect more.
For above-mentioned and other purposes, feature and advantage of the present invention can be become apparent, preferred embodiment cited below particularly, and cooperate appended graphicly, be described in detail below.
Description of drawings
Fig. 1 shown existing known charge pump clock signal and level, vertical, put clock pulse three's clock pulse figure.
Fig. 2 is shown as the circuit block diagram of embodiment of the invention charge pump clock generating circuit.
Fig. 3 is shown as the sequential chart of the circuit box embodiment of Fig. 2 charge pump clock generating circuit of the present invention.
Fig. 4 is shown as the result that the circuit that utilizes embodiment of the invention Fig. 2 is implemented after via the change parameter.
Fig. 5 is shown as the further detailed circuit of implementing of embodiment of the invention Fig. 2 charge pump clock generating circuit.
Fig. 6 is shown as the process flow diagram of the charge pump clock production method of the embodiment of the invention.
Fig. 7 is shown as the process flow diagram of the charge pump clock production method of another embodiment of the present invention.
Hsync: horizontal synchronization signal, demonstration clock pulse
Vsync: vertical synchronizing signal
DOTCLK: some time pulse signal
CPCK1, CPCK2, CPCK, CPCK-1～CPCK-6: charge pump clock signal
201: display cycle circuit for detecting 202: the pulsewidth counting circuit
204: the first comparers of 203: the first synchronous counters
205: counter initialization control circuit 206: clock generating circuit
CV1: the first count value CV2: second count value
CPRST: charge pump clock replacement signal RST: replacement signal
PV: pulse value PREV1: first preset value
PREV2: 501: the second synchronous counters of second preset value
502: the second comparers 503: the first or lock
504: the second or lock 505:JK trigger
601～606,701～709: the step of the embodiment of the invention
Embodiment
Reach technological means and the effect that predetermined goal of the invention is taked for further setting forth the present invention, below in conjunction with accompanying drawing and preferred embodiment, to charge pump clock generating circuit and its embodiment of method, structure, method, step, feature and the effect thereof that foundation the present invention proposes, describe in detail as after.
Because in the prior art, the clock pulse of charge pump causes the flaw of display on showing with showing the asynchronous meeting of clock pulse, therefore the present invention proposes charge pump clock generating circuit, can be with the noise that charge pump produced, average drops in each demonstration time pulse signal, makes that further the demonstration of display is perfect more.Below just to scheme to cooperate explanatory note.
Fig. 2 is shown as the circuit block diagram of embodiment of the invention charge pump clock generating circuit.This circuit comprises display cycle circuit for detecting 201, pulsewidth counting circuit 202, first synchronous counter 203, first comparer 204, counter initialization control circuit 205 and clock generating circuit 206.
First synchronous counter 203 receives charge pump clock replacement signal CPRST, demonstration clock pulse Hsync (is the embodiment that shows clock pulse with the horizontal synchronization clock pulse at this), some clock pulse DOTCLK and replacement signal RST, in order to the one first count value CV1 that adds up according to this clock pulse DOTCLK, when replacement signal RST activation, synchronous counter 203 is reset to a first initial value (at this embodiment, the first initial value with 0 as embodiment) with count value CV1.When charge pump clock replacement signal CPRST activation, the first count value CV1 is reset to the first initial value and stops to add up this first count value.Display cycle circuit for detecting 201 acceptance point clock pulse DOTCLK and show clock pulse Hsync, in order to the number of the pulse of calculating the some clock pulse DOTCLK during showing clock pulse Hsync as a pulse value PV.
Fig. 3 is shown as the sequential chart of the circuit embodiments of embodiment of the invention Fig. 2.Please also refer to Fig. 2 and Fig. 3, the pulse value PV that calculates in the horizontal synchronization clock pulse at this hypothesis display cycle circuit for detecting 201 is 4N+K, wherein N, K are natural number, and K is less than N, suppose that in addition frequency elimination value n is 4, therefore to calculate first preset value be N to pulsewidth counting circuit 202, and other second preset value is designed to 4-1=3.At first, synchronous counter 203 begins counting in the t0 time.When the first count value CV1 of synchronous counter 203 count down to N (t1, t3, t5), comparer 204 receives the first count value CV1 and the first preset value N, after two values are made comparisons, and activation replacement signal RST.Synchronous counter 203 receives the replacement signal RST of activation, just the first count value CV1 is returned 0 (t2, t4, t6).
When clock generating circuit 206 receives (t0) when showing that clock pulse Hsync transfers logic low potential to by logic high potential, clock generating circuit 206 is triggered by negative edge, and it is noble potential that charge pump clock CPCK just is set.When replacement signal RST activation (t2, t4, t6), clock generating circuit 206 is triggered by negative edge, just changes the logic state of charge pump clock CPCK.When replacement signal RST activation 3 times (t6), just be illustrated in and shown among the clock pulse Hsync, the control circuit of counter initialization at this moment 205 activation charge pump clock replacement signal CPRST through 3N some clock pulse DOTCLK pulse.When charge pump clock replacement signal CPRST activation, synchronous counter 203 is just kept the first count value CV1=0 of its output, and clock generating circuit 206 charge pump clock CPCK are set to logic low potential, up to receiving the next clock pulse Hsync that shows.
In this embodiment just as can be seen, because the embodiment of the invention is synchronous with charge pump clock and horizontal cycle signal, therefore can be with the noise that charge pump produced, average drops in each demonstration clock pulse (for example level), make each horizontal noise bright secretly all identical, can make further that just the demonstration of display is perfect more.In addition, this embodiment for example be one and show among the clock pulse Hsync that 2 charge pump clock CPCK are arranged, yet know this operator with reference to embodiments of the invention after, should know by inference, if will be as producing 0,1,2,3,4,8 or the like among Fig. 4 ... individual charge pump clock CPCK-1～CPCK-6, can adjust design parameter (for example frequency elimination value, second preset value or the like) with in response to different demands.
Fig. 5 is shown as the further detailed circuit of implementing of embodiment of the invention Fig. 2.In this embodiment, further disclose the logical circuit of counter initialization control circuit 205 and clock generating circuit 206.Counter initialization control circuit 205 comprises second synchronous counter 501 and second comparer 502.Second synchronous counter 501 receives replacement signal RST and charge pump clock replacement signal CPRST, according to the replacement signal RST one second count value CV2 that adds up, when charge pump clock replacement signal CPRST activation, count value CV2 is reset to one second initial value (for example 0).Second comparer, 502 count pick up value CV2.When count value CV2 more than or equal to the second preset value PREV2 (is 3 with the above embodiments), second comparer 502 is output charge pump clock replacement signal CPRST just.
Clock generating circuit comprises first or lock 503, second or lock 504 and JK flip-flop 505.First or lock 503 receive and show clock pulse Hsync and replacement signal RST.Second or lock 504 receive replacement signal RST and charge pump clock replacement signal CPRST.The J input end of JK flip-flop 505 couples first or the output terminal of lock 503.The K input end of JK flip-flop 505 couples second or the output terminal of lock 504.The Q output terminal output charge pump clock CPCK of JK flip-flop 505.
The foregoing description provides the embodiment of charge pump clock generating circuit, and a kind of charge pump clock production method below is provided, and Fig. 6 is shown as the process flow diagram of the charge pump clock production method of the embodiment of the invention.Please refer to shown in Figure 6ly, at first, receive one and show clock pulse, for example horizontal synchronization signal Hsync (step 601).When showing clock pulse Hsync activation, according to a clock pulse first count value (step 602) that adds up.Next judge that whether first count value is more than or equal to first preset value (step 603).If be judged as not, then get back to step 602 and continue counting; When being judged as when being, first count value is reset to the first initial value, for example be 0, and the logic state (step 604) of conversion charge pump clock.Next judge and show whether clock pulse transfers second state (step 605) to by first state.When being judged as when being, setting charge pump clock is the first logic of propositions state, and for example to set charge pump clock be logic low potential (step 606) to the foregoing description.
Fig. 7 is shown as the process flow diagram of the charge pump clock production method of another embodiment of the present invention.Please refer to shown in Figure 7, input level period signal (step 701) at first.Next according to a clock pulse one first count value (step 702) that adds up.Next step judges that whether first count value is more than or equal to first preset value (step 703).If be judged as not, then get back to step 702 and continue counting; When being judged as when being, first count value is reset to the first initial value, for example be 0, the logic state of conversion charge pump clock, and activation replacement signal RST (step 704).Next, the activation number of times record with replacement signal RST is second count value (step 705).
Next, judge that whether second count value is more than or equal to second preset value (step 706).When being judged as when being, first, second count value is reset to first, second initial value (for example being 0), and stops numeration (step 707).Next step is judged to show whether clock pulse Hsync transfers second state (step 708) to by first state.When being judged as when being, it is the first logic of propositions state (step 709) that charge pump clock CPCK is set, and gets back to step 702.
In sum, the present invention is because of adopting the numerical digit logical circuit, and charge pump clock and horizontal cycle signal is synchronous, therefore can be with the noise that charge pump produced, average drops in each display synchronization signal, makes that further the demonstration of display is perfect more.
The above, it only is preferred embodiment of the present invention, be not that the present invention is done any pro forma restriction, though the present invention discloses as above with preferred embodiment, yet be not in order to limit the present invention, any those skilled in the art, in not breaking away from the technical solution of the present invention scope, when the technology contents that can utilize above-mentioned announcement is made a little change or is modified to the equivalent embodiment of equivalent variations, in every case be not break away from the technical solution of the present invention content, according to technical spirit of the present invention to any simple modification that above embodiment did, equivalent variations and modification all still belong in the scope of technical solution of the present invention.
Claims (18)
1. charge pump clock generating circuit is characterized in that it comprises:
One first synchronous counter receives some clock pulses and a replacement signal, in order to one first count value that adds up according to this clock pulse, when this replacement signal activation, this count value is reset to a first initial value;
One first comparer receives this first count value, exports this replacement signal, when this first count value more than or equal to one first preset value, activation should the replacement signal; And
One clock generating circuit, receive one and show clock pulse and should the replacement signal, export a charge pump clock, when this replacement signal activation, change the logic state of this charge pump clock, when this demonstration clock pulse transferred one second state to by one first state, this charge pump clock was one first logic of propositions state.
2. charge pump clock generating circuit according to claim 1 is characterized in that wherein said first synchronous counter more comprises this demonstration clock pulse of reception.
3. charge pump clock generating circuit according to claim 1, it is characterized in that it more comprises a display cycle circuit for detecting, receive this clock pulse and this demonstration clock pulse, in order to the number of the pulse of calculating this clock pulse during this shows clock pulse as a pulse value.
4. charge pump clock generating circuit according to claim 3 is characterized in that it more comprises a pulsewidth counting circuit, receives this pulse value, in order to this pulse value divided by a frequency elimination value, calculate this first preset value.
5. charge pump clock generating circuit according to claim 1, it is characterized in that it more comprises a counter initialization control circuit, receive this replacement signal, export a charge pump clock replacement signal, when the number of times of this replacement signal activation more than or equal to one second preset value, this charge pump clock replacement signal of activation.
6. charge pump clock generating circuit according to claim 5, it is characterized in that wherein said first synchronous counter more comprises this charge pump clock replacement signal of reception, when this charge pump clock replacement signal activation, this first count value is reset to a first initial value and this first count value that stops to add up.
7. charge pump clock generating circuit according to claim 5, it is characterized in that wherein said clock generating circuit more comprises this charge pump clock replacement signal of reception, when this replacement signal activation, it is one second logic of propositions state that this charge pump clock is set, wherein this second logic of propositions state and this first logic of propositions state mutual exclusion.
8. charge pump clock generating circuit according to claim 5 is characterized in that wherein said counter initialization control circuit comprises:
One second synchronous counter receives this replacement signal and this charge pump clock replacement signal, in order to one second count value that adds up according to this replacement signal, when this charge pump clock replacement signal activation, this second count value is reset to one second initial value; And
One second comparer receives this count value, when this second count value more than or equal to this second preset value, export this charge pump clock replacement signal.
9. charge pump clock generating circuit according to claim 5 is characterized in that wherein said clock generating circuit comprises:
One first or lock, comprise first input end, second input end and output terminal, its first input end receives this demonstration clock pulse, and its second input end receives this replacement signal;
One second or lock, comprise first input end, second input end and output terminal, its first input end receives this replacement signal, and its second input end receives this charge pump clock replacement signal; And
One JK flip-flop comprises a J input end, a K input end and a Q output terminal, this J input end couple this first or the output terminal of lock, this K input end couple this second or the output terminal of lock, this Q output terminal is in order to export this charge pump clock.
10. charge pump clock generating circuit according to claim 1 is characterized in that wherein said demonstration clock pulse is a horizontal synchronization signal.
11. charge pump clock generating circuit according to claim 1 is characterized in that wherein said the first initial value is 0.
12. charge pump clock generating circuit according to claim 8 is characterized in that wherein said this second initial value is 0.
13. a charge pump clock production method is characterized in that it may further comprise the steps:
Receive one and show clock pulse;
When this shows clock pulse activation, according to some clock pulses one first count value that adds up;
When this first count value more than or equal to one first preset value, this first count value is reset to a first initial value, and changes the logic state of this charge pump clock; And
When this demonstration clock pulse transferred one second state to by one first state, setting this charge pump clock was one first logic of propositions state.
14. charge pump clock production method according to claim 13, it is characterized in that, wherein when this first count value more than or equal to one first preset value, this count value is reset to a first initial value, and the step of changing the logic state of this charge pump clock comprises:
One replacement signal is provided;
When this first count value more than or equal to one first preset value, activation should the replacement signal; And
When this replacement signal activation, this first count value is set at a first initial value, and changes the logic state of this charge pump clock.
15. charge pump clock production method according to claim 14 is characterized in that it more comprises:
Provide one second count value, in order to represent the activation number of times of this replacement signal; And
When this second count value more than or equal to one second preset value, setting this second count value is one second initial value, and to set this first count value be a first initial value, and stop to count this first, this second count value.
16. charge pump clock production method according to claim 13 is characterized in that wherein said demonstration clock pulse is a horizontal synchronization signal.
17. charge pump clock production method according to claim 13 is characterized in that wherein said the first initial value is 0.
18. charge pump clock production method according to claim 13 is characterized in that wherein said second initial value is 0.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2006101099289A CN100524443C (en) | 2006-08-24 | 2006-08-24 | Charge pump clock generating circuit and method thereof |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2006101099289A CN100524443C (en) | 2006-08-24 | 2006-08-24 | Charge pump clock generating circuit and method thereof |
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| CN101131806A true CN101131806A (en) | 2008-02-27 |
| CN100524443C CN100524443C (en) | 2009-08-05 |
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| CNB2006101099289A Expired - Fee Related CN100524443C (en) | 2006-08-24 | 2006-08-24 | Charge pump clock generating circuit and method thereof |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101888224B (en) * | 2009-05-12 | 2012-06-27 | 华映视讯（吴江）有限公司 | Generation method of control signal and device thereof |
| CN102708826A (en) * | 2012-06-01 | 2012-10-03 | 福州华映视讯有限公司 | Driving circuit for display panel |
| CN103856131A (en) * | 2012-12-06 | 2014-06-11 | 奕微科半导体科技股份有限公司 | voltage regulator control circuit for automobile generator |
| CN104076263B (en) * | 2013-03-28 | 2017-03-15 | 致茂电子(苏州)有限公司 | The measuring time value module of semiconductor ATE and method |
-
2006
- 2006-08-24 CN CNB2006101099289A patent/CN100524443C/en not_active Expired - Fee Related
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101888224B (en) * | 2009-05-12 | 2012-06-27 | 华映视讯（吴江）有限公司 | Generation method of control signal and device thereof |
| CN102708826A (en) * | 2012-06-01 | 2012-10-03 | 福州华映视讯有限公司 | Driving circuit for display panel |
| CN103856131A (en) * | 2012-12-06 | 2014-06-11 | 奕微科半导体科技股份有限公司 | voltage regulator control circuit for automobile generator |
| CN103856131B (en) * | 2012-12-06 | 2016-06-22 | 奕微科半导体科技股份有限公司 | voltage regulator control circuit for automobile generator |
| CN104076263B (en) * | 2013-03-28 | 2017-03-15 | 致茂电子(苏州)有限公司 | The measuring time value module of semiconductor ATE and method |
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| Publication number | Publication date |
|---|---|
| CN100524443C (en) | 2009-08-05 |
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