CN101123272A - A silicon base bar single electronic transistor and its making method - Google Patents

A silicon base bar single electronic transistor and its making method Download PDF

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Publication number
CN101123272A
CN101123272A CNA2006101095610A CN200610109561A CN101123272A CN 101123272 A CN101123272 A CN 101123272A CN A2006101095610 A CNA2006101095610 A CN A2006101095610A CN 200610109561 A CN200610109561 A CN 200610109561A CN 101123272 A CN101123272 A CN 101123272A
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source
silicon base
silicon
base bar
electronic transistor
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CN100533768C (en
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龙世兵
王琴
李志刚
刘明
陈宝钦
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Semiconductor Manufacturing International Shanghai Corp
Institute of Microelectronics of CAS
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Institute of Microelectronics of CAS
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Abstract

The invention discloses a silicon side grid single-electron transistor, which comprises a coulomb island, a source and a drain positioned on the two sides of the coulomb island, a tunnel knot connecting the coulomb island and the source, a tunnel knot connecting the coulomb island and the drain, a grid medium and a side grid positioned on the sides of the coulomb island, a source electrode deposited on the source, a drain electrode deposited on the drain, and a side grid electrode deposited on the side grid. The invention at the same time discloses a manufacturing method of the silicon side grid single-electron transistor. Through the invention, the reliability of the single-electron transistor and the compatibility of the traditional CMOS technique are improved, the manufacturing technique is simplified, the manufacturing cost is reduced, and the manufacturing efficiency is improved.

Description

A kind of silicon base bar single electronic transistor and preparation method thereof
Technical field
The present invention relates to nano electron device and technical field of nano-processing, relate in particular to a kind of silicon base bar single electronic transistor and preparation method thereof.
Background technology
With complementary Metal-oxide-semicondutor (CMOS) device is that the integrated circuit of mainstream technology is being followed Moore's Law always and developed rapidly, has entered the 90nm technology node at integrated circuit in 2004.Along with characteristic size enters into nanoscale, traditional CMOS technology is faced with more and more serious challenge, therefore, becomes the focus of research based on the nano electron device of new principle.
Single-electronic transistor has that size is little, speed is fast, low in energy consumption, can be integrated on a large scale etc. advantage, and have very wide application prospect, as can be used to make single-electron memory, single electron logical circuit, current standard, resistance standard, temperature standard, hypersensitive electrometer, microwave or Infrared Detectors etc.Therefore, single-electronic transistor has become one of following important candidate device that substitutes MOS transistor.
Generally speaking, single-electronic transistor partly is made of dielectric substrate 101, source 102, leakage 103, tunnel junction 104, coulomb island 105, tunnel junction 106, gate medium 107, grid 108 etc., as shown in Figure 1, Fig. 1 is the structural representation of present conventional single-electronic transistor.The core of single-electronic transistor is coulomb island 105, tunnel junction 104 and tunnel junction 106.Coulomb island 105 is made of atomic little metal or semiconductor-quantum-point particle, it on a certain direction respectively the tunnel junction 104 by both sides be connected with source 102, leakage 103 with 106.Source 102 and leakage 103 are positioned at the both sides on coulomb island 105.Tunnel junction 104 and 106 generally is made of insulating barrier, potential barrier of heterogenous junction and the potential field that caused by interfacial state or applied voltage etc.Thereby grid play the effect of the electron number in the electrochemical potential control island of regulating the island.Source 102, leakage 103, grid 108 generally are made of metal or doped semiconductor, are connected with the outside.
The operate as normal of wanting single-electronic transistor must satisfy the charging on coulomb island can be greater than the condition of heat energy, i.e. e 2/ 2C＞＞k BT, wherein k BTherefore be Boltzmann constant, must improve the work temperature of single-electronic transistor by the capacitor C that reduces the island, so just must by dwindle as far as possible the tunnel junction area particularly a coulomb island size realize.Therefore, how obtaining undersized coulomb structure is that " tunnel junction-coulomb island-tunnel junction " structure is the key of making high temperature even normal temperature single-electron device.
At present, when making the coulomb structure of single-electronic transistor, adopt carbon nano-tube, metal nanoparticle, nano metal oxide wire, quantum wire material or quanta point material etc. mostly.For example, application number is that 02244235.9 or 02157972.5 Chinese patent discloses a kind of method that adopts carbon nano-tube to make coulomb structure, application number is that 03131772.3 or 00229474.5 Chinese patent discloses a kind of method that adopts metal nanoparticle to make coulomb structure, application number is that 02157972.5 Chinese patent discloses a kind of method that adopts nano metal oxide wire to make coulomb structure, application number is that the Chinese patent of 01200510.X or 03142350.7 discloses a kind of method that adopts quantum wire material coulomb structure, and application number is that 01200511.8 Chinese patent discloses a kind of method that adopts quanta point material to make coulomb structure.
Utilize the single-electronic transistor of the coulomb structure making of above-mentioned making generally can both obtain higher working temperature, but utilize above-mentioned coulomb structure to make single-electronic transistor, have all generally that complex manufacturing technology, cost of manufacture height, make efficiency are low, the feasibility difference and with the shortcoming of traditional cmos process poor compatibility.
Summary of the invention
(1) technical problem that will solve
At the deficiency that above-mentioned prior art exists, one object of the present invention is to provide a kind of silicon base bar single electronic transistor, with the reliability that improves single-electronic transistor and with the compatibility of traditional cmos process.
Another object of the present invention is to provide a kind of manufacture method of silicon base bar single electronic transistor, to simplify manufacture craft, reduce cost of manufacture and to improve make efficiency.
(2) technical scheme
For achieving the above object, technical scheme of the present invention is achieved in that
A kind of silicon base bar single electronic transistor, this single-electronic transistor comprises: coulomb island, be positioned at coulomb source of both sides, island and leakage, be connected coulomb island and source tunnel junction, is connected coulomb island and leakage tunnel junction, be positioned at the side gate electrode that deposits on the drain electrode that deposits in the source electrode that deposits on coulomb gate medium of side, island and side grid, the source, the leakage and the side grid.
Described source, leakage, side grid, coulomb island, tunnel junction are made by the surface silicon of SOI substrate.
Described SOI substrate comprises:
Silicon base is used to support whole single-electronic transistor;
Oxygen buried layer is used to insulate and isolates the silicon base of single-electronic transistor and SOI substrate;
Surface silicon is used to make coulomb island, tunnel junction, source, leakage, the side grid of silicon base bar single electronic transistor.
The thickness of described SOI underlayer surface silicon is 30nm.
A kind of manufacture method of silicon base bar single electronic transistor, this manufacture method adopt electron beam lithography and figure to rely on method for oxidation, specifically may further comprise the steps:
A, the surface silicon of SOI substrate carried out ion injects and short annealing;
B, on the surface silicon of SOI substrate the spin coated electronic corrosion-resistant and before baking, adopt e-beam direct-writing exposure, developing and fixing formation source, leakage, nano wire, side gate figure in the electronic corrosion-resistant that applies;
C, the figure that will form in electronic corrosion-resistant are as mask, and the surface silicon of etching SOI substrate is also removed photoresist, formation source, leakage, nano wire, side gate figure in the surface silicon of SOI substrate;
D, the source to forming in the surface silicon, leakage, nano wire, side gate figure carry out figure and rely on oxidation, make the one dimension silicon nanowires change tunnel junction-coulomb island-tunnel junction structure into;
E, deposit SiO 2Gate dielectric membrane;
F, spin coated optics resist, to the optics resist of spin coated carry out preceding baking, lay photoetching mask plate exposure, counter-rotating baking, generally expose to the sun, development and photographic fixing, above source, leakage, grid, form contact hole graph;
The figure that G, utilization form in the optics resist corrodes SiO as mask 2Dielectric film;
H, on the source of exposing, leakage, grid and the optics resist do not removed evaporation one layer thickness less than the metal electrode material of optics resist thickness;
I, peel off the optics resist and go up the metal electrode material of evaporation side, carry out annealing in process, form electrode peeling off the remaining metal electrode material in back.
Described steps A comprises: the surface silicon to the SOI substrate is injected P 31+Ion, the injection energy is 30keV, implantation dosage is 1 * 10 15Cm -2, then at N 2Short annealing 10 seconds under 1000 ℃ of temperature in the atmosphere.
The spin coated electronic corrosion-resistant is for using sol evenning machine spin coated HSQ negativity negative electronic erosion-resisting agent on the surface silicon of SOI substrate described in the step B, and the spin coated rotating speed is 6000 rev/mins, and the spin coated time is 60 seconds;
Baking is baking before adopting hot plate under 150 ℃ 2 minutes before described in the step B;
E-beam direct-writing exposure described in the step B is that 50KeV, electronic beam current are that 200pA, exposure dose are 1000 to 2000 μ C/cm for adopting accelerating voltage 2Electron-beam lithography system, the HSQ negative electronic erosion-resisting agent is carried out e-beam direct-writing exposure;
Develop described in the step B for adopting the aqueous solution that contains 2.5% tetramethyl level ammonium hydroxide TMAH to develop 1 to 2 minute down at 40 to 50 ℃;
Photographic fixing described in the step B is for adopting deionized water photographic fixing at room temperature 1 minute;
The length of the bargraphs of one dimension described in the step B is 50 to 200nm, and width is 20 to 50nm.
The lithographic method that surface silicon adopted of the SOI of etching described in step C substrate is a high density inductively coupled plasma ICP etching; Described ICP etching is for adopting CHF 3/ N 2Mist, CHF 3Flow be 60sccm, N 2Flow be 60sccm, etching is 60 seconds under the 400W radio-frequency power;
Remove photoresist described in the step C and remove photoresist for wet method, described wet method is removed photoresist to adopting dense H2SO4+H2O2 to boil glue.
The temperature that figure described in the step D relies on oxidation is 1000 ℃;
The diameter on the described coulomb island that forms after figure relies on oxidation of step D is 5 to 20nm, and the width of the tunnel junction of formation is 1 to 5 nanometer.
The deposition process of the gate dielectric membrane of SiO2 described in the step e is low pressure plasma chemical vapor deposition LPCVD, and the thickness of described SiO2 gate dielectric membrane is 400nm.
The optics of spin coated described in step F resist is for being the AZ5214 positivity optics resist of 1.6 μ m with sol evenning machine spin coated thickness, and the spin coated rotating speed is 4000 rev/mins, and the spin coated time is 60 seconds;
Baking is baking before adopting hot plate under 95 ℃ 90 seconds before described in the step F;
The exposure of lay photoetching mask plate described in the step F is carried out 40 seconds exposure for adopting lay photoetching mask plate to shelter, and the exposure area is the zone beyond source, leakage, the grid contact hole;
The baking of reversing described in the step F was toasted 90 seconds down at 115 ℃ for adopting hot plate;
General exposing to the sun for to the All Ranges of AZ5214 exposure 80 seconds described in the step F;
Develop described in the step F is to adopt the special-purpose developer solution of AZ5214 at room temperature to develop 60 seconds;
Photographic fixing described in the step F is for adopting deionized water photographic fixing at room temperature 30 seconds;
The contact hole graph that forms above source, leakage, grid described in the step F is the rectangular graph that length and width is respectively 5 to 500 μ m.
The dielectric film of SiO2 described in the step G is to rely on the SiO that grows in the oxidizing process at figure described in the step D 2The SiO of deposit described in dielectric film and the step e 2Gate dielectric membrane.
Corrode SiO described in the step G 2Dielectric film is for adopting buffered hydrofluoric acid solution HF+NH 4F+H 2O corrodes at normal temperatures.
Metal electrode material described in the step H is that thickness is the Al-1%Si alloy firm of 1 μ m.
Peel off described in the step I that acetone is ultrasonic to be peeled off in order to adopt;
Be annealed into described in the step I under 400 ℃ at N 2Middle annealing 30 minutes.
(3) beneficial effect
From technique scheme as can be seen, the present invention has following beneficial effect:
1, utilizes the present invention, owing to select the SOI backing material for use, on the surface silicon of SOI substrate, make silicon base bar single electronic transistor by adopting methods such as electron beam lithography, dry etching, figure dependence oxidation, device or the circuit compatibility that can make with traditional cmos process, thus improved greatly single-electronic transistor reliability and with the compatibility of traditional cmos process.
2, utilize the method for making silicon base bar single electronic transistor provided by the invention, simplified manufacture craft greatly, reduced cost of manufacture, improved technology stability and make efficiency, be very beneficial for extensive promotion and application of the present invention.
3, the electron beam lithography of the present invention's employing is a kind of effective nanoprocessing means, has nano level resolution, and particularly on the less relatively substrate of atomic number, resolution is higher.The silicon nanowires that the present invention utilizes electron beam lithography to produce has nanoscale, width is for can reach 20 to 50nm, the diameter on the coulomb island that forms after figure relies on oxidation can reach 5 to 20nm, the width of the tunnel junction that forms can reach 1 to 5nm, is very suitable for making single-electronic transistor.
4, the present invention utilizes electron beam lithography only need produce the 1-dimention nano line structure, and then utilize figure to rely on oxidation and produce undersized " tunnel junction-coulomb island-tunnel junction " structure, avoided direct employing electron beam lithography to produce the highly difficult of undersized " tunnel junction-coulomb island-tunnel junction " structure.
5, the present invention uses the side grid be positioned at coulomb side, island, is positioned at coulomb top grid of top, island with employing and compares, and can omit the processing steps such as growth, photoetching, etching of polysilicon, has simplified technological process.
6, the present invention's total capacitance of adopting electron beam lithography and figure to rely on coulomb island in the single-electronic transistor that method for oxidation makes can be lower than 10aF, can obtain higher operating temperature.
7, the single-electronic transistor that utilizes the present invention to produce has relatively low tunnel resistor, and to a few M Ω, this is very favorable to high speed operation from hundreds of K Ω.
Description of drawings
Fig. 1 is the structural representation of present conventional single-electronic transistor;
Fig. 2 is the structural representation of silicon base bar single electronic transistor provided by the invention;
Fig. 3 makes the realization flow figure of silicon base bar single electronic transistor overall technological scheme for the present invention;
Fig. 4 is a method flow diagram of making silicon base bar single electronic transistor in the embodiment of the invention;
Fig. 4-1 is for carrying out the schematic diagram of ion injection and short annealing on the surface silicon of SOI substrate according to the embodiment of the invention;
Fig. 4-2 be according to the embodiment of the invention on the surface silicon of SOI substrate spin coated HSQ negative electronic erosion-resisting agent and before the schematic diagram that dries by the fire;
The schematic diagram of Fig. 4-3 for the HSQ negative electronic erosion-resisting agent of spin coated being carried out e-beam direct-writing exposure, development and photographic fixing according to the embodiment of the invention;
Fig. 4-4 is mask etching SOI underlayer surface silicon and the schematic diagram that removes photoresist for utilize electronic corrosion-resistant according to the embodiment of the invention;
Fig. 4-5 carries out the schematic diagram that figure relies on oxidation processes for source, leakage, nano wire, the side grid that form after to etching according to the embodiment of the invention in surface silicon;
Fig. 4-6 is according to deposit SiO on the surface silicon of the embodiment of the invention after figure relies on oxidation 2The schematic diagram of gate dielectric membrane;
Fig. 4-7 is according to the SiO of the embodiment of the invention in deposit 2The schematic diagram of spin coated AZ5214 positivity optics resist and preceding baking on the gate dielectric membrane;
Fig. 4-8 for according to the embodiment of the invention to the AZ5214 positivity optics resist of spin coated carry out lay photoetching mask plate exposure, counter-rotating baking, generally expose to the sun, the schematic diagram of development and photographic fixing;
Fig. 4-9 carries out mask etch SiO for adopt AZ5214 optics Etching mask according to the embodiment of the invention 2The schematic diagram of medium;
Fig. 4-10 is the schematic diagram according to embodiment of the invention evaporated metal electrode material;
Fig. 4-11 is for peeling off, anneal according to the embodiment of the invention and forming the schematic diagram of electrode.
Embodiment
For making the purpose, technical solutions and advantages of the present invention clearer, below in conjunction with specific embodiment, and with reference to accompanying drawing, the present invention is described in more detail.
As shown in Figure 2, Fig. 2 is the structural representation of silicon base bar single electronic transistor provided by the invention, and this silicon base bar single electronic transistor comprises: silicon base 201, oxygen buried layer 202, source 203, leakage 204, coulomb island 205, tunnel junction 206, tunnel junction 207, gate medium 208, side grid 209, source electrode 210, drain electrode 211 and gate electrode 212.
Wherein, silicon base 201 is used to support whole single-electronic transistor; Oxygen buried layer 202 is used to insulate and isolates the silicon base 201 of single-electronic transistor and SOI substrate.Source 203, leakage 204, coulomb island 205, tunnel junction 206, tunnel junction 207 and side grid 209 are made by the surface silicon of SOI substrate.Source 203 and leakage 204 are positioned at the both sides on coulomb island 205, and gate medium 208 and side grid 209 are positioned at the side on coulomb island 205.The original thickness of SOI underlayer surface silicon is 30nm.
Based on silicon base bar single electronic transistor structural representation shown in Figure 2, Fig. 3 shows the realization flow figure that the present invention makes the silicon base bar single electronic transistor overall technological scheme, this manufacture method adopts electron beam lithography and figure to rely on method for oxidation, specifically may further comprise the steps:
Step 301: the surface silicon of SOI substrate is carried out ion inject and short annealing;
Step 302: on the surface silicon of SOI substrate the spin coated electronic corrosion-resistant and before baking, adopt e-beam direct-writing exposure, developing and fixing formation source, leakage, nano wire, side gate figure in the electronic corrosion-resistant that applies;
Step 303: the figure that will form in electronic corrosion-resistant is as mask, and the surface silicon of etching SOI substrate is also removed photoresist, formation source, leakage, nano wire, side gate figure in the surface silicon of SOI substrate;
Step 304: source, leakage, nano wire, the side gate figure that forms in the surface silicon carried out figure rely on oxidation, make the one dimension silicon nanowires change tunnel junction-coulomb island-tunnel junction structure into;
Step 305: deposit SiO2 gate dielectric membrane;
Step 306: spin coated optics resist, to the optics resist of spin coated carry out preceding baking, lay photoetching mask plate exposure, counter-rotating baking, generally expose to the sun, development and photographic fixing, above source, leakage, grid, form contact hole graph;
Step 307: utilize the figure that in the optics resist, forms as mask, corrosion SiO2 dielectric film;
Step 308: evaporation one layer thickness is less than the metal electrode material of optics resist thickness on the optics resist of the source of exposing, leakage, grid and not removal;
Step 309: peel off the metal electrode material of optics resist and last evaporation side thereof, carry out annealing in process, form electrode to peeling off the remaining metal electrode material in back.
The critical process of this manufacture method is that electron beam lithography (EBL) and figure rely on oxidation, utilize electron beam lithography and etching can produce the one dimension silicon nanowires, adopt figure to rely on oxidation and can produce undersized " tunnel junction-coulomb island-tunnel junction " structure by the one dimension silicon nanowires.
It is a kind of and the closely-related method for oxidation of concrete graphics shape oxide that figure relies on method for oxidation.In the dry oxygen ambient of one dimension silicon nanowires about 1000 ℃ during oxidation, oxygen atom can be from the top and the side diffusion of figure, thereby oxidation betides near the edge of figure more; Simultaneously, the inhibition of the stress that the oxidation of silicon line center is subjected to accumulating in the oxidizing process, so the two ends oxidation of one dimension silicon line is the fastest, and intermediate oxidation is slower, so just forms the silicon coulomb island that respectively there is a tunnel junction at two ends, and this potential barrier is caused by quantum size effect.The present invention mainly utilizes this method for oxidation to make undersized coulomb of island and tunnel junction on the surface silicon of SOI substrate, thereby makes complete silicon base bar single electronic transistor.
Realization flow figure based on the described making silicon base bar single electronic transistor of Fig. 3 overall technological scheme further describes the method that the present invention makes silicon base bar single electronic transistor below in conjunction with specific embodiment.
Embodiment one
As shown in Figure 4, Fig. 4 is a method flow diagram of making silicon base bar single electronic transistor in the embodiment of the invention, and this method may further comprise the steps:
Step 401: the surface silicon of SOI substrate is carried out ion inject and short annealing.
The technological process corresponding with this step is shown in Fig. 4-1, and Fig. 4-1 is for carrying out the schematic diagram of ion injection and short annealing on the surface silicon of SOI substrate according to the embodiment of the invention.
Among Fig. 4-1, the SOI substrate is made of for 403 3 layers silicon base 401, oxygen buried layer 402, surface silicon that 30nm is thick from top to bottom successively.
The purpose that described surface silicon 403 to the SOI substrate is carried out ion injection and short annealing is to improve the conductivity of SOI underlayer surface silicon.The condition that described ion injects is: inject P 31+Ion, injection energy are that 30keV, implantation dosage are 1 * 10 15Cm -2The condition of described short annealing is: at N 2Short annealing 10 seconds under 1000 ℃ of temperature in the atmosphere.
Step 402: on the surface silicon of SOI substrate spin coated HSQ negative electronic erosion-resisting agent and before dry by the fire.
The technological process corresponding with this step shown in Fig. 4-2, Fig. 4-2 be according to the embodiment of the invention on the surface silicon of SOI substrate spin coated HSQ negative electronic erosion-resisting agent and before the schematic diagram that dries by the fire.
Described spin coated HSQ negative electronic erosion-resisting agent is for using sol evenning machine spin coated HSQ negative electronic erosion-resisting agent on the surface silicon of SOI substrate, and the spin coated rotating speed is 6000 rev/mins, and the spin coated time is 60 seconds.Baking was baking before adopting hot plate under 150 ℃ 2 minutes before described HSQ negative electronic erosion-resisting agent to spin coated carried out.
Step 403: adopt e-beam direct-writing exposure, development, photographic fixing formation source, leakage, nano wire, side gate figure in the HSQ negative electronic erosion-resisting agent.
The technological process corresponding with this step is shown in Fig. 4-3, and Fig. 4-3 is the schematic diagram that the HSQ negative electronic erosion-resisting agent of spin coated is carried out e-beam direct-writing exposure, development and photographic fixing according to the embodiment of the invention.
Among Fig. 4-3,405,406 is HSQ negativity electron source, leakage graphic, 407 is HSQ negative electronic erosion-resisting agent nano wire figure, and 408 is HSQ negative electronic erosion-resisting agent side gate figure, wherein specifically being of a size of of nano wire figure 407: length 50 to 200nm, width 20 are to 50nm.
The actual conditions of described e-beam direct-writing exposure, development, photographic fixing is: the employing accelerating voltage is that 50KeV, electronic beam current are that 200pA, exposure dose are 1000 to 2000 μ C/cm 2Electron-beam lithography system, the HSQ negative electronic erosion-resisting agent is carried out e-beam direct-writing exposure, and adopts the aqueous solution contain 2.5% tetramethyl level ammonium hydroxide (TMAH) to develop 1 to 2 minute down at 40 to 50 ℃, adopt deionized water photographic fixing at room temperature 1 minute.
Step 404: as mask, the surface silicon of etching SOI substrate is also removed photoresist with HSQ negative electronic erosion-resisting agent figure, formation source, leakage, nano wire, side gate figure in surface silicon.
The technological process corresponding with this step is shown in Fig. 4-4, and Fig. 4-4 is mask etching SOI underlayer surface silicon and the schematic diagram that removes photoresist for utilize electronic corrosion-resistant according to the embodiment of the invention.
Among Fig. 4-4,409 is the source, and 410 for leaking, 411 is nano wire, 412 is the side grid, and source 409, leakage 410, nano wire 411, side grid 412 constitute by the surface silicon 403 of SOI substrate, wherein specifically being of a size of of silicon nanowires 411: length 50 to 200nm, width 20 are to 50nm.
The lithographic method that the surface silicon 403 of described etching SOI substrate is adopted is high density inductively coupled plasma (ICP) etching, and described ICP etching is for adopting CHF 3/ N 2Mist, CHF 3Flow be 60sccm, N 2Flow be 60sccm, etching is 60 seconds under the 400W radio-frequency power; Described method of removing photoresist is that wet method is removed photoresist, and described wet method is removed photoresist to adopting dense H 2SO 4+ H 2O 2Boil glue.
Step 405: source, leakage, nano wire, the side gate figure that forms in the surface silicon carried out figure rely on oxidation, make silicon nanowires change tunnel junction-coulomb island-tunnel junction structure into.
The technological process corresponding with this step is shown in Fig. 4-5, and Fig. 4-5 carries out the schematic diagram that figure relies on oxidation processes for source, leakage, nano wire, the side grid that form after to etching according to the embodiment of the invention in surface silicon.
Among Fig. 4-5,413 be source 409 among Fig. 4-4 after the oxidation reduced thickness the source, 414 be leakage 410 among Fig. 4-4 after the oxidation reduced thickness leakage, 415 is the coulomb island that the center of the nano wire 411 among Fig. 4-4 forms after oxidation, 416,417 is two tunnel junctions that the two ends of the nano wire 411 among Fig. 4-4 form after oxidation, 419 for after the oxidation in the source 409 that constitutes by surface silicon, leak 410, SiO that nano wire 411, above the side grid 412 and side generate 2Medium.The diameter on coulomb island 415 is 5 to 20nm, and the width of tunnel junction 416,417 is 1 to 5 nanometer.
Described figure rely on that oxidation adopts oxidizing temperature be 1000 ℃.
Step 406: deposit SiO 2Gate dielectric membrane.
The technological process corresponding with this step is shown in Fig. 4-6, and Fig. 4-6 is according to deposit SiO on the surface silicon of the embodiment of the invention after figure relies on oxidation 2The schematic diagram of gate dielectric membrane.
Among Fig. 4-6, the thickness of polysilicon membrane 420 is 200nm.
The deposition process of described polysilicon membrane is low-pressure chemical vapor phase deposition (LPCVD).
Step 407: spin coated AZ5214 positivity optics resist and preceding baking.
The technological process corresponding with this step is shown in Fig. 4-7, and Fig. 4-7 is according to the SiO of the embodiment of the invention in deposit 2The schematic diagram of spin coated AZ5214 positivity optics resist and preceding baking on the gate dielectric membrane.
Described spin coated AZ5214 positivity optics resist is for being the AZ5214 positivity optics resist of 1.6 μ m with sol evenning machine spin coated thickness, and the spin coated rotating speed is 4000 rev/mins, and the spin coated time is 60 seconds; Baking was baking before adopting hot plate under 95 ℃ 90 seconds before described AZ5214 positivity optics resist to spin coated carried out.
Step 408: to the AZ5214 positivity optics resist of spin coated carry out lay photoetching mask plate exposure, counter-rotating baking, generally expose to the sun, development, photographic fixing, above source, leakage, grid, form contact hole graph.
The technological process corresponding with this step shown in Fig. 4-8, Fig. 4-8 for according to the embodiment of the invention to the AZ5214 positivity optics resist of spin coated carry out lay photoetching mask plate exposure, counter-rotating baking, generally expose to the sun, the schematic diagram of development and photographic fixing.
Among Fig. 4-8, through lay photoetching mask plate exposure, counter-rotating baking, generally expose to the sun, after the development, photographic fixing, source 413, leak 414, the AZ5214 optics resist of side grid 418 tops is removed, thereby at SiO 2The surface of gate medium forms contact hole graph.
Described lay photoetching mask plate exposure is carried out 40 seconds exposure for adopting lay photoetching mask plate to shelter, and the exposure area is the zone beyond source, leakage, the grid contact hole; Described counter-rotating baking was toasted 90 seconds down at 115 ℃ for adopting hot plate; Described general exposing to the sun for to the All Ranges of AZ5214 exposure 80 seconds; Described development was at room temperature developed 60 seconds for the special-purpose developer solution that adopts AZ5214; Described photographic fixing is for adopting deionized water photographic fixing at room temperature 30 seconds; The described contact hole graph that forms above source, leakage, grid is the rectangular graph that length and width is respectively 5 to 500 μ m.
Step 409: utilize AZ5214 optics resist figure as mask, corrosion SiO 2Dielectric film.
The technological process corresponding with this step is shown in Fig. 4-9, and Fig. 4-9 carries out mask etch SiO for adopt AZ5214 optics Etching mask according to the embodiment of the invention 2The schematic diagram of medium.
Shown in Fig. 4-9, after the corrosion, the SiO of source 413, leakage 414, side grid 418 tops 2Medium is removed, thus formation source, leakage, grid contact hole expose source 413 in the bottom of contact hole, leak 414, the surface of side grid 418, contact hole be shaped as rectangle, contact hole is of a size of long 5 to 500 μ m, wide 5 to 500 μ m.
Described SiO 2Dielectric film is to rely on the SiO that grows in the oxidizing process at figure described in the step 405 2The SiO of deposit described in dielectric film 419 and the step 406 2Gate dielectric membrane 420; Described corrosion SiO 2Dielectric film 419 and 420 can adopt buffered hydrofluoric acid solution HF+NH 4F+H 2O corrodes at normal temperatures.
Step 410: evaporation one layer thickness is less than the metal electrode material of AZ5214 optics resist thickness on the AZ5214 optics resist of the source of exposing, leakage, grid and not removal.
The technological process corresponding with this step is shown in Fig. 4-10, and Fig. 4-10 is the schematic diagram according to embodiment of the invention evaporated metal electrode material.
Described metal electrode material 422,423,424,425 is the Al-1%Si alloy firm, and the thickness of Al-1%Si film is 1 μ m.
Step 411: the metal electrode material of peeling off AZ5214 optics resist and last evaporation side thereof, carry out annealing in process to peeling off the remaining metal electrode material in back, between surface silicon and the metal material, form ohmic contact between polysilicon and the metal material, form electrode, finish the making of silicon base bar single electronic transistor.
The technological process corresponding with this step is shown in Fig. 4-11, and Fig. 4-11 is for peeling off, anneal according to the embodiment of the invention and forming the schematic diagram of electrode.
Among Fig. 4-11,423 is the source electrode on the source 413, and 424 for leaking the drain electrode on 414, and 425 is the side gate electrode on the side grid 418.
Acetone is ultrasonic to carry out the method for the metal electrode material of the described AZ5214 of peeling off optics resist and last evaporation side thereof in order to adopt; Described to peel off the back remaining metal electrode material carry out annealing in process under 400 ℃ at N 2Middle annealing 30 minutes.
Above-described specific embodiment; purpose of the present invention, technical scheme and beneficial effect are further described; institute is understood that; the above only is specific embodiments of the invention; be not limited to the present invention; within the spirit and principles in the present invention all, any modification of being made, be equal to replacement, improvement etc., all should be included within protection scope of the present invention.

Claims (15)

1. a silicon base bar single electronic transistor is characterized in that, this single-electronic transistor comprises:
Coulomb island, be positioned at coulomb source of both sides, island and leakage, be connected coulomb island and source tunnel junction, is connected coulomb island and leakage tunnel junction, be positioned at the side gate electrode that deposits on the drain electrode that deposits in the source electrode that deposits on coulomb gate medium of side, island and side grid, the source, the leakage and the side grid.
2. silicon base bar single electronic transistor according to claim 1 is characterized in that, described source, leakage, side grid, coulomb island, tunnel junction are made by the surface silicon of SOI substrate.
3. silicon base bar single electronic transistor according to claim 2 is characterized in that, described SOI substrate comprises:
Silicon base is used to support whole single-electronic transistor;
Oxygen buried layer is used to insulate and isolates the silicon base of single-electronic transistor and SOI substrate;
Surface silicon is used to make coulomb island, tunnel junction, source, leakage, the side grid of silicon base bar single electronic transistor.
4. silicon base bar single electronic transistor according to claim 2 is characterized in that, the thickness of described SOI underlayer surface silicon is 30nm.
5. the manufacture method of a silicon base bar single electronic transistor is characterized in that, this manufacture method adopts electron beam lithography and figure to rely on method for oxidation, specifically may further comprise the steps:
A, the surface silicon of SOI substrate carried out ion injects and short annealing;
B, on the surface silicon of SOI substrate the spin coated electronic corrosion-resistant and before baking, adopt e-beam direct-writing exposure, developing and fixing formation source, leakage, nano wire, side gate figure in the electronic corrosion-resistant that applies;
C, the figure that will form in electronic corrosion-resistant are as mask, and the surface silicon of etching SOI substrate is also removed photoresist, formation source, leakage, nano wire, side gate figure in the surface silicon of SOI substrate;
D, the source to forming in the surface silicon, leakage, nano wire, side gate figure carry out figure and rely on oxidation, make the one dimension silicon nanowires change tunnel junction-coulomb island-tunnel junction structure into;
E, deposit SiO 2Gate dielectric membrane;
F, spin coated optics resist, to the optics resist of spin coated carry out preceding baking, lay photoetching mask plate exposure, counter-rotating baking, generally expose to the sun, development and photographic fixing, above source, leakage, grid, form contact hole graph;
The figure that G, utilization form in the optics resist corrodes SiO as mask 2Dielectric film;
H, on the source of exposing, leakage, grid and the optics resist do not removed evaporation one layer thickness less than the metal electrode material of optics resist thickness;
I, peel off the optics resist and go up the metal electrode material of evaporation side, carry out annealing in process, form electrode peeling off the remaining metal electrode material in back.
6. the manufacture method of silicon base bar single electronic transistor according to claim 5 is characterized in that, described steps A comprises:
Surface silicon to the SOI substrate is injected P 31+Ion, the injection energy is 30keV, implantation dosage is 1 * 10 15Cm -2, then at N 2Short annealing 10 seconds under 1000 ℃ of temperature in the atmosphere.
7. the manufacture method of silicon base bar single electronic transistor according to claim 5 is characterized in that,
The spin coated electronic corrosion-resistant is for using sol evenning machine spin coated HSQ negativity negative electronic erosion-resisting agent on the surface silicon of SOI substrate described in the step B, and the spin coated rotating speed is 6000 rev/mins, and the spin coated time is 60 seconds;
Baking is baking before adopting hot plate under 150 ℃ 2 minutes before described in the step B;
E-beam direct-writing exposure described in the step B is that 50KeV, electronic beam current are that 200pA, exposure dose are 1000 to 2000 μ C/cm for adopting accelerating voltage 2Electron-beam lithography system, the HSQ negative electronic erosion-resisting agent is carried out e-beam direct-writing exposure;
Develop described in the step B for adopting the aqueous solution that contains 2.5% tetramethyl level ammonium hydroxide TMAH to develop 1 to 2 minute down at 40 to 50 ℃;
Photographic fixing described in the step B is for adopting deionized water photographic fixing at room temperature 1 minute;
The length of the bargraphs of one dimension described in the step B is 50 to 200nm, and width is 20 to 50nm.
8. the manufacture method of silicon base bar single electronic transistor according to claim 5 is characterized in that,
The lithographic method that surface silicon adopted of the SOI of etching described in step C substrate is a high density inductively coupled plasma ICP etching; Described ICP etching is for adopting CHF 3/ N 2Mist, CHF 3Flow be 60sccm, N 2Flow be 60sccm, etching is 60 seconds under the 400W radio-frequency power;
Remove photoresist described in the step C and remove photoresist for wet method, described wet method is removed photoresist to adopting dense H2SO4+H2O2 to boil glue.
9. the manufacture method of silicon base bar single electronic transistor according to claim 5 is characterized in that,
The temperature that figure described in the step D relies on oxidation is 1000 ℃;
The diameter on the described coulomb island that forms after figure relies on oxidation of step D is 5 to 20nm, and the width of the tunnel junction of formation is 1 to 5 nanometer.
10. the manufacture method of silicon base bar single electronic transistor according to claim 5, it is characterized in that, the deposition process of the gate dielectric membrane of SiO2 described in the step e is low pressure plasma chemical vapor deposition LPCVD, and the thickness of described SiO2 gate dielectric membrane is 400nm.
11. the manufacture method of silicon base bar single electronic transistor according to claim 5 is characterized in that,
The optics of spin coated described in step F resist is for being the AZ5214 positivity optics resist of 1.6 μ m with sol evenning machine spin coated thickness, and the spin coated rotating speed is 4000 rev/mins, and the spin coated time is 60 seconds;
Baking is baking before adopting hot plate under 95 ℃ 90 seconds before described in the step F;
The exposure of lay photoetching mask plate described in the step F is carried out 40 seconds exposure for adopting lay photoetching mask plate to shelter, and the exposure area is the zone beyond source, leakage, the grid contact hole;
The baking of reversing described in the step F was toasted 90 seconds down at 115 ℃ for adopting hot plate;
General exposing to the sun for to the All Ranges of AZ5214 exposure 80 seconds described in the step F;
Develop described in the step F is to adopt the special-purpose developer solution of AZ5214 at room temperature to develop 60 seconds;
Photographic fixing described in the step F is for adopting deionized water photographic fixing at room temperature 30 seconds;
The contact hole graph that forms above source, leakage, grid described in the step F is the rectangular graph that length and width is respectively 5 to 500 μ m.
12. the manufacture method of silicon base bar single electronic transistor according to claim 5 is characterized in that, the dielectric film of SiO2 described in the step G is to rely on the SiO that grows in the oxidizing process at figure described in the step D 2The SiO of deposit described in dielectric film and the step e 2Gate dielectric membrane.
13. the manufacture method of silicon base bar single electronic transistor according to claim 5 is characterized in that, corrodes SiO described in the step G 2Dielectric film is for adopting buffered hydrofluoric acid solution HF+NH 4F+H 2O corrodes at normal temperatures.
14. the manufacture method of silicon base bar single electronic transistor according to claim 5 is characterized in that, metal electrode material described in the step H is that thickness is the Al-1%Si alloy firm of 1 μ m.
15. the manufacture method of silicon base bar single electronic transistor according to claim 5 is characterized in that,
Peel off described in the step I that acetone is ultrasonic to be peeled off in order to adopt;
Be annealed into described in the step I under 400 ℃ at N 2Middle annealing 30 minutes.
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