CN101123179A - Control method for extension slice equability for 6 inch As back lining MOS part - Google Patents
Control method for extension slice equability for 6 inch As back lining MOS part Download PDFInfo
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- CN101123179A CN101123179A CNA2007101394462A CN200710139446A CN101123179A CN 101123179 A CN101123179 A CN 101123179A CN A2007101394462 A CNA2007101394462 A CN A2007101394462A CN 200710139446 A CN200710139446 A CN 200710139446A CN 101123179 A CN101123179 A CN 101123179A
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Abstract
The present invention discloses a 6 inch As dorsal closure substrate MOS device epitaxial slice uniformity controlling method. The processing steps of the method are: HCL in-situ polishing--first high-flow H2 drive gas--temperature reduction--growth of intrinsic layer--the second high-flow H2 drive gas--the process of growth of epitaxial layer of remaining thick. The time for the first high-flow H2 drive gas is 20 to 30 minutes, the time for the second high-flow H2 drive gas is 5 to 10 minutes. After repeat tests, the optimal drive gas time of the present invention is capable of controlling self-doping, increasing epitaxial slice electrical resistivity edge uniformity. The spreading resistance flatness and the transition zone abruptness of the epitaxial slice produced by the present invention are better than those of epitaxial slice produced by traditional method.
Description
Technical field
The present invention relates to a kind of production method of MOS device epitaxial slice, especially relate to a kind of 6 inches As back of the body envelope substrate MOS device epitaxial slice uniformity control method.
Background technology
Silicon epitaxial wafer is a main material of making semi-conductor discrete device, because it can guarantee the high-breakdown-voltage of PN junction, can reduce the forward voltage drop of device again, silicon epitaxy is again the main manufacture craft of bipolar integrated circuit (IC) simultaneously, it can allow the IC device be made in gently mixing on the epitaxial loayer of heavily doped buried regions, can form the PN junction of growth again, solve the isolating problem of IC.Make cmos circuit with silicon epitaxial wafer and can suppress the soft error that breech lock (Latchup) effect and anti-α particle are produced, so that silicon epitaxial wafer is used in cmos device is increasingly extensive.In recent years, electronic devices and components producer is in order to improve die yield, and is more and more stricter to the consistency and the transition region control requirement of heavily doped As (arsenic) substrate silicon epitaxial wafer.Therefore, the autodoping of the outer time-delay of control, the uniformity of raising epilayer resistance rate, extremely important for the MOS device breakdown consistency that improves the user.
At present, in the producer that produces epitaxial wafer, Cheng Shu heavily doped As substrate silicon epitaxy technique is two step epitaxys, and its basic step is as follows:
1 intensification back HCl original position polishing, though the corrosion of the HCl under the high temperature is useful to improving lattice structure, but also to produce some accessory substances simultaneously, and the substrate surface that at high temperature also will peel a layer from, so also some enters in the atmosphere impurity in these accessory substances and the substrate.
2 for the first time big flow H
2It is 15～20 minutes that gas, time are caught up with in flushing.Big flow H
2Gas is caught up with in flushing, and the impurity that is adsorbed on chip, base-plates surface and is trapped in the boundary-layer is taken away by primary air.
3 growth one deck intrinsic epitaxial loayers.The intrinsic epitaxial loayer of growth plays sealing process to chip surface, stops the further outwards volatilization of substrate impurity, and the thickness of epitaxial loayer can change according to the variation of epilayer resistance rate.
4 for the second time big flow H
2It also is 15～20 minutes that gas, time are caught up with in flushing.Big flow H
2Gas is caught up with in flushing, and the impurity that is adsorbed on chip, base-plates surface and is trapped in the boundary-layer is taken away by primary air.
5 carry out the growth of second stage, up to the desired thickness of epitaxial loayer.
There is following problem in the method for impurity in traditional control epitaxial loayer: because they generally were to use for two steps caught up with the gas method, carry out the original position polishing with HCL earlier, gas is caught up with on the cleaning silicon wafer surface then for a long time; Behind the regrowth intrinsic layer again with the gas of catching up with of a large amount of time.This to catch up with the gas time of catching up with of gas method be the method for always continuing to use, and catches up with the time of gas identical twice, so not only wasted a large amount of time, and not very good to the control of autodoping, totally unfavorable for a large amount of productions.6 inches autodopings are more serious than 4 inches, and very undesirable to the inhomogeneity control in edge.
Summary of the invention
The technical issues that need to address of the present invention provide a kind of can High-efficient Production the method for 6 inches As back of the body envelope substrate MOS device epitaxial slice.
For solving the problems of the technologies described above, the technical solution adopted in the present invention is:
1, selects satisfactory substrate for use;
2, the extension parameter is: epilayer resistance rate 24 ± 8% Ω cm, epitaxy layer thickness 50 ± 5% μ m.
3, the epitaxial device of Cai Yonging: adopt the PE2061 epitaxial furnace of Italian LPE SPA, every stove can be adorned 14 of 6 inches silicon chips.
4, technical process:
The back HCl original position polishing 4.1 heat up;
4.2 for the first time big flow H
2It is 20～30 minutes that gas, time are caught up with in flushing;
4.3 cooling;
4.4 growth one deck intrinsic epitaxial loayer;
4.5 for the second time big flow H
2It is 5～10 minutes that gas, time are caught up with in flushing.
4.6 carry out the growth of second stage, up to the desired thickness of epitaxial loayer.
Because the technological progress of having adopted technique scheme, the present invention to obtain is:
The present invention is through test of many times, found best catching up with the gas time in the method for producing 6 inches As back of the body envelope substrate MOS device epitaxial slice, though the primary gas time lengthening of catching up with, but total gas time of catching up with has reduced, can the limited time be fully utilized,, prolonged and caught up with the gas time in the higher period in impurity concentration, improved production efficiency.Especially effectively control autodoping, improved 6 inches As back of the body envelope substrate MOS device epitaxial slice resistivity edge uniformity.
In process of production, the impurity after impurity that early stage, high-temperature baking was evaporated from substrate and the polishing of HCL original position can be stored in the retention layer, and these impurity enter epitaxial loayer again in growth course, thereby influence the uniformity of epitaxial wafer.Have only the impurity in the method minimizing retention layer that carries with the air-flow flushing, could reduce the influence of autodoping, improve resistivity evenness.The key of the inventive method is to have given up twice of continuing to use for many years to catch up with gas time in the identical two traditional steps to catch up with gas method, catch up with the gas time by using in the different steps difference, when impurity is more, adopt long catching up with the gas time, at impurity more after a little while, then use less catching up with the gas time,, make the impurity that stores in the retention layer can be good at being eliminated by catching up with the gas time of twice of rational collocation.
Be the contrast of result of the test of the resistivity evenness of the epitaxial wafer produced with the method for method of the present invention and prior art below:
The resistivity that original two steps of table one are caught up with the epitaxial wafer of gas method gained: (unit: Ω cm)
| Test position | On | In | Down | A left side | Right | On average | Maximum | Minimum | Uniformity |
| Ground floor | 22.32 | 24.2 | 19.58 | 22.16 | 20.5 | 21.75 | 24.2 | 19.58 | 10.5％ |
The table two resistivity (unit: Ω cm) of catching up with the epitaxial wafer of gas method gained of the present invention
| Test position | On | In | Down | A left side | Right | On average | Maximum | Minimum | Uniformity |
| Ground floor | 22.84 | 24.10 | 23.07 | 23.99 | 24.08 | 23.62 | 24.10 | 22.84 | 2.68％ |
The inhomogeneity computing formula of parameter is in the last table: (maximum-minimum value) * 100%/(maximum+minimum value).As can be seen from the above table, the uniformity with the resistivity of catching up with the epitaxial wafer that the gas method produces of the ratio routine of the resistivity of the resulting epitaxial wafer of method of the present invention has improved greatly.
The flatness of the spreading resistance of the epitaxial wafer that obtains with the present invention and the steepness of transition region are all used the ideal of the epitaxial wafer that obtains than traditional method.
This technology has not only increased substantially the uniformity of resistivity, and has reduced the process time, has reduced production cost.This technology has been used for the large-scale production of company at present, and the silicon epitaxy product is applied to domestic how tame client on heavily doped As back of the body envelope substrate, has obtained the consistent of user and has approved.
Description of drawings
Fig. 1 is the spreading resistance figure that utilizes the epitaxial loayer that method of the present invention grows;
Fig. 2 is the spreading resistance figure that utilizes two step epitaxy grown epitaxial layers in the past.
Embodiment
Below in conjunction with embodiment the present invention is described in further details:
Embodiment 1
1, substrate requires: as following table.
| Parameter (parameter) | Unit (unit) | Specification Value (normal value) |
| Dopant (dopant) | Arsenic/ arsenic | |
| Resistivity (resistivity) | CM | 0.002-0.004 |
| RRG MAX (resistivity gradient position) | ％ | 25.0 |
| Orientation (crystal orientation) | Degree (degree) | 1-1-1 |
| Off Orientation (crystal orientation irrelevance) | Degree (degree) | 4.0°±0.5° |
| Thickness and thickness tolerance (thickness and tolerance) | Microns (micron) | 6260±20.0 |
| Diameter and diametical tolerance (diameter and tolerance) | Mm (millimeter) | 150.0+0.20 |
| Back side (back side) | A | 5000±500 |
2, extension parameter
Epilayer resistance rate 24 ± 8% Ω cm, epitaxy layer thickness 50 ± 5% μ m.
3, the epitaxial device of Cai Yonging
Adopt the PE2061 epitaxial furnace of Italian LPE SPA, every stove can be adorned 14 of 6 English inch silicon chips.
4, technical process:
The back HCl original position polishing 4.1 heat up;
4.2 for the first time big flow H
2It is 20 minutes that gas, time are caught up with in flushing;
4.3 cooling;
4.4 growth one deck intrinsic epitaxial loayer.
4.5 for the second time big flow H
2It is 10 minutes that gas, time are caught up with in flushing.
4.6 carry out the growth of second stage, up to the desired thickness of epitaxial loayer.
The difference of present embodiment and embodiment is: the first time in the technology 4.2 is with big flow H
2It is 30 minutes that the time of gas is caught up with in flushing; 4.5 the middle second time is with big flow H
2It is 5 minutes that gas, time are caught up with in flushing.
Embodiment 3
The difference of present embodiment and embodiment is: the first time in the technology 4.2 is with big flow H
2It is 25 minutes that the time of gas is caught up with in flushing; 4.5 the middle second time is with big flow H
2In wash that to catch up with gas, time be 7 minutes.
Claims (1)
1.6 inch As back of the body envelope substrate MOS device epitaxial slice uniformity control method comprises that processing step is HCL original position polishing---the H of for the first time big flow
2---second time is the H of flow greatly in cooling---growth intrinsic layer---to catch up with gas
2Catch up with the process of the epitaxial loayer of gas-growth residual thickness, it is characterized in that: the H of for the first time big flow
2The time of catching up with gas is 20～30 minutes, the H of for the second time big flow
2The time of catching up with gas is 5～10 minutes.
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| Application Number | Priority Date | Filing Date | Title |
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| CNB2007101394462A CN100508118C (en) | 2007-09-18 | 2007-09-18 | Control method for extension slice equability for 6 inch As back lining MOS part |
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| CNB2007101394462A CN100508118C (en) | 2007-09-18 | 2007-09-18 | Control method for extension slice equability for 6 inch As back lining MOS part |
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| CN101123179A true CN101123179A (en) | 2008-02-13 |
| CN100508118C CN100508118C (en) | 2009-07-01 |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102024676A (en) * | 2010-05-25 | 2011-04-20 | 福建钧石能源有限公司 | Method for manufacturing semiconductor device in single-chamber reactor |
| CN102290337A (en) * | 2011-09-26 | 2011-12-21 | 南京国盛电子有限公司 | Manufacturing method for silicon epitaxial wafer of low-voltage TVS (transient voltage suppressor) |
| CN105448653A (en) * | 2014-09-01 | 2016-03-30 | 中芯国际集成电路制造(上海)有限公司 | Method of reducing wafer epitaxy process defect |
| CN106876248A (en) * | 2017-02-21 | 2017-06-20 | 河北普兴电子科技股份有限公司 | 8 inches of thin-film epitaxy pieces, uniformity control method and applications |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102522334A (en) * | 2011-12-15 | 2012-06-27 | 天津中环领先材料技术有限公司 | Technology for preparing monocrystalline silicon wafer back sealing material used in IGBT by using high temperature oxidation process |
-
2007
- 2007-09-18 CN CNB2007101394462A patent/CN100508118C/en active Active
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102024676A (en) * | 2010-05-25 | 2011-04-20 | 福建钧石能源有限公司 | Method for manufacturing semiconductor device in single-chamber reactor |
| CN102290337A (en) * | 2011-09-26 | 2011-12-21 | 南京国盛电子有限公司 | Manufacturing method for silicon epitaxial wafer of low-voltage TVS (transient voltage suppressor) |
| CN105448653A (en) * | 2014-09-01 | 2016-03-30 | 中芯国际集成电路制造(上海)有限公司 | Method of reducing wafer epitaxy process defect |
| CN106876248A (en) * | 2017-02-21 | 2017-06-20 | 河北普兴电子科技股份有限公司 | 8 inches of thin-film epitaxy pieces, uniformity control method and applications |
| CN106876248B (en) * | 2017-02-21 | 2019-11-12 | 河北普兴电子科技股份有限公司 | 8 inches of thin-film epitaxy pieces, uniformity control method and application |
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| Publication number | Publication date |
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| CN100508118C (en) | 2009-07-01 |
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