CN101113997A - Signal polarity detection device and associated method - Google Patents
Signal polarity detection device and associated method Download PDFInfo
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- CN101113997A CN101113997A CNA2007100877333A CN200710087733A CN101113997A CN 101113997 A CN101113997 A CN 101113997A CN A2007100877333 A CNA2007100877333 A CN A2007100877333A CN 200710087733 A CN200710087733 A CN 200710087733A CN 101113997 A CN101113997 A CN 101113997A
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Abstract
A sign detection device including a first comparing device for comparing a first input signal with a first threshold signal in a first period and a second period to generate a first output signal; a second comparing device for comparing a second input signal with a second threshold signal to generate a second output signal; a converter for optionally changing the polarity of the second output signal to obtain a third output signal; and an operator coupled to the first comparing device and the converter for performing a logic operation of the first output signal and the third output signal to obtain polarity information of the product of the first input signal and the second input signal.
Description
Technical Field
The present invention relates to a signal polarity detection device and method, and more particularly, to a signal polarity detection device and method for detecting the polarity of the product of two input signals.
Background
Generation of Quadrature Signals (I/Q) has been widely used in various wireless signal transmission, and can be implemented by Quadrature down-conversion mixer or polyphase filter (polyphase filter). In non-zero intermediate frequency (non-zero-IF) receiver architectures, the quadrature signal I/Q is important for image signal cancellation for post-frequency conversion; in a zero-IF receiver architecture, the quadrature signal I/Q can be used for non-coherent demodulation (non-coherent demodulation). As shown In fig. 1, the radio signal receiving end block diagram is that after being received by an antenna 10, a radio frequency radio signal RF is respectively multiplied by sine ω t and Cos ω t signals to demodulate and generate an In-phase (In-phase) signal I and a Quadrature (Quadrature) signal Q, and the Quadrature (Quadrature) signal Q is subjected to 90-degree phase delay and then added to the In-phase (In-phase) signal I to obtain an intermediate frequency signal IF.
In order to eliminate the image signal, many conventional approaches called analog image cancellation structures (analog image cancellation structures) have been developed, such as a weiver image rejection mixer (weifer image rejection mixer), a Hartley image rejection mixer (Hartley image rejection mixer), and a complex filter (complex filter).
In an ideal state, the gain and phase of the In-phase (In-phase) signal I and the Quadrature (Quadrature) signal Q should be matched, that is, the amplitude of the In-phase (In-phase) signal I and the Quadrature (Quadrature) signal Q should be the same, and the phase difference between the signal I and the signal Q is 90 degrees, so that the image rejection effect is good. However, in reality, an imbalance occurs between the signal I and the signal Q, that is, the amplitude of the signal I and the amplitude of the signal Q are different, and the phase difference between the signal I and the signal Q cannot be perfectly maintained at 90 degrees. The conventional circuit has a high sensitivity to the imbalance between the signal I and the signal Q, so that the Image Rejection Ratio (IRR) can be only 30dB to 35dB. The following equation shows the relationship between the rejection ratio of the image signal and the gain and phase mismatch (mismatch) between the signal I and the signal Q:
where Δ A/A represents the value of the gain mismatch and θ represents the value of the phase mismatch, the graph is shown in FIG. 2.
However, image Rejection Ratio (IRR) of 30dB to 35dB has not been satisfactory for the applications of radio frequency signal receivers (radio receivers) of today, such as 60dB for Image Rejection Ratio (IRR) requirements of terrestrial television (terrestrial TV) receivers. As can be seen from fig. 2, to achieve an Image Rejection Ratio (IRR) of 60dB, Δ a/a and θ are kept under a gain mismatch of 0.01dB and a phase mismatch of 0.1 degrees, respectively, which are difficult to achieve in the analog signal domain without any correction circuit.
Therefore, some calibration techniques such as those described in the following [1] to [6] references have been developed to compensate for the imbalance between the analog signal I and the signal Q, but the offset of the components themselves will affect the calibration result, so it is necessary to develop a solution for accurately detecting the gain imbalance and the phase imbalance, which can improve the rejection ratio.
[1]L.Der and B.Razavi，“A 2GHz CMOS Image-Rejection Receiver with LMS Calibration，”IEEE J.of Solid-State Circuits，Vol.38，pp.167-175，February 2003.
[2]C.Heng et.al.，“A CMOS TV Tuner/DemodulatorIC with Digital Image Rejection，”IEEE J.OF Solid-State Circuits，Vol. 40，No.12，pp.2525-2535，December 2005.
[3]S.Lerstaveesin and B.Song，“A Complex Image Rejection Circuit with Sign Detection Only，”ISSCC Technical Digest， Session 25.2，2006.
[4]M.Hajirostam and K.Martin，“On-chip Image Rejection in a Low-IF CMOS Receiver，”ISSCC Technical Digest，Session 25.3，2006.
[5]G.M.Desjardins，“Adaptive Digital Signal Processing Algorithms for Image-Rejection Mixer Self-Calibration，” UC Berkeley MS.Thesi s，2000.
[6]I.Sever，“Adaptive Cal ibration Methods for an Image Rejection Mixer，”UC Berkeley MS.Thesis，2002
Disclosure of Invention
The present invention provides a signal polarity detection device, which can increase the rejection ratio of the image signal.
In order to solve the above technical problem, the present invention provides a signal polarity detection apparatus, including: a first comparing device for comparing a first signal with a first threshold signal in response to a first time interval and a second time interval to output a first output signal; a second comparator comprising a second comparator and a converter, the converter being electrically connected to the second comparator, the second comparator comparing a second signal with a second threshold signal and outputting a second output signal; the converter receives the second output signal and changes the polarity of the second output signal according to the first time interval and the second time interval so as to convert and output a third output signal; and an arithmetic unit electrically connected to the first comparator and the second comparator for receiving the first output signal and the third output signal and calculating and outputting a polarity data representing the product of the first signal and the second signal.
Another object of the present invention is to provide a signal polarity detection method, which can improve the rejection ratio of the image signal.
A method for detecting signal polarity is applied to a first signal and a second signal, and comprises the following steps: detecting the polarity of the first signal in a first period of time, and detecting the polarity of the inverted signal of the first signal in a second period of time to generate a first output signal; detecting the polarity of the second signal to generate a second output signal; receiving the second output signal, and respectively outputting the second output signal and an inverted signal of the second output signal in the first time period and the second time period to generate a third output signal; and generating polarity data representing the product of the first signal and the second signal by operation according to the variation of the first output signal and the third output signal in the first time interval and the second time interval.
The polarity of the output signal of the second comparing device is changed by the converter and is inconsistent with the polarity of the output signal of the first comparing device, and the polarity of the input signal can be known by operating the two output signals by the arithmetic unit, so that the rejection ratio of the image signal can be improved.
Drawings
The invention is described in further detail below with reference to the drawings and the detailed description.
FIG. 1 is a block diagram of a conventional quadrature signal down-converting demodulation wireless signal receiving end.
Fig. 2 is a graph of image signal rejection ratio versus gain versus phase mismatch (mismatch) between signal I and signal Q.
FIG. 3 is a block diagram of a detecting apparatus for detecting the signs of an imbalance between a signal I and a signal Q.
Fig. 4 is a circuit diagram of a signal polarity detection device according to a preferred embodiment of the invention.
FIG. 5 is a schematic diagram showing signal waveforms of the sampling clock signal CLK and the control signals Ψ 1 and Ψ 2 according to a preferred embodiment of the present invention.
FIG. 6 is a block diagram of an apparatus for detecting gain and phase imbalance of a signal according to a preferred embodiment of the present invention.
FIG. 7 is a flowchart illustrating a signal polarity detection method according to a preferred embodiment of the invention.
[ description of main reference symbols ]
Mutual exclusion nor gates 35, 36 low pass filters 37, 38
First comparator 41 second comparator 42
Converter 43 arithmetic unit 44
First output signal S1 second output signal S2
Third output signal S3 fourth output signal S4
First controlled switch 401 second controlled switch 402
Third controlled switch 403 fourth controlled switch 404
Inverter 430 fifth controlled switch 435
Accumulator 441 of sixth controlled switch 436
First comparing means 5 second comparing means 6
Detailed Description
FIG. 3 is a block diagram of a functional block diagram for detecting imbalance between signals I and Q. Assuming that α represents the gain mismatch value and θ represents the phase mismatch value, when α is much smaller than 1 and θ is also small, the signals I and Q can be expressed by the following equations, respectively:
I＝(1+α)cos(ωt+θ)
Q＝sin(ωt)
and the product of signal I and signal Q can be expressed as:
as can be seen from the above equation, the product of I and Q includes a DC component and two AC components, wherein the DC component is proportional to the phase mismatch value θ. Therefore, as long as the sign (or polarity) of the product of I and Q is known, a reference can be obtained to correct the phase mismatch between I and Q.
And the squared difference of signal I and signal Q can be expressed as:
I 2 -Q 2 ＝(I+Q)·(I-Q)
＝[(1+α)cos(ωt+θ)] 2 -sin 2 (ωt)
＝(1+2α+α 2 )cos 2 (ωt+θ)-sin 2 (ωt)
＝(1+2α+α 2 )(cos(ωt)-θsin(ωt)) 2 -sin 2 (ωt)
＝(1+2α+α 2 )(cos 2 (ωt)-2θcos(ωt)+θ 2 sin 2 (ωt))-sin 2 (ωt)
≌(1+2α)(cos 2 (ωt)-2θcos(ωt))-sin 2 (ωt)
≌cos 2 (ωt)-sin 2 (ωt)+2αcos 2 (ωt)
＝cos(2ωt)+α(1+cos(2ωt))
＝(1+α)cos(2ωt)+α
as can be seen from the above equation, the square error of the signal I and the signal Q comprises a DC component and an AC component, wherein the DC component and the value α of the gain mismatch have a proportional relationship. Therefore, as long as the sign (or polarity) of the squared difference between the signal I and the signal Q is known, a reference for correcting the I and Q gain mismatch can be obtained.
Therefore, the functional block diagram of fig. 3 for detecting the imbalance between the signal I and the signal Q can be used to detect the polarities α and θ. After the signals I and Q are input into the four analog comparators 31, 32, 33, 34 respectively to obtain the polarities of the signals I, Q, I-Q and I + Q, the polarities of the signals I2-Q2 and I × Q can be obtained through the operations of the exclusive nor gates 35, 36 and the low- pass filters 37, 38, so as to determine the direction in which the signals I and Q need to be corrected, and then the gains and phases of the signals I and Q can be changed through a digital-to-analog converter (DAC, not shown), so that the imbalance between the signals I and Q can be effectively reduced. However, as can be seen from the above equation, because of the mutual interference of the ac components, the sampled data detected by one sign is not sufficient to determine the unmatched polarity, so that it is necessary to accumulate enough samples to accurately determine the unmatched polarity (i.e. the function of the low-pass filters 37, 38).
Even though the impact of the mutual interference of the ac components on the positive and negative detection can be mitigated by accumulating enough samples, the offset voltages (offsets) of the analog comparators (analog comparators) 31, 32, 33, 34 in fig. 3 still cause a big problem of the error in the positive and negative detection. As can be seen from circuit simulation, when the 100 mVrms signal I and signal Q with α =1% are received, even if there is only 0.3mV of comparator offset, the unmatched polarities cannot be correctly determined, but the offset level of the analog comparator without offset compensation is about 10mV, which seriously affects the correction accuracy of the imbalance and limits the correction resolution.
Referring to fig. 4, a circuit diagram of a signal polarity detection device 40 according to a preferred embodiment of the invention is shown, which includes a first comparison device 5, a second comparison device 6 and an operator 44.
The signal polarity detection device 40 receives the first signal and the second signal to detect the polarity (i.e. sign) of the product; preferably, the first signal and the second signal are an In-phase (In-phase) signal I and a Quadrature (Quadrature) signal Q, respectively, or a sum (I + Q) and a difference (I-Q) of the In-phase signal and the Quadrature signal.
And the first comparator 41 in the first comparing means 5 and the second comparator 42 in the second comparing means 6 may be analog comparators. The first comparator 41 and the second comparator 42 can compare the levels of the signals inputted from the two input terminals thereof in response to the triggering of the rising edge of the sampling clock signal CLK, and then output an output signal representing the comparison result from the output terminal according to the magnitude relationship of the levels of the signals received from the first input terminal and the second input terminal. For example, when the first comparator 41 is used to determine the polarity of the in-phase signal I, the in-phase signal I is input to the first input terminal 411, and a first threshold signal T1 is input to the second input terminal 412, preferably, the first input terminal 411 and the second input terminal 412 can respectively receive the differential signal pair I, I —, i.e. the first threshold signal T1 can be the differential inverted phase signal I-, of the in-phase signal I, ideally, the first output signal S1 representing the polarity of the in-phase signal I is output from the first output terminal 413. Similarly, when the second comparator 42 is used to determine the polarity of the quadrature signal Q, the quadrature signal Q is input to the third input 421, and a second threshold signal T2 is input to the fourth input 422; preferably, the third input terminal 421 and the fourth input terminal 422 can receive the differential signal pair Q, Q-respectively, i.e. the second threshold signal T2 can be a differential inverse signal Q-of the quadrature signal Q, ideally, the second output signal S2 representing the polarity of the quadrature signal Q is outputted by the second output terminal 423.
However, since the first comparator 41 and the second comparator 42 are both analog comparators having offset voltages (offsets), the circuit is actually affected by the offset voltage α of the first comparator 41 and the offset voltage β of the second comparator 42. The input terminals of the first comparator 41 and the second comparator 42 are assumed to be differential signal pairs of a and B, respectively, but actually the equivalent inputs are (a- α) and (B- β), so that the polarity of (a- α) and the polarity of (B- β) are determined respectively. The output signal generated by the XOR NOR gate 440 of the operator 44 actually outputs the signal representing the polarity of (A- α) · (B- β), i.e., if the first comparator 41 and the second comparator 42 respectively input the pair of the in-phase signal I and the pair of the quadrature signal Q, the final output thereof actually represents the polarity of (I- α) · (Q- β).
Further, when (A- α) (B- β) is resolved, it can be found that:
(A-α)·(B-β)＝A·B-α·B-β·A+α·β
besides A.B, other terms can affect the detection accuracy, i.e., the offset voltage can seriously cause the defect of wrong sign detection. The signal polarity detection device 40 of the present invention in FIG. 4 shows that the effect of the offset voltage can be eliminated by using the controlled switch.
Preferably, the sampling clock signal CLK is first processed into the control signals Ψ 1 and Ψ 2 by a frequency divider (not shown) with a denominator 2n, and when n =1, Ψ 1 and Ψ 2 as shown in fig. 5 are used, so that the inverted Ψ 1 and Ψ 2 define the first time period t1 and the second time period t2 by their high-level time periods, respectively, and the first time period t1 and the second time period t2 are defined on two adjacent cycles from the sampling clock signal CLK. Alternatively, a single control signal may be used to define the first time period t1 and the second time period t2, for example, the high level and the low level of the control signal Ψ 1 are used to define the first time period t1 and the second time period t2, respectively.
Through the setting of the first controlled switch 401, the second controlled switch 402, the third controlled switch 403 and the fourth controlled switch 404 and the control of the control signals Ψ 1 and Ψ 2 as shown in fig. 4, the first controlled switch 401 and the second controlled switch 402 are turned on during the first time period t1 (the third controlled switch 403 and the fourth controlled switch 404 are turned off during the first time period t 1), so that the first input terminal 411 and the second input terminal 412 of the first comparator 41 can respectively receive the in-phase signal I and the differential inverted signal I-, and thus the equivalent input of the first comparator 41 turned on during the first time period t1 is (I- α), and the first output signal S1 representing the polarity of (I- α) is output. On the other hand, the third controlled switch 403 and the fourth controlled switch 404 are turned on during the second time period t2 (the first controlled switch 401 and the second controlled switch 402 are turned off during the second time period t 2), so that the first input terminal 411 and the second input terminal 412 of the first comparator 41 can receive I-and I, respectively, such that the equivalent input of the first comparator 41 turned on during the second time period t2 is (-I- α), and the output first output signal S1 represents the polarity of (-I- α). Broadly speaking, if the input of the first comparator 41 is a, the first output signal S1 is turned on to output the polarity of (a- α) during the first period t1 in consideration of the offset voltage α; the first output signal S1 is turned on and output in the second time period t2, which represents the polarity (-A-alpha).
For convenience of the following description, fig. 4 is labeled with a first output terminal 413, a second output terminal 423, a third output terminal 433, and a fourth output terminal 443, respectively, to output a first output signal S1, a second output signal S2, a third output signal S3, and a fourth output signal S4, respectively, and it is noted that the first output signal S1 represents the output of the first comparator 41; the second output signal S2 represents the output of the second comparator 42; the third output signal S3 represents the output of the second comparing means 6, i.e. the output of the converter 43; the fourth output signal S4 represents the output of the exclusive nor gate 440.
Furthermore, through the converter 43 as disclosed in fig. 4, including the inverter 430, the fifth controlled switch 435 and the sixth controlled switch 436, by controlling the control signals Ψ 1 and Ψ 2, the fifth controlled switch 435 is turned on in the first time period t1 and outputs the second output signal S2 output by the second comparator 42 after comparing the quadrature signal Q with the differential inverted signal Q-via the turned-on fifth controlled switch 435, which is directly converted into the third output signal S3 at the third output terminal 433, so that the equivalent input of the second comparator 42 turned on in the first time period t1 is (Q- β), and accordingly, the second comparing device 6 outputs the third output signal S3 at the third output terminal 433 representing the polarity of (Q- β) in the first time period t 1. On the other hand, the sixth controlled switch 436 is turned on during the second period t2, and the inverter 430 receives the second output signal S2 for inversion and then outputs the third output signal S3 through the turned-on sixth controlled switch 436, so that the second comparing device 6 outputs the third output signal S3 representing the polarity of- (Q- β) at the third output terminal 433 during the second period t2. Broadly speaking, if the input of the second comparator 42 is B, the third output signal S3 outputted by the second comparing device 6 in the first period t1 represents the polarity of (B- β) considering the offset voltage β; the inverter 430 is turned on to output the third output signal S3 representing the polarity of- (B- β) during the second time period t2.
As a result, the fourth output signal S4 outputted from the fourth output 443 by the XOR NOR gate 440 has a polarity of (A- α) · (B- β) during the first time period t1 and a polarity of (-A- α) · (- (B- β)) during the second time period t2.
After decomposition (-A-alpha) · (- (B-beta)) it can be found:
(-A-α)·(-(B-β))＝A·B+α·B-β·A-α·β
the term "α β" varied with the offset voltage α and the offset voltage β can be eliminated by adding the adjacent time, and only the unaffected a · B and the ac component (α B), - β a with relatively small value and capable of self-cancelling by long-time accumulation are left, so that when the xor gate 440 performs an xor operation on the first output signal S1 and the third output signal S3 (or performs an xor operation by using an xor gate, but the corresponding digital processing is changed correspondingly), the fourth output signal S4 is output at the fourth output terminal 443 and accumulated by the accumulator 441, for example, the circuit can be implemented by an integrator, so as to obtain the polarity representing the product of I and Q without being affected by the variation of the offset voltage α and the offset voltage β. Similarly, the polarity of the I + Q and I-Q product can be accurately detected by the above-mentioned device.
Fig. 6 is a block diagram of an apparatus for detecting gain imbalance α and phase mismatch θ between a signal I and a signal Q according to a preferred embodiment of the present invention, which uses the signal polarity detecting apparatus shown in fig. 4, wherein the in-phase signal I and the quadrature signal Q are respectively sent to two sets of first comparing device 5, second comparing device 6 and computing device 44 developed in the present application for processing, so as to obtain the gain imbalance values α and the polarities sgn (α) and sgn (- θ) of the phase mismatch θ without being affected by the offset of the comparator.
As shown by actual simulation, even if the offset voltage α and the offset voltage β are both as high as 5mV, the present technology can still correctly detect the polarity of the I/Q signal with 0.2% gain imbalance and 0.1 degree phase imbalance. For example, the gain imbalance and the phase imbalance which are accurately detected after the offset correction of the invention can be fed back to the front stage through the digital-to-analog converter to adjust the gain and the phase, so that the gain imbalance and the phase imbalance can be well controlled.
Fig. 7 is a flowchart of a signal polarity detection method according to a preferred embodiment of the invention, mainly applying polarity data for accurately determining the product of a first signal and a second signal, and the method comprises the following steps:
step 601: the polarity of the first signal is detected in a first period, and the polarity of the inverted signal of the first signal is detected in a second period so as to generate a first output signal.
Step 602: detecting the polarity of the second signal to generate a second output signal; receiving the second output signal, and outputting the second output signal and an inverted signal of the second output signal in the first period and the second period respectively to form a third output signal.
Step 603: and performing exclusive-or (XOR) operation on the first output signal and the third output signal to output a fourth output signal.
Step 604: the fourth output signal is accumulated to generate the polarity data representing the product of the first signal and the second signal.
Applying the above steps to the circuit block diagram of fig. 6 showing the gain imbalance α and the phase mismatch θ between the detectable signal I and the detectable signal Q, the polarity data represents the phase imbalance when the first signal and the second signal are the in-phase signal and the quadrature signal, respectively; when the first signal and the second signal are the sum of the in-phase signal and the orthogonal signal and the difference between the in-phase signal and the orthogonal signal, respectively, the polarity data represents the imbalance of the gain. Assuming that the polarity data generated in step 604 represents a gain imbalance, the method flow of fig. 7 may further include the step of generating a polarity data representing a phase mismatch, which can be obtained by steps 601 to 604. The gain and phase of the circuit are compensated based on the polarity data representing the gain imbalance and the polarity data representing the phase mismatch.
The first period and the second period may be defined by two adjacent cycles of a sampling clock signal, for example, as defined by the signal shown in fig. 5, but not limited thereto. The principle is that the first time interval and the second time interval have substantially the same length and are evenly distributed, for example, a 2n divided frequency signal of the sampling frequency signal, where n is a positive integer, so as to achieve the purpose of canceling the error.
Claims (13)
1. A signal polarity detection device, comprising:
a first comparing device for comparing a first signal with a first threshold signal in response to a first time interval and a second time interval to output a first output signal;
a second comparator, comprising a second comparator and a converter, wherein the converter is electrically connected to the second comparator, and the second comparator compares a second signal with a second threshold signal to output a second output signal; the converter receives the second output signal and changes the polarity of the second output signal in response to the first time interval and the second time interval so as to convert and output a third output signal; and
an arithmetic unit electrically connected to the first comparator and the second comparator for receiving the first output signal and the third output signal and outputting a polarity data representing the product of the first signal and the second signal.
2. The apparatus of claim 1, wherein the first comparing means switches input paths of the first signal and the first threshold signal corresponding to the first time interval and the second time interval.
3. The apparatus of claim 2, wherein the first comparator comprises a first comparator having a first input terminal, a second input terminal and a first output terminal, the first comparator receives the first signal and the first threshold signal from the first input terminal and the second input terminal respectively during the first period, receives the first threshold signal and the first signal from the first input terminal and the second input terminal respectively during the second period, and outputs the first output signal from the first output terminal according to the magnitude of the electrical level of the signals received by the first input terminal and the second input terminal.
4. The apparatus of claim 3, wherein the first comparator further comprises a first controlled switch, a second controlled switch, a third controlled switch and a fourth controlled switch, the first input terminal, the second input terminal, the first signal and the first threshold signal are electrically connected through the controlled switches, the first controlled switch and the second controlled switch are turned on in the first time period, so that the first input terminal and the second input terminal can receive the first signal and the first threshold signal, respectively, and the third controlled switch and the fourth controlled switch are turned on in the second time period, so that the first input terminal and the second input terminal can receive the first threshold signal and the first signal, respectively.
5. The apparatus of claim 1, wherein the second comparator has a third input terminal, a fourth input terminal, and a second output terminal, receives the second signal and the second threshold signal from the third input terminal and the fourth input terminal, respectively, and outputs the second output signal from the second output terminal according to the magnitude of the voltage levels of the signals received by the third input terminal and the fourth input terminal; and the converter includes:
a fifth controlled switch, electrically connected between the second output terminal of the second comparator and the arithmetic unit, for receiving the second output signal and conducting in the first period of time to output the third output signal;
the inverter is electrically connected to the second output end of the second comparator, receives the second output signal, inverts the second output signal and outputs the second output signal; and
a sixth controlled switch, electrically connected between the inverter and the operator, for receiving the inverted signal of the second output signal and turning on in the second period of time to output the third output signal.
6. The apparatus according to claim 1, wherein the operator comprises:
a exclusive nor gate electrically connected to the first comparator and the second comparator, for performing an exclusive nor operation on the first output signal and the third output signal and outputting a fourth output signal; and
an accumulator, electrically connected to the XOR gate, for accumulating the fourth output signal to generate the polarity data representing the product of the first signal and the second signal.
7. The apparatus of claim 1, wherein the first signal and the second signal are an in-phase signal and a quadrature signal, respectively, and the first threshold signal and the second threshold signal are inverted signals of the in-phase signal and the quadrature signal, respectively.
8. The apparatus of claim 1, wherein the first signal and the second signal are both in-phase signals, and the first threshold signal and the second threshold signal are respectively a quadrature signal and an inverted signal of the quadrature signal.
9. The apparatus of claim 1, wherein the first comparator and the second comparator compare with each other according to a sampling clock signal, and the first period and the second period are defined by two adjacent cycles of the sampling clock signal.
10. A signal polarity detection method applied to a first signal and a second signal, the method comprising the steps of:
detecting the polarity of the first signal in a first period of time and detecting the polarity of the inverted signal of the first signal in a second period of time to generate a first output signal;
detecting the polarity of the second signal to generate a second output signal;
receiving the second output signal, and outputting the second output signal and an inverted signal of the second output signal in the first period and the second period respectively to generate a third output signal; and
generating a polarity data representing the product of the first signal and the second signal by operation according to the variation of the first output signal and the third output signal in the first time interval and the second time interval.
11. The method of claim 10, wherein the first signal and the second signal are an in-phase signal and an orthogonal signal, respectively.
12. The method of claim 10, wherein the first signal and the second signal are a sum of an in-phase signal and a quadrature signal and a difference between the in-phase signal and the quadrature signal, respectively.
13. The method of claim 10, wherein the first time interval and the second time interval are substantially equal in length and are distributed evenly.
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