CN101101581A

CN101101581A - Data reading method of wishbone system structure

Info

Publication number: CN101101581A
Application number: CNA2007100254120A
Authority: CN
Inventors: 张斌; 胡明昌
Original assignee: JIANGSU LEMOTE TECHNOLOGY Corp Ltd
Current assignee: JIANGSU LEMOTE TECHNOLOGY Corp Ltd
Priority date: 2007-07-27
Filing date: 2007-07-27
Publication date: 2008-01-09

Abstract

Characters of the invention are that the method includes following steps: master unit send 'read' command to slave unit, and the flag bit TAGN_O of the 'read' command is in use for indicating length of data needed to read; TAGN_O of master unit is connected to TAGN_I of slave unit; slave unit reads back data in the said length from data interface; returns the data reads back to master unit. Comparing prior art, the disclosed method makes Wishbone slave unit know how many data needed to read for master unit when receiving 'read' command. Thus, slave unit can adjust own action to access anther interface based on data needed to read for master unit so as to prevent wasting bandwidth, and increasing time delay.

Description

The method of read data in the wishbone architecture

Technical field

The present invention relates to be used for the method for read data in the Wishbone architecture, particularly wishbone architecture of SOC (system on a chip) interconnection.

Background technology

Wishbone is the architecture that is used for SOC (system on a chip) (SOC) system interconnection that Silicore company releases, and, interconnection simple owing to its hardware configuration handled up efficient and freely open, so be widely used in the on-chip interconnect system.

Four kinds of modules have been defined in the Wishbone architecture: main equipment, slave unit, link block and system module.Wherein system module produces the clock and the reset signal of whole Wishbone system, and link block is responsible for connecting main equipment and slave unit, and main exchanges data occurs between main equipment and the slave unit module.The Wishbone main equipment is the initiator who operates on the Wishbone interface, and it can initiatively be given an order, provide write data and receive read data; The Wishbone slave unit is the take over party of operation, and it receives order, write data and returns read data.

The Wishbone architecture specification has defined the signal name and the implication thereof of main equipment and slave unit.Except necessary control signal and address data signal, in optional signal, TAGN_O and TAGN_I are zone bits, and the user can be self-defined, and the extra operation information that provides outside the essential signal of Wishbone regulation is provided.Wherein N is the number of diacritics position, because sometimes need to use a plurality of zone bits.

When common Wishbone architecture realizes, the Wishbone module all is to finish the conversion of other interfaces to Wishbone, the PCI of Wishbone interface (Peripheral ComponentInterconect for example, the Peripheral Component Interconnect standard) USB of controller, Wishbone interface (UniversalSerial Bus, USB (universal serial bus)) controller etc.In the description of background technology, illustrate as an example with the pci controller of Wishbone interface.Initiate a Wishbone read operation when main equipment to slave unit, the slave unit module will return to main equipment then from the pci interface readback data earlier.Generally speaking, slave unit does not know how many data main equipment needs, and slave unit all read datas of having only by the time it to obtain from pci interface know just whether main equipment needs new data after all returning, so occur the situations of following two kinds of waste efficient probably: 1) slave unit is from data lacking than the main equipment needs that pci interface reads back, at this moment slave unit must be initiated read operation once more on pci interface, again these data are returned to afterwards main equipment Deng the pci interface return data, a read operation of main equipment has become serialized a plurality of read operations fully on another interface of PCI, PCI may be by idle, bandwidth does not make full use of, and the slave unit return data to give the time-delay of main equipment also be the poorest; 2) the slave unit data of reading back than main equipment need many, the bandwidth on the pci interface of slave unit has been wasted so, if the another one interface is a shared bus structure, this waste will influence the performance of all devices on the shared bus.

Summary of the invention

At above-mentioned defective, the method of read data in the Wishbone architecture provided by the invention, by being masked as the length that TAGN_O sets required read data, make the Wishbone slave unit when receiving read command, just know how many read datas main equipment needs, slave unit can be adjusted the own behavior that visit the another one interface according to the read data of main equipment needs, avoid in background technology, mentioning to the waste of bandwidth and the increase of time-delay.

The method of read data is characterized in that in a kind of Wishbone architecture provided by the invention,

Comprise the steps:

Main equipment sends read command to slave unit, and the zone bit TAGN_O of described read command is used to indicate the length of required read data;

The TAGN_O of main equipment links the TAGN_I of slave unit;

Slave unit is from the read back data of described length of data-interface;

Slave unit returns to main equipment with described readback data.

Compared with prior art, the method of read data in the Wishbone architecture provided by the invention, by being masked as the length that TAGN_O sets required read data, make the Wishbone slave unit when receiving read command, just know how many read datas main equipment needs, slave unit can be adjusted the own behavior that visit the another one interface according to the read data of main equipment needs, avoid in background technology, mentioning to the waste of bandwidth and the increase of time-delay.

Description of drawings

Fig. 1 is the one-piece construction synoptic diagram of inventive embodiments Godson 2E north bridge;

Fig. 2 is the PCI bridge module of Wishbone interface;

Fig. 3 is the Godson 2E processor interface module of Wishbone interface;

Fig. 4 is the time-delay contrast synoptic diagram of PCI DMA (Direct Memory Access, direct memory access) read operation.

Embodiment

Below be embodiment provided by the invention.

Fig. 1 is the general illustration of embodiment Godson 2E north bridge.The main interface of embodiment comprises Godson 2E processor interface and pci interface.Corresponding main modular comprises cpu i/f module and PCI bridge module.The cpu i/f module is connected by the Wishbone agreement with the PCI bridge module.Godson 2E processor interface can be supported the request of 8 Outstanding, and promptly main uncompleted operation is less than 8, just can continue to send next request.

Fig. 2 is the structural drawing of PCI bridge module.The PCI bridge module is made up of PCI main equipment and two modules of PCI slave unit, and it has realized the pci interface agreement, is responsible for the PCI equipment in the connected system.The PCI main equipment is the Wishbone slave unit, and it handles CPU to the visit of north bridge pci configuration space and the CPU visit to PCI equipment; The PCI slave unit is the Wishbone main equipment, and its receives the request that PCI equipment is initiated, and comprises dma operation and to the visit of pci configuration space, is converted to the operation of Wishbone bus.

Fig. 3 is the structural drawing of cpu i/f module.Order and the data sent for cpu i/f at first in the order data formation of writing module inside, and are initiated operation on the Wishbone bus by the Wishbone host device interface by the order in the formation, and data and order are delivered to object module; Read return data and deposit read data earlier in and return in the formation, and return by the cpu i/f order.To the DMA read-write requests that the PCI bridge module is initiated by Wishbone slave unit interface, directly give an order, and write out data or the data that cpu i/f returns are directly returned to the PCI bridge to cpu i/f.

For the PCIDMA read operation, at first on pci bus, to initiate by PCI equipment, the PCI bridge module of Godson 2E north bridge receives order, and passes through the Wishbone main equipment module read command on the Wishbone interface of oneself; The cpu i/f module receives read request from the Wishbone slave unit interface of oneself, gives an order to cpu i/f then, and the data that cpu i/f is returned return to the PCI bridge module.Data width between PCI bridge and the cpu i/f is 64 (8 bytes), and 32 byte datas are returned in each read operation of processor interface.

The PCI bridge joint is received the DMA read command that PCI equipment is initiated on pci bus, by the difference order is that Memory Read, Memory Read Line and Memory Read Multiple judge how many data PCI equipment needs, general Memory Read and Memory Read Line only get the data that a processor interface read operation is returned, be data 32 bytes of a Cache (high-speed cache) row also, MemoryRead Multiple gets the capable data of a plurality of Cache.In our realization, use TAG0_O 1 to indicate that to need the capable data of a plurality of Cache, TAG0_O be that 0 indication needs the data that Cache is capable.Fig. 4 is that PCIDMA need to read the time-delay synoptic diagram of 64 byte datas when the Wishbone main equipment read data length of TAGN_O indication PCI bridge was arranged.

The above only is a preferred implementation of the present invention; should be pointed out that for those skilled in the art, under the prerequisite that does not break away from the principle of the invention; can also make some improvements and modifications, these improvements and modifications also should be considered as protection scope of the present invention.

Claims

1, the method for read data in a kind of Wishbone architecture is characterized in that, comprise the steps: that main equipment sends read command to slave unit, the zone bit TAGN_O of described read command is used to indicate the length of required read data;

The TAGN_O of main equipment links the TAGN_I of slave unit;

Main equipment is from the read back data of described length of data-interface;

Slave unit returns to main equipment with described readback data.