CN101099360B - Bus system and method for operating the same - Google Patents
Bus system and method for operating the same Download PDFInfo
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- CN101099360B CN101099360B CN2006800016732A CN200680001673A CN101099360B CN 101099360 B CN101099360 B CN 101099360B CN 2006800016732 A CN2006800016732 A CN 2006800016732A CN 200680001673 A CN200680001673 A CN 200680001673A CN 101099360 B CN101099360 B CN 101099360B
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Abstract
The present invention relates to a bus system for a real-time communication between the high units (11, 13) and at least a secondary unit. The bus system is used to exchange the address and data information through the bus (15). The invention provides other field (44) between the fields (42, 43) for a rapid message exchange.
Description
Technical field
The present invention relates to bus system, relate in particular to a kind of serial radio control bus (RCBSER), it is used for real-time control example such as exterior antenna tuner, amplifier and filter etc.
Background technology
In serial bus system, be the process of a standard based on the Message Processing of storing message transfer.Message is transferred to another bus node from a bus node, and the message of the current bus node of handling is by priority treatment.Using such node associated transport of message, real-time capacity can't be provided, because the processing time of the message in the bus node memory is unpredictable, is can obtain statistics ground to show at the most.
Compare with synchronous bus, wherein certain part of synchronizing channel is assigned to specific node in section sometime, and asynchronous being controlled at do not need to allow a plurality of requests of transmission request low volume data under the situation that transmission of messages interrupts.Document US 5,719,858 and EP 1465370 A1 have proposed the system that permission is carried out asynchronous transmission based on synchronous physical channel.Therefore, become possibility for the transmission between two nodes provides a kind of environment, this environment also can satisfy the urgent requirement about time conditions.For example, at US 5,719, under 858 the situation, several nodes are connected to TDM (time division multiplexing) bus, make a certain bandwidth can use several bus nodes on this bus.Then, utilize the timeslice method to give each unit with this allocated bandwidth.Under the situation of EP 1465370 A1, in order to carry out asynchronous process,, and packagedly advance in so-called " clock frame ", so can allow to become in the enterprising line asynchronous transfer of data of synchronous bus with a data message segmentation.
The Manchester's code method is the standard method of setting up for bus system.This method is easy to realize, not influenced by direct current and allows the website of mutual communication to carry out automatically synchronously, so, do not need to provide independently clock pulse.
Summary of the invention
The objective of the invention is the communication in the accelerate bus system, thereby improve the real-time capacity of bus system.
This purpose can be by having claim 1 the bus system of feature and the method with feature of claim 11 realize.
In serial bus system, can be by synchronizing signal real-time exchange bit information between each unit, parallel is can transmit with asynchronous system than the message of length therewith.
In this bus system, the bus node of central bus node or signalment is defined as higher level (superordinate) unit, link to each other with several other nodes that are defined as subordinate (subordinate) unit by bus, communicate by slave unit.
Especially, synchronizing signal constantly exchanges between each unit, and signal it is pressed for time is transferred to another unit with this synchronizing signal from a unit.Parallel therewith is, the message of finite length can be between each unit asynchronously and be totally independent of synchronizing signal and transmit or exchange.
The benefit that further expands is elaborated in the dependent claims.
Know that in information system, except that address and data message, head can also be attached in the data message of message system, this permission receiver carries out in order to receive message synchronously in this example.This message is described in following described realization, for example is described with 24 fields, and wherein, 13 fields are used for address information, and 8 fields are used for data.13 fields that are used for address information are not only indicated the address of each slave unit, also determine parameter adopted or to be revised in each servicing unit.
Message header not only indicates the beginning of message, also is used for the synchronous of unit.This character string also can be called synchronization character, allows the beginning part of receiver identification data word subsequently.
In order to allow the initial synchronisation between each unit, at first transmit a so-called synchronization frame.This has guaranteed the mutual calibration of public clock pulse, and the distribution of message field being distributed to their coding.If there is not the transmission of message or data message, synchronization frame constantly is transferred to next unit from a unit.This has also just guaranteed the synchronous of clock pulse generator.
The real-time exchange of information is based on the bit signal that constantly exchanges between each unit, or clock pulse signal.The initial transmission of synchronization frame has specified character ' X ' to ' 0 ' or ' 1 ' and ' Y ' distribution to ' 0 ' or ' 1 '.This information is transferred to all unit on the serial bus system, so that identical signal is transferred on all connecting lines.If a bit message is wished to transmit to the higher level unit in unit, this has just changed ' X ' to ' 0 ' or ' 1 ' and/or ' Y ' distribution to ' 0 ' or ' 1 '.In the unit of back, this signal combines with the clock pulse signal of self, is integrated in the AND element, with the formation composite signal, and is transferred to the unit of arranging in next extreme higher position.Like this, a bit signal can be transferred to another unit from a unit apace, until master unit.The packet that is independent of bit information arrives the intermediate bit position by bit distribution, so that packet transmits with clock pulse signal with asynchronous system.Therefore, can refer to passage, in this passage, on the one hand, bit information can be by real-time exchange constantly, and on the other hand, Chang message can be utilized the time to distribute to carry out asynchronous transmission relatively.
In addition, because bit information is not placed in intermediate store, therefore, can also further provide real-time capacity.Bit signal is by carrying out being incorporated in the unit as continuous signal after AND is connected with bit signal that inside generates, and execution at once.Data message must be extracted out at first, and is read into memory with whole length, so that understood.
The use of Differential Manchester Encoding allows field, and each is represented with a bit, thereby makes that the message-length that obtains at last is 48 bits, and the length of data and address information is designated as 8 and 13 bits respectively.With different is in the normally used coding method of this introduction, allow the other character of definition, with regard to them, allow the other control character of definition.By with comprise ' K ', ' J ', ' 0 ' and ' 1 ' standard alphabetic different, ' READY ', ' TX_ACTIVE ' and ' CARRIER_MAGNITUDE ' can create by the character that adds or control signal ' X ', ' Y '.
For for example message transfer in the slave unit that is linked in sequence by coaxial cord or optical fiber cable, a memory is provided in each servicing unit, wherein message was placed into intermediate store before transmission, therefore, guaranteed the controlled messages transmission from the slave unit to the slave unit.In addition, corresponding logical block provides and has been used for handling the message of slave unit or is used for the means of message transfer to another slave unit.Memory and logical block can realize by for example use programmable gate array (FPGA assembly) in device, thereby permission is at the distant view demand of bus performance ability to be considered.
Integrated memory and logical block is provided, realized being used to handle the transmission course of the standard message of following type and message it is pressed for time:
1), at first detects to determine whether internal storage has comprised message if slave unit receives message.If memory has comprised message, then the message of receiving is input in the memory, and only all message that formerly receive or the message that is input to memory be transferred to subsequently slave unit or when memory removes, just can be transmitted.
2) if received message and memory for empty from slave unit, then this message is directly transmitted.
3) if receive it is pressed for time message from slave unit, the state of detection of stored device not then, but Direct Test internal state, and only after the check internal state, just transmit this message.
4) if received TX_ACTIVE or TX_ACTIVE/CARRIERMAGNITUDE message from the higher level unit, the setting of slave unit no longer changes, and internal state is set.After the message that receives from slave unit formerly, this message is transferred to slave unit subsequently immediately.
Utilize this general message basic framework, basic functions can be provided, wherein be connected in each slave unit of bus termination, communicate by universal serial bus and higher level unit.In this article, can provide about successfully adjusting the answer message of parameter, or the state of slave unit or for example the value of temperature can be transferred to the higher level unit.Clock pulse signal by continuous exchange comes transmitted bit message, and this also allows the real-time quick exchange of information unit in addition.
Description of drawings
Below with reference to accompanying drawing the present invention is described in further detail.Described accompanying drawing is as follows:
Fig. 1 a shows the structure of universal serial bus;
Fig. 1 b shows the structure of slave unit;
Fig. 2 shows a kind of application of bus;
Fig. 3 shows the message structure of standard;
Fig. 4 shows the message structure of the quick transmission that is used for message;
Fig. 5 shows Differential Manchester Encoding;
Fig. 6 shows the time response that is used for the message of quick transmission on bus;
Fig. 7 a shows the message between the phase I slave unit;
Fig. 7 b shows the message between the second stage slave unit;
Fig. 8 a shows the message that is used for quick transmission on bus in the phase I;
Fig. 8 b shows the message that is used for quick transmission on bus in second stage;
Fig. 9 shows the message that is used for quick transmission on bus in the phase III;
Figure 10 shows specific message it is pressed for time;
Figure 11 shows the time response in the transmission of messages of phase I; And
Figure 12 shows the time response in the transmission of messages of second stage.
Embodiment
The structure of the bus system 1 shown in Fig. 1 a and Fig. 1 b is by higher level unit 1
1Obtained embodiment, this higher level unit can be connected with a plurality of slave units 1
2, 1
3 Slave unit 1
2, 1
3Connected in series, form serial structure.In this article, for example the first slave unit UE4 of preselector is connected to for example higher level unit UE of radio device by two cables, and then, for example the second slave unit UE3 of standing-wave meter is connected to first slave unit by other two cables, or the like.Last slave unit UE1, for example antenna tuner (ATU) appears at bus 1
5Ending.
The replaceable coaxial cable of optical fiber cable and optical connector is as cable 1
4Although bus system 1 mainly designs in order to control external module, notion described below also is suitable for the application scenario of needs control internal module.By simplifying, write a Chinese character in simplified form RCBSER and also be used to describe bus 1
5Must should be mentioned that each device unit 1
1, 1
2And 1
3Have self for example programmable gate array (FPGA assembly) of domination arbitrarily respectively, it comprises memory 1
211, and by total line traffic control communication.
As shown in Figure 3, standard message 3 comprises message header 3
3, this message header 3
3Form by initial bits ' J ', the initial bits ' K ' of following and a status bits subsequently.Status bits can be by character RD/WR_RF or IRQ_RF_EXT definition, and depending on transmission is to realize to slave unit from the higher level unit, still realizes in opposite direction.Next be address field 3
1With data field 3
2In the message structure of representing with example, 13 bits are used for address field, and 8 bits are used for data field.
Fig. 4 shows in the free position between clock pulse bit or character message is carried out segmenting by bit.Clock pulse signal can be identified as the alternating series of character ' X ' and ' Y '.Below the coding that Differential Manchester Encoding at first is used to character will be described.In this article, character ' X ' can be identified, because it appears between first and second initial bits or synchronization bit ' K ' and ' J '.The back at initial bits or synchronization bit ' J ' followed in character ' Y '.Result as pressing bit segmentation message compares with the message of asynchronous transmission between the unit, can simultaneously and be totally independent of universal serial bus exchange bit information.The staggered insertion of character ' X ' and ' Y ' can be estimated immediately.The bit message of the clock pulse signal transmission by continuous exchange is also can be shown as signal it is pressed for time.
Fig. 5 shows the structure of preferred Manchester's code method 5.According to method 5, the segmentation of bit cell has appearred being subdivided into, wherein by with bit cell back half compare, the first half of bit cell shows different polarity or amplitude.This means the sudden change that level has taken place in each bit cell, this also allows for example to participate in the simple synchronization of each side.In this article, the difference of character produces by the edge that bit begins to locate.For example, character ' 0 ' characterizes by the edge that bit begins to locate, and under the situation of character ' 1 ', does not have the edge to be encoded.According to the advantageous variant of existing Manchester's code, two code expansions ' K ' and ' J ' are applied to coded identification extraly and are concentrated, and that is to say to be applied in a large amount of adopted characters.In this article, providing the code that does not have change in polarity or level flip-flop to occur in the bit centre expands.Character ' K ' characterizes by the edge that bit begins to locate, and character ' J ' characterizes by begin place's ' not having the edge ' at bit.
Fig. 6 shows the time response or the sequential 6 of message packet, also is the time response or the sequential of message packet 4 it is pressed for time specifically.The 12.5MHz data rate of usage example, every than peculiar T
BThe time of=80ns distributes, and therefore whole length of message it is pressed for time are T
M=3.84 μ s (=24 * 80ns).This just provides 1% tolerance bandwidth for the safe handling of message.
Fig. 7 a and Fig. 7 b show standard message and handle.Fig. 7 a shows and utilizes memory 1
211Carry out the processing of standard message.
From higher level unit 1
1To slave unit 1
2And/or 1
3 Standard message 3 by slave unit 1
2And/or 1
3Receive simultaneously.This transmission of messages is described with the connection of point-to-multipoint.
Two kinds of methods may be used to handle standard message 3.Fig. 7 a and Fig. 7 b have described the method for operation.Fig. 7 a shows first kind of situation, and wherein, slave unit UEn receives message N by point-to-point connection from slave unit UEn-1
1, and by message N
2Represent, and check the message memory 1 of himself
211Whether be empty.If situation is true, message N then
3Directly transferred to the memory of slave unit UEn+1 subsequently.
Fig. 7 b shows second kind of situation.If memory 1
211Comprised at least one message, the message N that receives
4Be stored in memory 1
211In, be included in memory 1 up to all
211In message successfully handled, and after only the message of all in memory is successfully handled, just can be used as message N
6Be transferred to slave unit UEn+1 subsequently.Message N
4At memory 1
211In the time of staying depend on memory 1
211The initial number of middle message.
The processing procedure of signal 4 it is pressed for time is shown in Fig. 8 a and Fig. 8 b, if desired or may carry out the individual processing of message and quick exchange with the bit information form time, and urgent signal 4 of transmission time.For example, if be used for high-frequency signal transmission the same to the higher level unit UE of slave unit UE1～UE4, radio device transmits given settings such as being provided with of for example amplification factor, filter parameter or antenna tuner, and before transmission beginning, ask the affirmation that successfully is provided with about desired parameters soon, so that subsequently can transmitting high-frequency signal, just urgent signal 4 of transmission time.Then, this affirmation is transferred to higher level unit UE with the form of it is pressed for time signal 4 from slave unit UE1～UE4.Transmission is carried out with such form: bus 1
5Last element UE1 first change the coding of its clock pulse signal.Compare the coverlet reason of staying alone in the slave unit that signal is it is pressed for time passed through in transmission with standard message.
The first kind of method in common that provides is provided Fig. 8 a.If in Fig. 8 a, pass through N
7Expression, arrive slave units 1 at the signal it is pressed for time 4 of front unit UE2
2As for the higher level unit to all or only several slave unit UE1～UE4 (for example, to slave unit UE3) the result in preceding message of high-frequency transmission, internal state ready (READY) is the most detected, signal 4 is as it is pressed for time message N of collective then
8Be transferred to slave unit UE3 subsequently, or in the end be transferred to higher level unit UE under the situation of a slave unit UE4.
Fig. 8 b shows and is relating to the specific T X_ACTIVE signal 10 of high-frequency signal transmission on the horizon
1Processing procedure during generation.In this variation, all slave unit UE1～UE4 expect READY signal 10
3, and this signal for example is transferred to slave unit UE4 from slave unit UE3, is transferred to higher level unit UE then.
In this article, transmission is carried out by this way: higher level unit UE transmission signals N
9To slave unit UEn.Internal state is set to READY, and waits for bus 1
5In come comfortable before the signal N of slave unit UEn-1
10After the inquiry internal state, transmit a composite signal N
11To slave unit UEn+1.
Fig. 9 shows further signal processing flow.Slave unit UEn receives the signal N from higher level unit UE
12When using bus 15, this relates to the reception of the TX_ACTIVE/CARRIER_MAGNITUDE signal of describing direct transmission mode.Then, internal state is by the (not shown) that is provided with of selectivity.Afterwards, if from receiving signal N at preceding slave unit UEn-1
13, then generate signal N
14And be transferred to slave unit 1
2
Figure 10 shows three signal specific, is specifically to be transferred to slave unit UE1～UE4 and to transfer to the signal it is pressed for time 10 of central location UE from slave unit UE1～UE4 from higher level unit UE
1, 10
2With 10
3In this article, first signal 10 from higher level unit UE to all slave unit UE1～UE4
1Feature be that this signal is encoded as the constant series of character ' X ' as clock pulse signal.Figure 10 shows real-time bit information and the relative parallel exchange of long packet again.The feature of character TX_ACTIVE is, as the signal 10 from higher level unit UE to slave unit UE1～UE4
1Transmission.Secondary signal 10 from higher level unit UE to slave unit UE1～UE4
2Also use clock pulse signal to transmit.Yet, TX_ACTIVE and CARRIER_MAGNITUDE alternate transmission.In this article, CARRIER_MAGNITUDE is as ' Y ' transmission.Guaranteed the calibration of clock pulse generator again in preamble frame.Under the situation of the READY signal from slave unit UE1～UE4 to higher level unit UE, the READY signal transmits in the above described manner.
Figure 11 and Figure 12 show the general picture of bus activity with the time vector diagram form, and it is used for by bus 1
5Slave unit UE1～the UE4 of last connection comes urgent signal of transmission time to higher level unit UE.Length in bus top-ranking unit is T
MRequest and after predetermined response time of last or terminal slave unit UE1, according to above-mentioned point-to-point signal processing mode, the signal that about parameter the result is set in the slave unit is transferred to slave unit UEn from slave unit UEn-1, and arrives higher level unit UE at last.Then, acquisition total response time as shown in figure 11.The estimation that Figure 12 shows internal state needs the situation of entire message duration.
The present invention is not limited to above-mentioned exemplary embodiment.Can use in a different manner according to bus system of the present invention.All above-mentioned and elements that indicate can merge mutually in needs.
Claims (14)
1. a bus system is used for higher level unit (1
1) and one or more slave units (1
2, 1
3) by bus (1
5) real time communication of IA interchange address and data message, it is characterized in that,
For the quick exchange of message, the field (4 that is being used for address and data message
2, 4
3) between provide other field (4
4);
The head (4 of data block
1) comprise a plurality of synchronization field (4
5) and at least one be used to represent the field (4 of message status
6), described a plurality of synchronization field (4
5) and at least one be used to represent the field (4 of message status
6) be placed in the field (4 that is used for address and data message
2, 4
3) before, wherein data message (4
3) follow in address information (4
2) afterwards;
In view of comprising address, data, synchronously and the field (4 of state information
2, 4
3, 4
5, 4
6), comprise the other field (4 of an other character
4) be disposed in after each character of described data block (4), and these fields are by character ' X ' and ' Y ' alternately definition.
2. bus system as claimed in claim 1 is characterized in that,
The field (4 that is used for the quick exchange of message
4) be used for the field (4 of address and data message
2, 4
3) arranged alternate.
3. bus system as claimed in claim 1 is characterized in that,
Described data block (4) is made up of 48 fields, wherein said address, data, synchronously and state information respectively by 13 characters, 8 characters, 2 characters and 1 character representation.
4. bus system as claimed in claim 3 is characterized in that,
Bitwise to each field (4
2, 4
3, 4
4, 4
5, 4
6) encode synchronization field (4
5), mode field (4
6), address information (4
2) and data message (4
3) correspondingly represent with 2 bits, 1 bit, 13 bits and 8 bits respectively.
5. as each described bus system in the claim 1 to 4, it is characterized in that,
Each slave unit (1
2, 1
3) have a memory (1
211), slave unit (1
2) by bus (1
5) connection higher level unit (1
1) and the ending slave unit (1
3).
6. as each described bus system in the claim 1 to 4, it is characterized in that,
Described data block (4) is in bus (1
5) on signal or transmission of messages by coaxial cable or optical fiber cable (1
4) carry out.
7. bus system as claimed in claim 4 is characterized in that,
Described bits of encoded realizes by Differential Manchester Encoding (5).
8. as each described bus system in claim 1 to 4 and 7, it is characterized in that,
Described higher level unit (1
1) be radio device (2
1), described slave unit is one or more servicing units (2
2, 2
3).
9. bus system as claimed in claim 8 is characterized in that,
Described servicing unit (2
2) be amplifier, standing-wave meter, frequency selector or automatic antenna tuner (2
3).
10. the method for an operator trunk system, this bus system is used for higher level unit (1
1) and one or more slave units (1
2, 1
3) IA interchange address information and data message and the real time communication that exchanges other message, this method comprises following treatment step:
Whenever first slave unit (1
2) from second slave unit (1
3) when receiving message, check this first slave unit (1
2) internal storage (1
211) whether comprise message;
If described memory (1
211) comprised message, then received message is input to memory (1
211) in, and have only receive before all or be input to memory (1
211) message be transferred to described first slave unit (1
2) time, just transmit this message; And
Whenever from described first slave unit (1
2) receive message and memory (1
211) when being empty, directly transmit this message;
If from described second slave unit (1
3) receive real-time messages, detection of stored device (1 not then
211) state, but the Direct Test internal state if this state is READY, then transmits this message.
11. method as claimed in claim 10 is characterized in that,
The quantity of all real-time messages comprises at least three message, promptly introduces the TX_ACTIVE message (10 of transmission mode
1), the TX_ACTIVE/CARRIER_MAGNITUDE message (10 of this transmission mode of mark
2) and the READY message (10 of mark ready state
3).
12. method as claimed in claim 11 is characterized in that,
Described TX_ACTIVE message (10
1) and TX_ACTIVE/CARRIER_MAGNITUDE message (10
2) from higher level unit (1
1) be transferred to slave unit (1
2, 1
3), described higher level unit (1
1) be radio device, described slave unit (1
2, 1
3) be the servicing unit of radio device, and described READY message (10
3) from a slave unit (1
3) transfer to slave unit (1 subsequently
2), up to the direct-connected last slave unit (1 in higher level unit
2) with this transmission of messages to higher level unit (1
1).
13. method as claimed in claim 12 is characterized in that,
If servicing unit (2
2, 2
3) from radio device (2
1) receive TX_ACTIVE message or TX_ACTIVE/CARRIER_MAGNITUDE message (10
1, 10
2), then all current adjustment processes all stop.
14. method as claimed in claim 13 is characterized in that,
After adjustment process stops, described servicing unit (2
3) internal state be set to READY, and from another servicing unit (2
3) receive READY message (10
3) afterwards, this READY state transfers to servicing unit (2 subsequently immediately
2) or radio device (2
1).
Applications Claiming Priority (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DE102005009495 | 2005-03-02 | ||
| DE102005009495.3 | 2005-03-02 | ||
| DE102005034652.9 | 2005-07-25 | ||
| DE102005034652A DE102005034652B4 (en) | 2005-03-02 | 2005-07-25 | Bus system and method for operating the bus system |
| PCT/EP2006/001161 WO2006092201A2 (en) | 2005-03-02 | 2006-02-09 | Bus system and method for operating the same |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101099360A CN101099360A (en) | 2008-01-02 |
| CN101099360B true CN101099360B (en) | 2011-10-26 |
Family
ID=39012140
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2006800016732A Expired - Fee Related CN101099360B (en) | 2005-03-02 | 2006-02-09 | Bus system and method for operating the same |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN101099360B (en) |
| ZA (1) | ZA200704981B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE102010041368A1 (en) * | 2010-09-24 | 2012-04-19 | Robert Bosch Gmbh | Method and subscriber station for the optimized transmission of data between subscriber stations of a bus system |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5687356A (en) * | 1992-06-22 | 1997-11-11 | International Business Machines Corporation | Hub and interface for isochronous token ring |
| US6205119B1 (en) * | 1997-09-16 | 2001-03-20 | Silicon Graphics, Inc. | Adaptive bandwidth sharing |
| CN1297192A (en) * | 2000-12-26 | 2001-05-30 | 北京和利时系统工程股份有限公司 | In-situ implementation method for site software of bus peripherals |
| US6504849B1 (en) * | 1997-05-15 | 2003-01-07 | Cypress Semiconductor Corporation | Fiber auto-negotiation |
-
2006
- 2006-02-09 ZA ZA200704981A patent/ZA200704981B/en unknown
- 2006-02-09 CN CN2006800016732A patent/CN101099360B/en not_active Expired - Fee Related
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5687356A (en) * | 1992-06-22 | 1997-11-11 | International Business Machines Corporation | Hub and interface for isochronous token ring |
| US6504849B1 (en) * | 1997-05-15 | 2003-01-07 | Cypress Semiconductor Corporation | Fiber auto-negotiation |
| US6205119B1 (en) * | 1997-09-16 | 2001-03-20 | Silicon Graphics, Inc. | Adaptive bandwidth sharing |
| CN1297192A (en) * | 2000-12-26 | 2001-05-30 | 北京和利时系统工程股份有限公司 | In-situ implementation method for site software of bus peripherals |
Also Published As
| Publication number | Publication date |
|---|---|
| CN101099360A (en) | 2008-01-02 |
| ZA200704981B (en) | 2008-11-26 |
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