CN101098181A - Method for controlling time-delay stability of time service type satellite receiver - Google Patents
Method for controlling time-delay stability of time service type satellite receiver Download PDFInfo
- Publication number
- CN101098181A CN101098181A CNA200610018025XA CN200610018025A CN101098181A CN 101098181 A CN101098181 A CN 101098181A CN A200610018025X A CNA200610018025X A CN A200610018025XA CN 200610018025 A CN200610018025 A CN 200610018025A CN 101098181 A CN101098181 A CN 101098181A
- Authority
- CN
- China
- Prior art keywords
- time delay
- delay control
- control circuit
- time
- tracking loop
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Abstract
The invention discloses a time delay stability control method of time service satellite receiver, comprising an analogue receiving channel time delay control circuit, a digit receiving channel time delay control circuit, a frequency mark synthesis circuit, and data processing time delay control circuit, wherein the input of the analogue receiving channel time delay control circuit is connected to the digit receiving channel time delay control circuit respectively connected with the frequency mark synthesis circuit and the data processing time delay control circuit, the frequency mark synthesis circuit is connected with the data processing time delay control circuit. The invention considers the effect of each element on time delay stability, to provide an integral time delay control method for the digit receiving channel, data processing time delay control, and analogue receiving channel time delay control portions, to confirm the time delay stability of satellite receiver. The time delay index of the time service satellite receiver is improved from 100ns to 10ns.
Description
Technical field
The present invention relates to a kind of delay stability of time control method, relate to a kind of method for controlling time-delay stability of time service type satellite receiver specifically.
Background technology
The split-second precision benchmark is one of important basic guarantee platform in fields such as communication, electric power, traffic and national defense construction.Along with the develop rapidly of modern information technologies, more and more higher to the requirement of high accuracy time service.The special industry timing tracking accuracy has now reached the nanosecond requirement, influences a delay stability of time that key factor is a receiver of time service precision, so satellite Timing Receiver delay stability of time is proposed requirements at the higher level.And traditional homemade Timing Receiver can not satisfy this required precision.
For satisfying requirements such as the synchronous desired precision height of temporal frequency, wide coverage, generally adopt import GPS time service type receiver at present.GPS time service type receiver is widely used in all trades and professions of China, make China face huge potential potential safety hazard, the high accuracy time-frequency product of being badly in need of China's independent intellectual property right comes progressively to substitute GPS time service type receiver, to satisfy the needs of Chinese national economy and national defense construction.
At present, from time service type satellite receiver design angle commonly used both at home and abroad, delay stability of time is mainly reflected in digital received channel time delay control section, data processing time delay control section and simulation receive path time delay control section.Tradition time service type satellite receiver concentrates on data processing time delay control section to the delay stability of time control technology, pays close attention to satellite clock correction calibrated error, Satellite Orbit Determination error, ionosphere correction residual error, troposphere correction residual error equal error treatment technology; Wait the level and smooth and treatment technology of observed quantity based on carrier wave ring and sign indicating number ring, thereby make time service precision satisfy certain index, make the time delay calibrated error satisfy index request, but the time delay stability differs bigger between each time service type satellite receiver.
The simulation receive path time delay control section of tradition time service type satellite receiver adopts Surface Acoustic Wave Filter (SAWF) more.SAWF be a kind of utilize that surface acoustic wave effect and resonance characteristic make frequency is had the device of selection.SAWF have volume little, in light weight, can handle in real time signal, analog/digital compatibility, characteristics such as anti-electromagnetic interference performance is good, loss is low and frequency selectivity is good.Therefore since the practicability sixties in surface acoustic wave techniques to 20 century, developed greatly, be widely used in fields such as range finding, location, navigation.But Surface Acoustic Wave Filter has very big time delay, has a strong impact on channel time delay stability.
Summary of the invention
Purpose of the present invention just is a kind of method for controlling time-delay stability of time service type satellite receiver that precision is more accurate, delay stability of time is higher.
Purpose of the present invention can realize by following measure:
The present invention includes simulation receive path time delay control circuit, digital received channel time delay control circuit, the time frequency marking combiner circuit, data processing time delay control circuit, wherein, simulation receive path time delay control circuit is input to digital received channel time delay control circuit, frequency marking combiner circuit and data processing time delay control circuit when digital received channel time delay control circuit is connected respectively to, the time frequency marking combiner circuit also be connected with data processing time delay control circuit; Simulation receive path time delay control circuit wherein is to be made of the rf inputs that is serially connected successively, one-level low noise amplifier, one-level dielectric filter, secondary low noise amplifier, frequency mixer, local oscillator, one-level operational amplifier, one-level LC filter, two-level operating amplifier and secondary LC filter, medium frequency output end; Wherein, digital received channel time delay control section mainly comprises pseudo range measurement error robustness control method and digital synchronization control method, and pseudo range measurement error robustness control method adopts code tracking loop and carrier tracking loop simultaneously; Adopt the carrier wave householder method in the design of code tracking loop, carrier tracking loop adopts multistage phase-locked loop (PLL) steady track method.
Carrier tracking loop adopts multistage phase-locked loop (PLL) and the auxiliary steady track method of multistage FLL (FLL) among the present invention.Carrier tracking loop adopts 2 rank FLL to assist 3 rank phase-locked loop (PLL) steady track methods.Perhaps, carrier tracking loop adopts 3 rank FLL to assist 5 rank PLL steady track methods.The code tracking loop adopts the relevant and wide district correlation technique in narrow district.
The present invention is owing to adopt foregoing circuit and method, take all factors into consideration satellite receiver and receive, handle each link influence that delay stability of time brought, proposition can guarantee the delay stability of time problem of satellite receiver to digital receive path part, data processing time delay control section and the comprehensive delay control method of simulation receive path time delay control section.The time delay index that makes traditional time service type satellite receiver is promoted in 10 ns by 100ns.
Description of drawings
Fig. 1 is a schematic block circuit diagram of the present invention;
Fig. 2 is the schematic block circuit diagram of simulation receive path time delay control circuit among the present invention;
Fig. 3 is the schematic block circuit diagram of carrier tracking loop in the digital received channel time delay control circuit among the present invention.
Embodiment
The present invention does with detailed description below in conjunction with drawings and Examples:
Embodiment 1:
As shown in the figure, the present invention includes simulation receive path time delay control circuit, digital received channel time delay control circuit, the time frequency marking combiner circuit, data processing time delay control circuit, wherein, simulation receive path time delay control circuit is input to digital received channel time delay control circuit, frequency marking combiner circuit and data processing time delay control circuit when digital received channel time delay control circuit is connected respectively to, the time frequency marking combiner circuit also be connected with data processing time delay control circuit; Simulation receive path time delay control circuit wherein is to be made of the rf inputs that is serially connected successively, one-level low noise amplifier, one-level dielectric filter, secondary low noise amplifier, frequency mixer, local oscillator, one-level operational amplifier, one-level LC filter, two-level operating amplifier and secondary LC filter, medium frequency output end; Wherein, digital received channel time delay control section mainly comprises pseudo range measurement error robustness control method and digital synchronization control method, and pseudo range measurement error robustness control method adopts code tracking loop and carrier tracking loop simultaneously; Adopt the carrier wave householder method in the design of code tracking loop, carrier tracking loop adopts multistage phase-locked loop (PLL) steady track method.
Operation principle of the present invention is as follows: the present invention is different from traditional time service type satellite receiver, from digital received channel part, data processing time delay control section and simulation receive path time delay control section three parts, Comprehensive Control satellite receiver time delay improves its stability greatly.Wherein:
Digital received channel time delay control section:
Digital received channel part delay stability of time technology mainly comprises pseudo range measurement error robustness control technology and digital synchronization control technology.
Employing carrier wave ancillary technique in the design of code tracking loop, blanking code gyration attitude makes a sign indicating number gyration attitude stress error to ignore, and adopts the relevant and wide district correlation technique assurance tracking accuracy in narrow district simultaneously.
Carrier tracking loop adopts the method for designing of the auxiliary 3 rank PLL steady tracks of 2 rank FLL, under identical equivalent noise bandwidth, second-order F LL is than what a magnitude of dynamic stress performance of three rank PLL, therefore under dynamic environment, during the loop first closure and during the dynamic stress, follow the tracks of with FLL, return the PLL mode in stable state with under hanging down dynamically.
Sign indicating number ring, carrier tracking loop adopt said method, guarantee that tracking accuracy satisfies certain index request to guarantee the pseudo range measurement error, can satisfy the requirement of delay stability of time from face.The digital received channel time delay that is caused by the cascade of digital operation in addition can guarantee the stability of interchannel time delay by the synchronization design.
Simulation receive path time delay control section:
Simulation receive path part is because the hardware temperatures characteristic causes the time delay temperature to float error, its time delay is mainly caused by filter, amplifier etc., by the device screening of strictness, guarantee the analogue device temperature characterisitic, comprehensively reduce the temperature drift error from the following aspects in design simultaneously:
Filter is introduced time delay
A) introduce time delay hardly because of high-quality dielectric filter, and have high delay stability of time, can use.
B) Surface Acoustic Wave Filter has very big time delay, usually about 1000nS, even therefore its stability reaches 1/1000 and also can not use.
C) time delay of LC filter is relevant with its exponent number, as: 80MHz (center) 30MHz (bandwidth) 5 rank Butterworth filter time delays are about 12nS.High-quality LC device time delay variable quantity can use less than 0.05nS (30 degrees centigrade).Time delay and variable quantity thereof improve with filter order and increase, and therefore need the appropriate design filter parameter.
Amplifier is introduced time delay
Amplifier will be introduced phase lag at high band, cause time delay.We can select the big device of GB (gain bandwidth product) value for use, make the frequency working point (working band) of amplifier away from 3dB high-frequency cut-off point.
For example: the phase lag angle of getting amplifier is 5 degree, and the time delay of 0.17nS is arranged approximately for the signal of 80MHz at this moment, and when causing that when 30 degrees centigrade of variations in temperature the phase lag angle changes 10%, its time delay variable quantity is 0.017nS.
Embodiment 2
The present invention includes simulation receive path time delay control circuit, digital received channel time delay control circuit, the time frequency marking combiner circuit, data processing time delay control circuit and clock circuit, wherein, simulation receive path time delay control circuit is input to digital received channel time delay control circuit, frequency marking combiner circuit and data processing time delay control circuit when digital received channel time delay control circuit is connected respectively to, the time frequency marking combiner circuit also be connected with data processing time delay control circuit; Simulation receive path time delay control circuit wherein is to be made of the rf inputs that is serially connected successively, one-level low noise amplifier, one-level dielectric filter, secondary low noise amplifier, frequency mixer, local oscillator, one-level operational amplifier, one-level LC filter, two-level operating amplifier and secondary LC filter, medium frequency output end; Wherein, the digital received channel part mainly comprises pseudo range measurement error robustness control method and digital synchronization control method, and pseudo range measurement error robustness control method adopts code tracking loop and carrier tracking loop simultaneously; Adopt the carrier wave householder method in the design of code tracking loop, carrier tracking loop adopts multistage phase-locked loop (PLL) steady track method.
Carrier tracking loop adopts multistage phase-locked loop (PLL) and the auxiliary steady track method of multistage FLL (FLL) among the present invention.
Its operation principle is with embodiment 1.
Embodiment 3
The present invention includes simulation receive path time delay control circuit, digital received channel time delay control circuit, the time frequency marking combiner circuit, data processing time delay control circuit and clock circuit, wherein, simulation receive path time delay control circuit is input to digital received channel time delay control circuit, frequency marking combiner circuit and data processing time delay control circuit when digital received channel time delay control circuit is connected respectively to, the time frequency marking combiner circuit also be connected with data processing time delay control circuit; Simulation receive path time delay control circuit wherein is to be made of the rf inputs that is serially connected successively, one-level low noise amplifier, one-level dielectric filter, secondary low noise amplifier, frequency mixer, local oscillator, one-level operational amplifier, one-level LC filter, two-level operating amplifier and secondary LC filter, medium frequency output end; Wherein, the digital received channel part mainly comprises pseudo range measurement error robustness control method and digital synchronization control method, and pseudo range measurement error robustness control method adopts code tracking loop and carrier tracking loop simultaneously; Adopt the carrier wave householder method in the design of code tracking loop, carrier tracking loop adopts multistage phase-locked loop (PLL) steady track method.
Carrier tracking loop adopts carrier tracking loop to adopt 2 rank FLL to assist 3 rank phase-locked loop (PLL) steady track methods among the present invention.
Its operation principle is with embodiment 1.
Embodiment 4
The present invention includes simulation receive path time delay control circuit, digital received channel time delay control circuit, the time frequency marking combiner circuit, data processing time delay control circuit and clock circuit, wherein, simulation receive path time delay control circuit is input to digital received channel time delay control circuit, frequency marking combiner circuit and data processing time delay control circuit when digital received channel time delay control circuit is connected respectively to, the time frequency marking combiner circuit also be connected with data processing time delay control circuit; Simulation receive path time delay control circuit wherein is to be made of the rf inputs that is serially connected successively, one-level low noise amplifier, one-level dielectric filter, secondary low noise amplifier, frequency mixer, local oscillator, one-level operational amplifier, one-level LC filter, two-level operating amplifier and secondary LC filter, medium frequency output end; Wherein, the digital received channel part mainly comprises pseudo range measurement error robustness control method and digital synchronization control method, and pseudo range measurement error robustness control method adopts code tracking loop and carrier tracking loop simultaneously; Adopt the carrier wave householder method in the design of code tracking loop, carrier tracking loop adopts multistage phase-locked loop (PLL) steady track method.
Carrier tracking loop adopts 3 rank FLL to assist 5 rank PLL steady track methods among the present invention.
Its operation principle is with embodiment 1.
Embodiment 5
The present invention includes simulation receive path time delay control circuit, digital received channel time delay control circuit, the time frequency marking combiner circuit, data processing time delay control circuit and clock circuit, wherein, simulation receive path time delay control circuit is input to digital received channel time delay control circuit, frequency marking combiner circuit and data processing time delay control circuit when digital received channel time delay control circuit is connected respectively to, the time frequency marking combiner circuit also be connected with data processing time delay control circuit; Simulation receive path time delay control circuit wherein is to be made of the rf inputs that is serially connected successively, one-level low noise amplifier, one-level dielectric filter, secondary low noise amplifier, frequency mixer, local oscillator, one-level operational amplifier, one-level LC filter, two-level operating amplifier and secondary LC filter, medium frequency output end; Wherein, the digital received channel part mainly comprises pseudo range measurement error robustness control method and digital synchronization control method, and pseudo range measurement error robustness control method adopts code tracking loop and carrier tracking loop simultaneously; Adopt the carrier wave householder method in the design of code tracking loop, carrier tracking loop adopts multistage phase-locked loop (PLL) steady track method.
Carrier tracking loop adopts multistage phase-locked loop (PLL) and the auxiliary steady track method of multistage FLL (FLL) among the present invention.Carrier tracking loop adopts auxiliary 3 rank phase-locked loop (PLL) steady track methods of 2 rank FLL or the auxiliary 5 rank PLL steady track methods of 3 rank FLL.The code tracking loop adopts the relevant and wide district correlation technique in narrow district.
Claims (5)
1, a kind of method for controlling time-delay stability of time service type satellite receiver, it is characterized in that: it comprise simulation receive path time delay control circuit, digital received channel time delay control circuit, the time frequency marking combiner circuit, data processing time delay control circuit, wherein, simulation receive path time delay control circuit is input to digital received channel time delay control circuit, frequency marking combiner circuit and data processing time delay control circuit when digital received channel time delay control circuit is connected respectively to, the time frequency marking combiner circuit also be connected with data processing time delay control circuit; Simulation receive path time delay control circuit wherein is to be made of the rf inputs that is serially connected successively, one-level low noise amplifier, one-level dielectric filter, secondary low noise amplifier, frequency mixer, local oscillator, one-level operational amplifier, one-level LC filter, two-level operating amplifier and secondary LC filter, medium frequency output end; Wherein, digital received channel time delay control section mainly comprises pseudo range measurement error robustness control method and digital synchronization control method, and pseudo range measurement error robustness control method adopts code tracking loop and carrier tracking loop simultaneously; Adopt the carrier wave householder method in the design of code tracking loop, carrier tracking loop adopts multistage phase-locked loop (PLL) steady track method.
2, method for controlling time-delay stability of time service type satellite receiver according to claim 1 is characterized in that: described carrier tracking loop adopts multistage phase-locked loop (PLL) and the auxiliary steady track method of multistage FLL (FLL).
3, method for controlling time-delay stability of time service type satellite receiver according to claim 1 and 2 is characterized in that: described carrier tracking loop adopts 2 rank FLL to assist 3 rank phase-locked loop (PLL) steady track methods.
4, method for controlling time-delay stability of time service type satellite receiver according to claim 1 and 2 is characterized in that: described carrier tracking loop adopts 3 rank FLL to assist 5 rank PLL steady track methods.
5, method for controlling time-delay stability of time service type satellite receiver according to claim 1 and 2 is characterized in that: described code tracking loop adopts the relevant and wide district correlation technique in narrow district.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA200610018025XA CN101098181A (en) | 2006-06-27 | 2006-06-27 | Method for controlling time-delay stability of time service type satellite receiver |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA200610018025XA CN101098181A (en) | 2006-06-27 | 2006-06-27 | Method for controlling time-delay stability of time service type satellite receiver |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN101098181A true CN101098181A (en) | 2008-01-02 |
Family
ID=39011740
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNA200610018025XA Pending CN101098181A (en) | 2006-06-27 | 2006-06-27 | Method for controlling time-delay stability of time service type satellite receiver |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN101098181A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102291231A (en) * | 2010-06-16 | 2011-12-21 | 株式会社东芝 | Synchronous signal generating device and synchronous signal generating method |
| CN111431557A (en) * | 2020-06-12 | 2020-07-17 | 长沙北斗产业安全技术研究院有限公司 | Signal tracking method and signal tracking system suitable for multi-mode modulation system |
| CN111464397A (en) * | 2020-04-08 | 2020-07-28 | 清华大学 | Method and system for measuring bidirectional distance and clock error |
| CN116633327A (en) * | 2023-07-20 | 2023-08-22 | 泉州艾奇科技有限公司 | Clock circuit, electronic equipment and chip based on time service pulse timing |
-
2006
- 2006-06-27 CN CNA200610018025XA patent/CN101098181A/en active Pending
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102291231A (en) * | 2010-06-16 | 2011-12-21 | 株式会社东芝 | Synchronous signal generating device and synchronous signal generating method |
| CN102291231B (en) * | 2010-06-16 | 2014-05-07 | 株式会社东芝 | Synchronous signal generating device and synchronous signal generating method |
| CN111464397A (en) * | 2020-04-08 | 2020-07-28 | 清华大学 | Method and system for measuring bidirectional distance and clock error |
| CN111464397B (en) * | 2020-04-08 | 2021-04-30 | 清华大学 | Method and system for measuring bidirectional distance and clock error |
| CN111431557A (en) * | 2020-06-12 | 2020-07-17 | 长沙北斗产业安全技术研究院有限公司 | Signal tracking method and signal tracking system suitable for multi-mode modulation system |
| CN116633327A (en) * | 2023-07-20 | 2023-08-22 | 泉州艾奇科技有限公司 | Clock circuit, electronic equipment and chip based on time service pulse timing |
| CN116633327B (en) * | 2023-07-20 | 2023-10-10 | 泉州艾奇科技有限公司 | Clock circuit, electronic equipment and chip based on time service pulse timing |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN107643674B (en) | Vernier type TDC circuit based on FPGA carry chain | |
| CN102621563B (en) | GPS (global positioning system) software receiver signal tracking method based on FPGA (field programmable gate array) and system of GPS software receiver signal tracking method | |
| CN103675780B (en) | A kind of radar simulator for the full coherent of Ku wave band | |
| CN101509968B (en) | High dynamic high precision intermediate frequency simulation satellite signal generating method | |
| TW200709587A (en) | Circuit for measuring an eye size of data, and method of measuring the eye size of data | |
| CN101098181A (en) | Method for controlling time-delay stability of time service type satellite receiver | |
| CN102694760A (en) | Method for tuning digital compensation filter, and digital compensation filter | |
| CN110907962A (en) | Beidou double-frequency satellite signal radio frequency receiver | |
| CN104569961A (en) | Radar ranging method based on spectrum zooming | |
| CN104917556A (en) | Synchronous multi-beam signal generation method based on ultrahigh-speed DAC | |
| CN112838862B (en) | Broadband radio frequency signal frequency detection and tracking device based on all-digital phase-locked loop | |
| CN108918965A (en) | Multi channel signals phase, amplitude high-precision measuring method | |
| CN201499145U (en) | Millimeter wave frequency source | |
| CN202583467U (en) | FPGA-based GPS software receiver signal tracking system | |
| CN204515123U (en) | A kind of echo wave signal acquisition device of millimetre-wave radar | |
| CN103439690B (en) | A kind of ultra wide band radar frequency synthesizer device | |
| CN102546040A (en) | Method and system for testing channel delay difference | |
| CN102944885B (en) | Method and device for simulating multi-channel consistency by satellite navigation signal | |
| CN104460313A (en) | GPS time service device for providing high-precision large-step time synchronizing signals | |
| CN105577177B (en) | A kind of controllable frequency source of part frequency deviation phase noise | |
| US8179949B2 (en) | Correlation method and signal processing method of CDMA receiver using mapping | |
| CN102937714B (en) | Integrated precise time delay and rapid frequency spectrum shaping method of satellite navigation signal simulator | |
| CN104467825A (en) | Self-adaptive rapid crystal locking method based on Clean-up digital phase-locked loop | |
| CN115882896B (en) | DDS spread spectrum circuit, device and method for obtaining optimal scheme of spread spectrum circuit | |
| CN103984809A (en) | Method and device for compensating inter-satellite time difference |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C12 | Rejection of a patent application after its publication | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20080102 |