CN101086974A - Built-in testing device and method and testing device built in wafer cutting line section - Google Patents
Built-in testing device and method and testing device built in wafer cutting line section Download PDFInfo
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- CN101086974A CN101086974A CN 200610083137 CN200610083137A CN101086974A CN 101086974 A CN101086974 A CN 101086974A CN 200610083137 CN200610083137 CN 200610083137 CN 200610083137 A CN200610083137 A CN 200610083137A CN 101086974 A CN101086974 A CN 101086974A
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Abstract
A kind of embedded testing device and method and testing device which is built between wafer cutting lines is used to test at least one integrated circuit and output of several integrated circuits are digital code. Embedded testing device includes digitalizer and test platform, the testing device which is built between wafer cutting lines includes digitalizer. The digitalizer is set on wafer, and electric connected with the output of the integrated circuit, it is used to transform output of the integrated circuit to digital code. The test platform is electric connected with the output of the digitalizer to provide at least one test pattern for the integrated circuits, and receives and checks digital codes output by the digitalizer.
Description
Technical field
The present invention relates to a kind of wafer test apparatus, and be particularly related to a kind of embedded testing device that digitizer is embedded in wafer.
Background technology
Integrated circuit (integrated circuit) is through in design and the process of making, must be through a series of verification and testing, guaranteeing its function and quality, even can revise the manufacturing process of integrated circuit according to the result of these tests.The test of integrated circuit all is necessary in the different phase of semiconductor fabrication process, and each integrated circuit all must be accepted test to guarantee its electrical functionality at wafer stage and encapsulated phase.Along with the reinforcement of integrate circuit function and complicated, also just more important with accurate testing requirement at a high speed.But each integrated circuit in wafer kenel use test board testing wafer, its step is as follows.At first, each crystalline substance side (die) (referring to each integrated circuit on wafer), provide a plurality of weld pads (pad) on every side, in order to output or the input as electric signal.Then, the weld pad of the test probe contact input of tester table is in order to import outer electric signal in addition.At last, tester table contacts the weld pad of output to measure the electric signal of output by test probe.Above-mentioned electric signal for example is critical voltage (threshold voltage) or saturation current (saturate current) etc.
Yet the accuracy of wafer sort is different with test platform detection electric signal ability.For example, at present the chip for driving of display floater need record output voltage values more accurately in the wafer sort stage, so test platform need have the high-resolution ability and just can test.Generally speaking, if desire driver IC at wafer stage test display floater, then test platform need have the resolution of 16 analog digital conversions (its accuracy is about 0.01% ± 2mV) or high-resolution more.And the test platform of high-resolution need possess the signal that digitizer that high-resolution is arranged records in order to analysis.Usually these digitizers are the test circuit module of customized design, and its test specification is according to the customer demand manufacturing but not therefore a large amount of production relatively need pay higher manufacturing cost.Adopt the high-order test platform of above-mentioned customized test circuit module that the cost of wafer sort will be improved.In addition, when carrying out wafer sort, test platform needs the use test probe to contact the weld pad of each integrated circuit one by one to record electric signal.Yet test probe can be along with the loss with the increase of weld pad frequency of exposure, to such an extent as to influence test accuracy.
Summary of the invention
In view of this, purpose of the present invention just provides a kind of embedded testing device, and it tests at least one integrated circuit with the digitizer that is arranged at wafer.
Another object of the present invention provides a kind of embedded testing device, it chooses the output of a plurality of test targets on the wafer to be arranged on selector on the wafer, and, reduce the wastage with the frequency of exposure that reduces test probe and weld pad with the test target that the digitizer test is chosen.
Another purpose of the present invention provides a kind of embedded testing device, to electrically input to a plurality of test targets with the switch that is arranged on the wafer, and choose a plurality of test targets with selector and export, and the output of testing at least one test target of choosing with digitizer.
A further object of the present invention provides a kind of embedded method of testing, in order to test at least one integrated circuit on wafer.
A further object of the present invention provides the testing apparatus that is built in the wafer cutting line interval in a kind of, in order to the digital code that is output as of a plurality of integrated circuits in the conversion wafer.
Based on above-mentioned and other purpose, the present invention proposes a kind of embedded testing device, in order to test at least one integrated circuit on wafer.This embedded testing device comprises digitizer and test platform.Digitizer is arranged on the wafer, and is electrically connected to the output of integrated circuit, is converted to digital code in order to the output with this integrated circuit.Test platform is electrically connected to the output of digitizer, gives this integrated circuit in order at least one test sample book (test pattern) to be provided, and receives and verify the digital code that this digitizer is exported.
According to the described embedded testing device of preferred embodiment of the present invention, above-mentioned test platform comprises a plurality of test probes, and this test platform is electrically connected to the input of integrated circuit and the output of digitizer by these test probes.
From another viewpoint, the present invention proposes a kind of embedded testing device, in order to test a plurality of test targets on wafer.This embedded testing device comprises selector, digitizer and test platform.Selector is arranged on the wafer, comprises a plurality of input groups and an output group.Each input group of this selector is electrically connected to the output group of the test target of correspondence separately, is used to select one in the input group of this selector, and selected input group is electrically connected the output group of selector so far.Digitizer is arranged on this wafer.The input group of this digitizer is electrically connected the output group of selector so far, and wherein this digitizer is converted to digital code with its input.Test platform is electrically connected the output group of digitizer so far, gives the test target in order at least one test sample book (test pattern) to be provided, and receives and verify the digital code that this digitizer is exported.
According to the described embedded testing device of preferred embodiment of the present invention, above-mentioned test platform comprises a plurality of test probes, and this test platform is electrically connected to the input group of test target and the output group of digitizer by these test probes.
According to the described embedded testing device of preferred embodiment of the present invention, also comprise: input buffer, be arranged on the wafer, and the input group of this input buffer is electrically connected to test platform, and the output group of this input buffer is electrically connected to the input group of test target, sends these test targets in order to the test sample book that test platform is exported.
The present invention proposes a kind of embedded testing device, in order to test a plurality of test targets on wafer.This embedded testing device comprises selector, digitizer, switch and test platform.Selector, digitizer, switch all are arranged on the wafer.Selector comprises a plurality of input groups and an output group, wherein each input group of selector is electrically connected to the output group of the test target of correspondence separately, be used to select one in the input group of selector, and selected input group is electrically connected the output group of selector so far.The input group of digitizer is electrically connected to the output group of selector, and wherein digitizer is converted to digital code with its input.Switch comprises an input group and a plurality of output group, wherein each output group of switch is electrically connected to the input group of the test target of correspondence separately, in order to one of in the output group that optionally the input group of switch is electrically connected to switch.Test platform is electrically connected to the input group of switch and the output group of digitizer, gives switch in order at least one test sample book (test pattern) to be provided, and receives and verify the digital code that digitizer is exported.
According to the described embedded testing device of preferred embodiment of the present invention, above-mentioned test platform comprises a plurality of test probes, and this test platform is electrically connected to the input group of switch and the output group of digitizer by these test probes.
According to the described embedded testing device of preferred embodiment of the present invention, wherein selector comprises multiplexer (multiplexer).
According to the described embedded testing device of preferred embodiment of the present invention, wherein switch comprises demultiplexer (demultiplexer).
According to the described embedded testing device of preferred embodiment of the present invention, wherein selector, digitizer and switch are to be arranged in the line of cut interval of wafer.
According to the described embedded testing device of preferred embodiment of the present invention, wherein each tests the circuit of an illumination range in the manufacturing process that target is a wafer.
According to the described embedded testing device of preferred embodiment of the present invention, wherein each test target is an integrated circuit to be measured.
The present invention proposes a kind of embedded method of testing, and in order to test at least one integrated circuit on wafer, this method of testing comprises that step is as follows.At first, digitizer is set on wafer, then, makes the input group of this digitizer be electrically connected to the output group of integrated circuit.Afterwards, by this digitizer the output of this integrated circuit is converted to digital code.Then, import the input of at least one test sample book (testpattern) to integrated circuit.At last, and verify the digital code that this digitizer is exported.
According to the described embedded method of testing of preferred embodiment of the present invention, also comprise: in a plurality of integrated circuits to be measured on wafer, select one of them integrated circuit.
According to the described embedded method of testing of preferred embodiment of the present invention, wherein digitizer comprises analog-digital converter.
According to the described embedded method of testing of preferred embodiment of the present invention, wherein digitizer is to be arranged in the line of cut interval of wafer.
According to the described embedded method of testing of preferred embodiment of the present invention, wherein integrated circuit comprises the driver of display floater.
The present invention proposes to be built in a kind of the testing apparatus in wafer cutting line interval, the digital code that is output as in order to a plurality of integrated circuits in the conversion wafer, this testing apparatus is arranged at the line of cut interval of wafer, it is characterized in that this device comprises a digitizer, be arranged at the line of cut interval of wafer, and be electrically connected to the output of integrated circuit, be converted to digital code for detection in order to output with integrated circuit.
The present invention proposes to be built in a kind of the testing apparatus in wafer cutting line interval, the digital code that is output as in order to a plurality of integrated circuits in the conversion wafer, this testing apparatus is arranged at the line of cut interval of wafer, this device comprises a selector, be arranged at the line of cut interval of wafer, comprise a plurality of input groups and an output group, wherein each input group of selector is electrically connected to the output group of the integrated circuit of correspondence separately, be used to select one in a plurality of input groups of selector, and selected input group be electrically connected to the output group of selector.And a digitizer, being arranged at the line of cut interval of wafer, the input group of this digitizer is electrically connected to the output group of selector, and wherein this digitizer is converted to digital code for detection with its input.
The present invention's digitizer that wafer sort is required is embedded in the line of cut interval of wafer, and will be electrically connected to the output of integrated circuit, in order to transfer output signal to digital code, with the correctness of proof scheme.Therefore can utilize the tester of lower-order to obtain the testing precision that is equivalent to the high-order tester, and reach the purpose of saving the test funds.The present invention controls input with selector and switch in addition, each integrated circuit can shared same input group input test sample (test pattern), to reduce the chance and the number of times of test probe contact integrated circuit weld pad, and reduce the quantity of use test probe and the wearing and tearing that slow down test probe, and then save testing cost.
State with other purpose, feature and advantage and can become apparent on the present invention for allowing, preferred embodiment cited below particularly, and conjunction with figs. are described in detail below.
Description of drawings
Fig. 1 is provided with the block diagram of an integrated circuit for one of first embodiment of the invention digitizer.
Fig. 2 is the block diagram of the shared digitizer of a plurality of integrated circuits on the wafer of second embodiment of the invention.
Fig. 3 A is the block diagram of the shared digitizer of a plurality of test targets on the wafer of third embodiment of the invention.
Fig. 3 B is the circuit block diagram with the block 340 amplification backs of Fig. 3 A.
Fig. 4 is the shared digitizer of a plurality of integrated circuits and with the block diagram of buffer control input on the wafer of fourth embodiment of the invention.
Fig. 5 A is the shared digitizer of a plurality of test targets and with the block diagram of buffer control input on the wafer of fourth embodiment of the invention.
Fig. 5 B is the circuit block diagram with the block 540 amplification backs of Fig. 5 A.
Fig. 6 is the shared digitizer of a plurality of integrated circuits and with the block diagram of switch control input on the wafer of fifth embodiment of the invention.
Fig. 7 is the shared digitizer of a plurality of test targets and with the block diagram of switch control input on the wafer of fifth embodiment of the invention.
The main element description of symbols
100: wafer
110,220,410,610: integrated circuit
111,121,231,331,431,561,631,731: the output weld pad
112,212,312,412,512,612,712: power lead
120,230,360,430,560,630,730: digitizer
130,250,320,520,450,520,650,750: the line of cut interval
190: test platform
191: test probe
210,310,510,710: the test target
330,530: the digitizer module
340,540: block
240,350,420,550,620,720: selector
440,570: input buffer
441,571: the input group of input buffer
442,572: the output group of input buffer
640,740: switch
641,741: the input group of switch
Embodiment
For make within the present invention hold more clear, below the example that can implement according to this really as the present invention especially exemplified by the driver IC of display panels.The person of ordinary skill in the field can be according to the present invention's spirit and the teaching of following all embodiment, and applies the present invention to the wafer stage test job of various integrated circuits.
First embodiment
Fig. 1 is provided with the block diagram of an integrated circuit for one of first embodiment of the invention digitizer.Please refer to Fig. 1, wafer 100 comprises a plurality of integrated circuits 110 and a plurality of digitizer 120.Zone between each integrated circuit 110 is line of cut interval 130, and digitizer 120 is arranged on the line of cut interval 130.Digitizer 120 is electrically connected to the output of integrated circuit 110.In present embodiment, integrated circuit 110 is the driver of display panels for example, so the output signal of integrated circuit 110 may be analog signal.So digitizer 120 can be implemented it with analog-digital converter, so that the simulation output of integrated circuit 110 is converted to digital code.This integrated circuit 110 is provided with a plurality of output weld pads (output pad).The a plurality of output weld pads of hatched example areas 111 expressions among Fig. 1 around each integrated circuit 110, and a plurality of output weld pads of hatched example areas 121 expressions of each digitizer 120.Each output weld pad of integrated circuit 110 is connected to the input of digitizer 120 respectively accordingly.Test platform 190 comprises a plurality of test probes 191.In present embodiment, test platform 190 is with the output weld pad 121 of test probe 191 contact digitizers and the input of integrated circuit 110, and provide at least one test sample book (test pattern) to give integrated circuit 110, and receive the digital code of being exported with checking from the output weld pad 121 of digitizer.In present embodiment, each integrated circuit 110 of wafer 100 all is assigned with the digitizer 120 of a correspondence, so the output of integrated circuit 110 produces digital code via the conversion of corresponding digitizer 120.In addition, the digitizer 120 required electric power that provide are to be electrically connected digitizers 120 with power lead 112 and to be provided by integrated circuit 110.
Then narrate the operating procedure of present embodiment.Wafer 100 to be measured at first is provided.On wafer 100, the input group of digitizer 120 is electrically connected to the output group of integrated circuit 110.Next, 190 more than test probes 191 of test platform are connected on the wafer input group of at least one selected integrated circuit in a plurality of integrated circuits 110 to be measured, and the output that is connected to the digitizer 120 in the line of cut interval that is embedded in wafer.Test platform 190 is via the input group of test probe 191 at least one test sample book of input (test pattern) to integrated circuit 110.Integrated circuit 110 reaches digitizer 120 with test result, and digitizer 120 is converted to digital code with the output of integrated circuit 110.At last, test platform 190 contacts the output group of digitizers 120 to obtain and the validation test result by test probe 191.
The accuracy of wafer sort is different with test platform detection electric signal ability.The test platform of higher accuracy need possess the electric signal that digitizer that high-resolution is arranged records in order to analysis.And these digitizers are the test circuit module according to the customized design of customer demand manufacturing, and its cost is expensive.Therefore, among the present invention this digitizer is embedded on the wafer, then can reduces the cost of extra manufacturing digitizer.When integrated circuit testing, just can use the test platform (for example personal computer) of lower-order to come testing integrated circuits, and not be subject to the test platform that needs to use higher-order.The digitizer that is embedded in the line of cut interval of wafer will be cut destruction after wafer sort is finished, so the circuit of test such as digitizer does not influence the work of integrated circuit after finishing the cutting of crystalline substance side.In addition, digitizer is embedded in the line of cut interval, and it does not take the area of making integrated circuit, so do not influence the integrated circuit production capacity.
Each integrated circuit need be provided with a digitizer in first embodiment, but but also the design alternative device allow the shared digitizer of a plurality of integrated circuits.Embodiment below in conjunction with the shared digitizer of a plurality of integrated circuits of description of drawings please refer to following explanation.
Second embodiment
Fig. 2 is the block diagram of the shared digitizer of a plurality of integrated circuits on the wafer of second embodiment of the invention.Please refer to Fig. 2, the circuit in the wafer fabrication process in the illumination range (photo shut) is a test target 210 (as shown in Figure 2), comprises a plurality of integrated circuit 220, a digitizer 230 and a selector 240 at present embodiment.Zone between each integrated circuit is line of cut interval 250, and digitizer 230 and selector 240 are arranged on the line of cut interval 250.Selector 240 can be multiplexer (multiplexer), and digitizer 230 can be implemented it with analog-digital converter.Each integrated circuit 220 is provided with a plurality of output weld pads 211 (shown in figure bend zone).The device of present embodiment is similar to the embodiment of above-mentioned Fig. 1, below only narrates difference.
A plurality of integrated circuits 220 shared digitizers 230 in the test target 210 of Fig. 2 (in the present embodiment, illumination range of test target 210 expressions).This digitizer 230 has a plurality of output weld pads 231 (shown in figure bend zone).The output group of each integrated circuit 220 is connected to the input group of selector 240 respectively accordingly.When testing, test platform can be controlled selector 240, makes this selector 240 select one of them input group, and selected input group is electrically connected to the output group of selector 240.The output group of this selector 240 is electrically connected to the input group of digitizer 230.Digitizer 230 is converted to digital code with the output of integrated circuit 220.Test platform contacts the input group of each integrated circuit 220 with test probe, and transmits at least one test sample book via test probe and give integrated circuit 220.Test platform contacts the output weld pad 231 of digitizer 230 in addition with test probe, so that receive and verify the digital code that digitizer 230 is exported.In addition, digitizer 230 and the selector 240 required electric power that provide in the present embodiment can be electrically connected with power lead 212 and it is provided by arbitrary integrated circuit 220 in the test target 210.
The present embodiment digitizer that wafer sort is required is embedded in the line of cut interval of wafer, in order to transfer output signal to digital code, with the correctness of proof scheme.Therefore can utilize the tester of lower-order to obtain the testing precision that is equivalent to the high-order tester, and reach the purpose of saving testing cost.In addition, compare with last embodiment, present embodiment is also selected the integrated circuit of desire checking with selector, so each integrated circuit can shared same digitizer, and can reduce the number of times of test probe contact integrated circuit weld pad.So present embodiment can slow down the wearing and tearing of test probe, and then save testing cost.
The 3rd embodiment
By another angle, a plurality of test targets also can a shared digitizer, utilizes selector to come the switch test target.Fig. 3 A is the block diagram of the shared digitizer of a plurality of test targets on the wafer of third embodiment of the invention.Please refer to Fig. 3 A, wafer region is divided into a plurality of illumination ranges (photo shut) 310 among the figure, and is being between cutting area 320 between each illumination range.Digitizer module 330 is arranged on the line of cut interval 320 of wafer.
Fig. 3 B is the circuit block diagram with the block 340 amplification backs of Fig. 3 A.Please refer to Fig. 3 B, include a plurality of test targets 3 10 and a digitizer module 330 among the figure.Comprise a selector 350 and a digitizer 360 in this digitizer module 330.Wherein the output group of each test target 310 is electrically connected to each input group of selector 350, and the output group of this selector 350 then is electrically connected to the input group of digitizer 360.Comprise many group test probes in the test platform, and be electrically connected to the input group of each test target 310, and a plurality of output weld pads 331 (shown in figure bend zone) that are electrically connected to digitizer 360.Test platform can provide at least one group test sample book, imports each test target 310 via test probe.Selector 350 is tested target in order to selection, and test result is reached digitizer 360.The output signal of each test target 310 may be analog signal.So digitizer 360 can be implemented it with analog-digital converter, be converted to digital code so that will simulate output, and pass the test platform checking back via test probe.In addition, selector 350 and the digitizer 360 required electric power that provide can be electrically connected with power lead 312 and it is provided by the arbitrary test target 310 in the block 340.
Among above-mentioned three embodiment, the test probe of test platform must be electrically connected to the input group of each integrated circuit or test target.Can loss in order to the test probe that transmits test sample book along with the increase of frequency of exposure, to such an extent as to influence test accuracy.Perhaps, test platform must have many groups in order to transmit the test probe of test sample book, so that can contact the integrated circuit of all desire tests or the input group of test target simultaneously, and reduce the number of times of test probe contact wafer, yet but need increase the quantity of test probe.In following examples, another kind of framework is proposed, can lower the number of times of test probe contact wafer of test platform and the loss that slows down test probe, and reduce the quantity of test probe.
The 4th embodiment
Fig. 4 is the shared digitizer of a plurality of integrated circuits and with the block diagram of buffer gain input signal on the wafer of fourth embodiment of the invention.The device of present embodiment is similar to the device of Fig. 2, so same section will repeat no more between the two.Please refer to Fig. 4, comprise a plurality of integrated circuit to be measured 410, selector 420, a digitizer 430 and an input buffer 440 in this wafer.Zone between each integrated circuit is line of cut interval 450.Selector 420, digitizer 430 all are arranged in the line of cut interval 450 of wafer with input buffer 440.The device difference of Fig. 4 and Fig. 2 is that Fig. 4 is provided with an input buffer 440.
Please refer to Fig. 4, the input group 441 of test platform use test probe contact input buffer 440, and the output group 442 of input buffer 440 is electrically connected to the input group of each integrated circuit 410.Test platform is input to input buffer 440 with test sample book.This test sample book can be sent to the input of each integrated circuit 410 through input buffer 440 thus.The test probe of test platform need not contact each integrated circuit 410 respectively, only need the input of contact buffer 440 then test sample book can be sent to each integrated circuit 410, therefore can reduce the loss (or quantity of minimizing test probe) of test probe, and then save testing cost.
Test platform can be controlled selector 420, makes this selector 420 select one of them input group, and selected input group is electrically connected to the output group of selector 420.Digitizer 430 is converted to digital code with the output of integrated circuit 410.Therefore, test platform can contact the digital code that digitizer 430 more than output weld pad 431 (the oblique line portion with digitizer in scheming 430 represents it) is obtained conversion by test probe, and the correctness of checking digital code.In addition, selector 420 and the digitizer 430 required electric power that provide can be electrically connected with power lead 412 and it is provided by arbitrary integrated circuit 410 among the figure.
In like manner, the device of the shared digitizer of a plurality of test targets also can be protected test probe with an input buffer, and Fig. 5 a is the shared digitizer of a plurality of test targets and with the block diagram of buffer control input on the wafer of fourth embodiment of the invention.Please refer to Fig. 5 A, be divided into a plurality of illumination ranges (photo shut) 510 in the wafer, and be between cutting area 520 between each illumination range.Digitizer module 530 is arranged on the line of cut interval of wafer.
Fig. 5 B is the circuit block diagram with the block 540 amplification backs of Fig. 5 A.Please refer to Fig. 5 B, include a plurality of test target 510, a digitizer module 530 and an input buffer 570 among the figure.Comprise a selector 550 and a digitizer 560 in the digitizer module 530.Wherein, the input group 571 of input buffer 570 is electrically connected to test platform, and in order to the acceptance test sample, output group 572 then is connected to the input group of each test target 510, is sent to each test target 510 in order to the test sample book that will receive.Because the output signal of each test target 510 may be analog signal.So digitizer 560 can be implemented it with analog-digital converter, be converted to digital code so that will simulate output, and pass the test platform checking back.In addition, selector 550, digitizer 560 and the input buffer 570 required electric power that provide can be electrically connected with power lead 512 and it is provided by the test target 510 in the wafer.
Function at the input buffer of the 4th embodiment is sent to each integrated circuit or test target for the test sample book that will import, and to integrated circuit or test target transmission test sample book, its framework is described below following examples for distinctly.
The 5th embodiment
Fig. 6 is the shared digitizer of a plurality of integrated circuits and with the block diagram of switch control input on the wafer of fifth embodiment of the invention.The device of present embodiment is similar to the device of Fig. 2, please be simultaneously with reference to Fig. 2 and Fig. 6, and the device of Fig. 6 comprises a plurality of integrated circuit to be measured 610, selector 620, a digitizer 630 and a switch 640.Zone between each integrated circuit is line of cut interval 650, wherein selector 620, digitizer 630 and switch 640 are the line of cut intervals 650 that are arranged on the wafer, its required electric power that provides can be electrically connected with power lead 612 and it is provided by integrated circuit 610.This device is that with the device difference of Fig. 2 this device comprises a switch 640, and this switch possesses an input group and a plurality of output group.Each output group is electrically connected to the input group of corresponding integrated circuit 610 separately.Switch 640 optionally is sent to the input group of one of them integrated circuit in order to the test sample book with the test platform input.
Present embodiment to carry out step as described below.At first, test platform use test probe is sent to test sample book the input group 641 (shown in the figure bend) of switch 640.Afterwards, switch 640 one of optionally reaches test sample book in the integrated circuit 610.The input group of selector 620 is electrically connected to the output group of integrated circuit.The input group of digitizer 630 is electrically connected to the output group of selector 620, and input signal is converted to digital code.At last, test platform use test probe contact digitizer 630 respectively exports weld pad 631 (partly representing it with oblique line among the figure) to receive and to verify the digital code of output.
In like manner, a plurality of test targets also can be controlled the input of test sample book with switch on the wafer, and Fig. 7 is the shared digitizer of a plurality of test targets on the wafer of fifth embodiment of the invention, and with the block diagram of switch control input.Please refer to Fig. 7, device for example is the enlarged drawing of block 540 of Fig. 5 A among the figure, comprising a plurality of test target 710, selector 720, a digitizer 730 and a switch 740.Selector 720 for example is a multiplexer (multiplexer), and switch 740 for example is a demultiplexer (demultiplexer), and digitizer 730 for example is an analog-digital converter.Zone in the wafer between each test target is line of cut interval 750, and selector 720, digitizer 730 and switch 740 all are installed on the line of cut interval 750 of wafer.
Described with present embodiment Fig. 6 device, after the test sample book of switch 740 acceptance test platform inputs, optionally test sample book is exported to each test one of in target 710.Its step and device couple the seemingly device of Fig. 6 of present embodiment of relation object, below in detail device and the operating procedure of Fig. 7 are described in detail no longer.
In sum, comprise following advantage at least in embedded testing device of the present invention:
Therefore 1. the present invention is embedded in the wafer to be measured because of testing required digitizer, can utilize the test platform of more cheap low order to finish the test of integrated circuit.That is the present invention need not use expensive high-order test platform, can reach and the identical test function of high-order test platform that possesses the high-resolution digitizer.Therefore, the present invention can reduce testing cost.
2. therefore the present invention can additionally not take under the condition of chip area because of in the line of cut interval that will test required digitizer and be embedded in wafer to be measured, uses more cheap low order test platform to carry out the test function of high-resolution.
3. be embedded in the switch and the selector of wafer by use, making only needs when testing integrated circuits the test probe contact on the circuit in line of cut interval, and do not need to contact one by one each integrated circuit, therefore the contact loss that can reduce test probe quantity and lower test probe, and then reduction testing cost.
Though the present invention discloses as above with preferred embodiment; right its is not in order to limit the present invention; any person of ordinary skill in the field; without departing from the spirit and scope of the invention; when can doing a little change and improvement, so the present invention's protection range is as the criterion when looking the claim person of defining.
Claims (39)
1. embedded testing device in order to test at least one integrated circuit on wafer, is characterized in that comprising:
Digitizer is arranged on this wafer, and is electrically connected to the output of this integrated circuit, is converted to digital code in order to the output with this integrated circuit; And
Test platform is electrically connected to the output of this digitizer, in order to providing at least one test sample book to this integrated circuit, and receives and the digital code of verifying that this digitizer is exported.
2. the embedded testing device according to claim 1 is characterized in that this test platform comprises a plurality of test probes, and this test platform is electrically connected to the input of this integrated circuit and the output of this digitizer by above-mentioned these test probes.
3. the embedded testing device according to claim 1 is characterized in that this digitizer comprises analog-digital converter.
4. the embedded testing device according to claim 1 is characterized in that this digitizer is to be arranged in the line of cut interval of this wafer.
5. the embedded testing device according to claim 1 is characterized in that this integrated circuit comprises the driver of display floater.
6. embedded testing device in order to test a plurality of test targets on wafer, is characterized in that comprising:
Selector, be arranged on this wafer, comprise a plurality of input groups and output group, wherein each input group of this selector is electrically connected to the output group of the test target of correspondence separately, be used to state on this selector in these input groups and select one, and selected input group is electrically connected to the output group of this selector;
Digitizer is arranged on this wafer, and the input group of this digitizer is electrically connected to the output group of this selector, and wherein this digitizer is converted to digital code with its input; And
Test platform is electrically connected to the output group of this digitizer, in order to providing at least one test sample book to above-mentioned these test targets, and receives and the digital code of verifying that this digitizer is exported.
7. the embedded testing device according to claim 6, it is characterized in that this test platform comprises a plurality of test probes, and this test platform is electrically connected to the input group of above-mentioned these test targets and the output group of this digitizer by above-mentioned these test probes.
8. the embedded testing device according to claim 6 is characterized in that this selector comprises multiplexer.
9. the embedded testing device according to claim 6 is characterized in that this digitizer comprises analog-digital converter.
10. the embedded testing device according to claim 6 is characterized in that this digitizer and this selector are to be arranged in the line of cut interval of this wafer.
11. the embedded testing device according to claim 6 is characterized in that the circuit of each above-mentioned these test target for an illumination range in the manufacturing process of this wafer.
12. the embedded testing device according to claim 6 is characterized in that each above-mentioned these test target is an integrated circuit to be measured.
13. the embedded testing device according to claim 12 is characterized in that this integrated circuit comprises the driver of display floater.
14. the embedded testing device according to claim 6 is characterized in that also comprising:
Input buffer, be arranged on this wafer, and the input group of this input buffer is electrically connected to this test platform, and the output group of this input buffer is electrically connected to the input group of above-mentioned these test targets, sends above-mentioned these test targets in order to this test sample book that this test platform is exported.
15. the embedded testing device according to claim 14 is characterized in that this input buffer is to be arranged in the line of cut interval of this wafer.
16. an embedded testing device in order to test a plurality of test targets on wafer, is characterized in that comprising:
Selector, be arranged on this wafer, comprise a plurality of input groups and output group, wherein each input group of this selector is electrically connected to the output group of the test target of correspondence separately, be used to state on this selector in these input groups and select one, and selected input group is electrically connected to the output group of this selector;
Digitizer is arranged on this wafer, and the input group of this digitizer is electrically connected to the output group of this selector, and wherein this digitizer is converted to digital code with its input;
Switch, be arranged on this wafer, comprise input group and a plurality of output group, wherein each output group of this switch is electrically connected to the input group of the test target of correspondence separately, one of states on this switch in these output groups in order to optionally the input group of this switch is electrically connected to; And
Test platform is electrically connected to the input group of this switch and the output group of this digitizer, in order to providing at least one test sample book to this switch, and receives and the digital code of verifying that this digitizer is exported.
17. the embedded testing device according to claim 16 is characterized in that this test platform comprises a plurality of test probes, and this test platform is electrically connected to the input group of this switch and the output group of this digitizer by above-mentioned these test probes.
18. the embedded testing device according to claim 16 is characterized in that this selector comprises multiplexer.
19. the embedded testing device according to claim 16 is characterized in that this digitizer comprises analog-digital converter.
20. the embedded testing device according to claim 16 is characterized in that this switch comprises demodulation multiplexer.
21. the embedded testing device according to claim 16 is characterized in that this selector, this digitizer and this switch are to be arranged in the line of cut interval of this wafer.
22. the embedded testing device according to claim 16 is characterized in that the circuit of each above-mentioned these test target for an illumination range in the manufacturing process of this wafer.
23. the embedded testing device according to claim 16 is characterized in that each above-mentioned these test target is an integrated circuit to be measured.
24. the embedded testing device according to claim 23 is characterized in that this integrated circuit comprises the driver of display floater.
25. an embedded method of testing in order to test at least one integrated circuit on wafer, is characterized in that comprising:
Digitizer is set on this wafer;
Make the input group of this digitizer be electrically connected to the output group of this integrated circuit;
By this digitizer the output of this integrated circuit is converted to digital code;
Import of the input of at least one test sample book to this integrated circuit; And
Verify the digital code that this digitizer is exported.
26. the embedded method of testing according to claim 25 is characterized in that also comprising:
In a plurality of integrated circuits to be measured on wafer, select one of them integrated circuit.
27. the embedded method of testing according to claim 25 is characterized in that this digitizer comprises analog-digital converter.
28. the embedded method of testing according to claim 25 is characterized in that this digitizer is to be arranged in the line of cut interval of this wafer.
29. the embedded method of testing according to claim 25 is characterized in that this integrated circuit comprises the driver of display floater.
30. be built in the testing apparatus in wafer cutting line interval in one kind, in order to the digital code that is output as of a plurality of integrated circuits in the conversion wafer, this testing apparatus is arranged at the line of cut interval of this wafer, it is characterized in that this device comprises:
Digitizer is arranged at the line of cut interval of this wafer, and is electrically connected to the output of above-mentioned these integrated circuits, is converted to digital code for detection in order to the output with above-mentioned these integrated circuits.
31. the testing apparatus according to claim 30 is characterized in that this digitizer comprises analog-digital converter.
32. the testing apparatus according to claim 30 is characterized in that above-mentioned these integrated circuits comprise the driver of display floater.
33. the testing apparatus according to claim 30 is characterized in that also comprising:
Input buffer, the line of cut interval of this wafer is set, the input group of this input buffer is in order to receiving one group of test sample book signal, and the output group of this input buffer is electrically connected to above-mentioned these integrated circuits, sends above-mentioned these integrated circuits in order to should organize the test sample book signal.
34. the testing apparatus according to claim 30 is characterized in that also comprising:
Switch, be arranged at the line of cut interval of this wafer, comprise input group and a plurality of output group, wherein the input group of this switch is in order to receive one group of test sample book signal, each output group of this switch be electrically connected to separately state on the correspondence these integrated circuits the input group, one of state on this switch in these output groups in order to optionally the input group of this switch is electrically connected to.
35. be built in the testing apparatus in wafer cutting line interval in one kind, in order to the digital code that is output as of a plurality of integrated circuits in the conversion wafer, this testing apparatus is arranged at the line of cut interval of this wafer, it is characterized in that this device comprises:
Selector, be arranged at the line of cut interval of this wafer, comprise a plurality of input groups and output group, wherein each input group of this selector is electrically connected to the output group of stating these integrated circuits on the correspondence separately, be used to state on this selector in these input groups and select one, and selected input group is electrically connected to the output group of this selector; And
Digitizer is arranged at the line of cut interval of this wafer, and the input group of this digitizer is electrically connected to the output group of this selector, and wherein this digitizer is converted to digital code for detection with its input.
36. the testing apparatus according to claim 35 is characterized in that also comprising:
Input buffer, the line of cut interval of this wafer is set, the input group of this input buffer is in order to receiving one group of test sample book signal, and the output group of this input buffer is electrically connected to above-mentioned these integrated circuits, sends above-mentioned these integrated circuits in order to should organize the test sample book signal.
37. the testing apparatus according to claim 35 is characterized in that also comprising:
Switch, be arranged at the line of cut interval of this wafer, comprise input group and a plurality of output group, wherein the input group of this switch is in order to receive one group of test sample book signal, each output group of this switch be electrically connected to separately state on the correspondence these integrated circuits the input group, one of state on this switch in these output groups in order to optionally the input group of this switch is electrically connected to.
38. the testing apparatus according to claim 35 is characterized in that this digitizer comprises analog-digital converter.
39. the testing apparatus according to claim 35 is characterized in that above-mentioned these integrated circuits comprise the driver of display floater.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200610083137 CN101086974A (en) | 2006-06-05 | 2006-06-05 | Built-in testing device and method and testing device built in wafer cutting line section |
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| Application Number | Priority Date | Filing Date | Title |
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| CN 200610083137 CN101086974A (en) | 2006-06-05 | 2006-06-05 | Built-in testing device and method and testing device built in wafer cutting line section |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112752978A (en) * | 2018-10-12 | 2021-05-04 | 爱德万测试株式会社 | Analysis device, analysis method, and analysis program |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN112752978A (en) * | 2018-10-12 | 2021-05-04 | 爱德万测试株式会社 | Analysis device, analysis method, and analysis program |
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