CN101082895A - Complicated circuit system universal bus - Google Patents

Abstract

The invention discloses an all-purpose bus of complex circuit system, which comprises the following parts: system host, system bus, digital mode circuit interface, system digital mode circuit and system analog mode circuit, wherein the system bus contains digital paralleling system bus and analog paralleling system, which is separated into control bus, address bus and data bus; one end of the bus system connects a breaking switch; the host connects the other end of breaking switch; the digital end of the system host connects one end of digital mode circuit interface of the other end of the digital paralleling bus; the other end of the digital mode circuit connects the system digital analog circuit through digital paralleling bus; the analog end of the system host connects the system analog mode circuit of the other end of the analog paralleling bus through breaking switch. The invention reduces the design period of estimating system greatly to improve the estimating speed with simple technique, which can be applied in the estimating testing system of complex circuit widely.

Description

A kind of complicated circuit system universal bus

Technical field

The present invention relates to a kind of versabus, particularly about a kind of to complicated circuit system universal bus.

Background technology

At present, in various electronic apparatus systems, have various bus structure, but they design for dedicated system all.The electronic technology develop rapidly, various new products emerge in an endless stream, and popular at present system bus also has a variety of.For complicated circuit system, integrated circuit particularly, hope can be carried out actual hardware circuit design result's assessment and emulation testing before the mask manufacturing, to increase the credibility and the reliability of design result.Traditional method of testing all is to set up corresponding system earlier, then it is debugged and test analysis.The characteristics that this way has are with strong points, can directly assess at designed integrated circuit or system; Its shortcoming then is universal not strong, and particularly concerning medium and small integrated circuit (IC) design, there are the characteristics of long, technical sophistication of design cycle in this special-purpose evaluation system, therefore generally should not adopt.Up to the present, also do not see complicated circuit system is assessed relevant report with the versabus of emulation testing.

Summary of the invention

At the problems referred to above, the purpose of this invention is to provide a kind of versabus with bus general characteristic, can test most systems.

For achieving the above object, the present invention takes following technical scheme: a kind of complicated circuit system universal bus is characterized in that: it comprises system host, system bus, digital module circuit interface, system digits modular circuit and system simulation modular circuit five parts; Described system bus comprises digital parallel system bus and simulation parallel system bus, they are divided into control bus, address bus and data bus, one end of described bus system connects a cutting-off switch, described main frame connects the other end of described cutting-off switch, the digital end of described system host is connected to described digital module circuit interface one end of the described digital parallel bus other end by described cutting-off switch, and the described digital module circuit interface other end is connected to described system digits modular circuit by described digital parallel bus; The analog end of described system host connects the described system simulation modular circuit of the described simulation parallel bus other end by described cutting-off switch.

The layout of described system bus is three plug sockets, every row's 64 pins, and three rows are totally 192 pins.

Described system bus signal is divided into system's pin signal, address data bus signal, system's control bus signal, iic bus signal, IIS bus signals, self-defined expansion IO, LCD Interface signal, touch screen signal, system module selection signal and power supply signal; Described system pin signal packet is drawn together CLKo, nRESET, CLKi and RESET, described address data bus signal comprises D[15:0] and A[19:0], described system control bus signal comprises nCS[1:0], INT[1:0], nWE, nOE, nACK and nWAIT, described iic bus signal comprises SCL and SDA, described IIS bus signals comprises I2SLRCK, I2SSDO, I2SSDI, I2SSCLK, and CDCLK, described self-defined expansion IO comprises MCUIO[0:9] and PLDIO[0:21], described LCD Interface signal comprises VD[23:0], LCD_PWREN, VCLK, VFRAME, VLINE, VM, VSYNC, HSYNC, VDEN and LEND, described touch screen signal comprises nXPON, XMON, nYPON and YMON, described system module selects signal to comprise arm_nOE, dsp_nOE, mcu_nOE and sopc_nOE, described power supply signal comprises VCC5, VCC12, VCC-12, VCC3P3 and GND.

Described system host comprises one or more in ARM system, Single Chip Microcomputer (SCM) system, SOPC system and the dsp system, realize communication by Serial Port Line, netting twine or self-defined mode between the described system host, synchronization can only have a described system host to connect described system bus.

Described system host module board is provided with level shifting circuit.

Described data bus is provided with driving circuit, and it is by read-write logic control data outbound course.

Described data bus is provided with driving circuit, and it is by read-write logic control data outbound course.

The present invention is owing to take above technical scheme, and it has the following advantages: 1, owing to the invention provides a kind of universal bus system, so greatly reduce the design cycle of evaluating system, technology is also fairly simple.2, owing to the invention provides the bus structure of complicated circuit, so can set up needed evaluating system quickly and easily.3, because bus of the present invention can connect different numerals and analogue unit circuit, the user can be provided with bus, constitutes the device architecture of required emulation, so improved estimating velocity greatly, increases the reliability of integrated circuit (IC) design simultaneously.The present invention can be widely used in the assessment test macro of complicated circuit.

Description of drawings

Fig. 1 is a system architecture synoptic diagram of the present invention

Fig. 2 is that the CPLD expansion IO of system host of the present invention realizes block diagram

Fig. 3 is the write sequential chart of system host of the present invention to peripheral system digital-to-analog modular circuit

Fig. 4 is the read sequential chart of system host of the present invention to peripheral system digital-to-analog modular circuit

Fig. 5 is a system bus schematic layout pattern of the present invention

Embodiment

Below in conjunction with drawings and Examples, the present invention is described in detail.

As shown in Figure 1, the present invention is made up of system host 1, system bus 2, digital module circuit interface 3, system digits modular circuit 4 and system simulation modular circuit 5, wherein, system bus 2 comprises digital parallel system bus 21 and simulation parallel system bus 22, and these buses all are divided into data bus, control bus and address bus three classes.

System host 1 is a main body of the present invention, comprise ARM (a kind of risc processor that Advance RISC Machine company produces) system, Single Chip Microcomputer (SCM) system, SOPC (System On Programmable Chip, the programmable logic system that ALTERA company produces) system and DSP (digital signal processor, digital signal processor) one or more in the system, communicate by Serial Port Line or netting twine between them, also can according to circumstances define (as shown in Figure 2) voluntarily, as CPLDIO is the IO of CPLD/FPGA expansion on the system host 1, be to realize by the IO that CPLD expands, wherein MCUIO is the IO on the core controller on the system host 1, and A and B are socket.The interconnected interface flexibly that provides between the different system all is provided aforesaid way.System host 1 is by system bus 2 control external system digital module circuit 4 and system simulation modular circuits 5 (control timing as shown in Figure 3, Figure 4).

The two ends of digital module circuit interface 3 are respectively by digital parallel bus 21 connected system main frames 1 and system digits modular circuit 4, guarantee to realize seamless link between the digital circuitry of varying level, mainly play the effect of level conversion.

System digits modular circuit 4 can be the bus-structured digital display circuit of any the present invention of having, and they realize mutual connection by digital parallel bus 21.

System simulation modular circuit 5 can be the system that 200MHz voltage controlled oscillator, 10-bit comparer, the direct comparator circuit of the two poles of the earth 4-bit, pipeline module circuit, coding circuit and the integration that is made of the 200MHz operational amplifier, differential, amplification, low-pass filter and Hi-pass filter and assessment contain the integrated circuit structure of A/D change-over circuit.

If between any two system hosts 1 or system host 1 different with the level signal of 4,5 of modules, for example the level of DSP is 3.3V, the signal of CPLD is 5V, then need increase level shifting circuit on the module board of separately system host 5V signal, makes it reach 3.3V.The present invention advises the unified 3.3V of employing of all system modules power supply, and for module undesirable, that need carry out level conversion, the recommendation level transferring chip is CBTD16210.

For data bus, if need data quantity transmitted very big, so, for buffering need add driving circuit such as chip 74HC16245 (a kind of 16 tunnel bidirectional buffering chips), by read-write logic control outbound course.Because synchronization can only have a system host 1 control system bus 2, so the end at system bus 2 connects a cutting-off switch, system host 1 is linked the other end of cutting-off switch, guarantees that synchronization has only the IO resource that a block system main frame can using system bus 2.The level signal of system bus 2 is used 3.3V.

The layout of total system bus 2 (as shown in Figure 5) is: ABC is three plug sockets, single 64 pins, and three rows are totally 192 pins.Physical feature is the carrier of total system bus.The signal of system bus 2 is described (seeing Table 1) according to packet mode, and wherein I represents input signal, and O represents output signal, and IO represents input/output signal.

Table 1

Signal name	Input/output state	Describe
			Bus
D[15:0]	IO	Data bus needs to connect low eight D[7:0 at least]
			A[19:0]	O	Address bus, low 5 A[4:0] must connect
nCS[1:0]	O	Sheet choosing (low level is effective)
			INT[1:0]	I	The processor external interrupt signal
CLKo	O	The modular system clock output signal
			CLKi	I	The external clock input signal
nRESET	I	Reset signal (low level is effective)
			RESET	I	Reset signal (high level is effective) is not as need not connecting
nWE	O	Write signal (low level is effective)
			nOE	O	Read signal (low level is effective)
nACK	I	Return and confirm handshake (low level is effective)
			nWAIT	I	Waiting signal (low level is effective)
Iic bus
			SCL	IO	The iic clock signal
SDA	IO	The iic data-signal
			The IIS bus
I2SLRCK	IO	Audio frequency IIS channel selecting clock
			I2SSDO	O	The output of audio frequency IIS serial data
I2SSDI	I	The input of audio frequency IIS serial data
			I2SSCLK	IO	Audio frequency IIS serial clock
CDCLK	O	The CODEC system clock
			Processor IO expansion
MCUIO[0:9]	IO	The IO spread signal of each module handler
			The PLDIO expansion
PLDIO[0:21]	IO	The expansion of programmable logic device (PLD) IO on each module
			Liquid crystal pin (ARM special use)
VD[23:0]	O	The LCD data bus
			LCD_PWREN	O	LCD power enable control signal
VCLK	O	The LCD clock signal
			VFRAME	O	The LCD frame signal
VLINE	O	The capable signal of LCD
			VM	O	Ranks voltage electrode switching signal
VSYNC	O	Vertical synchronizing signal
			HSYNC	O	Horizontal-drive signal
VDEN	O	Data enable signal
			LEND	O	The end of line signal
Touch screen signal (ARM special use)
			nXPON	I	+ X-axis switch controlling signal

XMON	I	-X-axis switch controlling signal
			nYPON	I	+ Y-axis switch controlling signal
YMON	I	-Y-axis switch controlling signal
			The selection signal is noted: arbitrary moment can only have one effectively, and is effectively low
arm_nOE	?I	Arm system output enable end 0: the permission system uses external module resource 1: not fair external module is permitted to use the external module resource
			dsp_nOE	?I	Dsp system output enable end 0: the permission system uses external module resource 1: not permission system uses the external module resource
mcu_nOE	?I	Mcu system output enable end 0: the permission system uses external module resource 1: not permission system uses the external module resource
			sopc_nOE	?I	Sopc system output enable end 0: the permission system uses external module resource 1: not permission system uses the external module resource
Power supply ground
			VCC5		5 volts of power supplys
VCC12		12 volts of power supplys
			VCC-12		-12 volts of power supplys
VCC3P3		3.3 volt power supply
			GND		Earth signal

System's pin signal packet is drawn together:

The CLKo clock output signal is for all bus apparatus provide clock signal, except INT[1:0] and the nRESET signal, the rising edge that other all sequential circuits all pass through CLKo triggers, system clock frequency is operated in 0-100MHz.

NRESET is the low prosposition signal of replying by cable of system's output, all registers and signal on the bus is returned to original state, with the signal asynchronous work of CLKo;

CLKi is that optional signal is operated in 0-100MHz by the clock signal of external module to the system host input;

RESET is the high level reset signal of system's output, and is optional, is used for high level reset device on the resetting system module.

The address data bus signal comprises:

D[15:0] be 16 I/O data buss of independence that system bus had;

A[19:0] be 20 OPADD buses of independence that system bus had, addressable 1M space.

System's control bus signal comprises:

NCS[1:0] be the bus chip selection signal of system output, two 1M address spaces of addressable;

INT[1:0] for the system bus look-at-me of input, produce by system module, in order to the interrupt system main frame;

NWE belongs to output signal, and system host is effective during to the system module writing information;

NOE belongs to output signal, and is effective during system host reading system module information;

NACK belongs to input signal, the system module confirmation signal;

NWAIT belongs to input signal, prolongs the system host bus cycle signal, and when nWAIT was low level, the current bus cycles can not complete operation.

The iic bus signal comprises:

SCL is the iic bus clock signal, belongs to input/output signal;

SDA is the iic bus data-signal, belongs to input/output signal.

The IIS bus signals comprises:

I2SLRCK selects clock signal for the IIS bus run, belongs to input/output signal;

I2SSDO is the output of IIS serial data;

I2SSDI is the input of IIS serial data;

I2SSCLK is the IIS serial clock signal, belongs to input/output signal;

CDCLK is the CODEC clock signal of system, belongs to output signal.

Self-defined expansion IO comprises:

MCUIO[0:9] be that the system host processor is expanded IO;

PLDIO[0:21] for system host CPLD expansion IO,, can carry out the IO expansion to finish specific operation by programming device on the system host because system host processor IO can not cooperate bus to finish some specific time sequence.

The LCD Interface signal comprises:

VD[23:0] be the liquid crystal display data bus, be used for data output;

LCD_PWREN is the liquid crystal display switch controlling signal, belongs to output signal;

VCLK is the output of liquid crystal display clock;

VFRAME is the output of liquid crystal display frame signal;

VLINE is the capable signal output of liquid crystal display;

VM alternately changes the row and column polarity of voltage of pixel, belongs to output signal;

VSYNC is the output of row synchronizing signal;

HSYNC is line synchronizing signal output;

VDEN is a data enable signal, belongs to output signal;

LEND belongs to output signal for the row end signal.

Touch screen signal comprises:

NXPON is a touch-screen X-axis positive signal;

XMON is a touch-screen X-axis negative signal;

NYPON is a touch-screen Y-axis positive signal;

YMON is a touch-screen Y-axis negative signal.

System module selects signal to comprise:

Arm_nOE belongs to input signal, and when this signal was effective, system host was the ARM module;

Dsp_nOE belongs to input signal, and when this signal was effective, system host was the DSP module;

Mcu_nOE belongs to input signal, and when this signal was effective, system host was the MCU module;

Sopc_nOE belongs to input signal, and when this signal was effective, system host was the SOPC module.

Power supply signal comprises:

VCC5 is system's primary power (a 5V power supply), and maximum current 5A satisfies most of module for power supply demand;

VCC12 is the 12V power supply, and is optional, and specific demand is used;

VCC-12 is-the 12V power supply that optional, specific demand is used;

VCC3P3 is the 3.3V power supply, system host operating voltage, maximum operating currenbt 3A;

GND is an earth signal.

A, B, C respectively arrange putting in order of bus and are expressed as follows (shown in table 2, table 3, table 4) successively:

Table 2

Sequence number	Title	Purposes	Sequence number	Title	Purposes
						A1	?VCC5	The 5V power supply	?A2	?GND	Ground
A3	?MCUIO0	Processor IO	?A4	?MCUIO1	Processor IO
						A5	?MCUIO2	Processor IO	?A6	?MCUIO3	Processor IO
A7	?MCUIO4	Processor IO	?A8	?MCUIO5	Processor IO
						A9	?MCUIO6	Processor IO	?A10	?MCUIO7	Processor IO
A11	?MCUIO8	Processor IO	?A12	?MCUIO9	Processor IO
						A13	?VCC3P3	3.3V power supply	?A14	?VCC3P3	3.3V power supply
A15	?GND	Ground	?A16	?GND	Ground
						A17	?PLDIO0	PLD expands IO	?A18	?PLDIO1	PLD expands IO
A19	?PLDIO2	PLD expands IO	?A20	?PLDIO3	PLD expands IO
						A21	?PLDIO4	PLD expands IO	?A22	?PLDIO5	PLD expands IO
A23	?VCC3P3	3.3V power supply	?A24	?VCC3P3	3.3V power supply
						A25	?GND	Ground	?A26	?GND	Ground
A27	?PLDIO6	PLD expands IO	?A28	?PLDIO7	PLD expands IO
						A29	?GND	Ground	?A30	?GND	Ground
A31	?PLDIO8	PLD expands IO	?A32	?PLDIO9	PLD expands IO
						A33	?PLDIO10	PLD expands IO	?A34	?PLDIO11	PLD expands IO
A35	?PLDIO12	PLD expands IO	?A36	?PLDIO13	PLD expands IO
						A37	?PLDIO14	PLD expands IO	?A38	?PLDIO15	PLD expands IO

A39	?VCC3P3	3.3V power supply	A40	?VCC3P3	3.3V power supply
						A41	?GND	Ground	A42	?CLKo	Clock output (clock that module outwards provides)
A43	?PLDIO16	PLD expands IO	A44	?PLDIO17	PLD expands IO
						A45	?PLDIO18	PLD expands IO	A46	?PLDIO19	PLD expands IO
A47	?PLDIO20	PLD expands IO	A48	?PLDIO21	PLD expands IO
						A49	?VCC3P3	3.3V power supply	A50	?VCC3P3	3.3V power supply
A51	?GND	Ground	A52	?I2SLRCK	The IIS signal
						A53	?CLKi	Clock input (the outside clock that provides to module)	A54	?I2SSDO	The IIS signal
A55	?RESET	(effectively high) resets	A56	?I2SSDI	The IIS signal
						A57	?GND	Ground	A58	?I2SSCLK	The IIS signal
A59	?VCC12	The 12V power supply	A60	?CDCLK	The IIS signal
						A61	?VCC-12	-12V power supply	A62	?GND	Ground
A63	?VCC5	The 5V power supply	A64	?VCC5	The 5V power supply

Table 3

Sequence number	Title	Purposes	Sequence number	Title	Purposes
						?B1	?VCC5	The 5V power supply	?B2	?GND	Ground
?B3	?D0	Data bus 0	?B4	?D1	Data bus 1
						?B5	?D2	Data bus 2	?B6	?D3	Data bus 3
?B7	?D4	Data bus 4	?B8	?D5	Data bus 5
						?B9	?D6	Data bus 6	?B10	?D7	Data bus 7
?B11	?D8	Data bus 8	?B12	?D9	Data bus 9
						?B13	?D10	Data bus 10	?B14	?D11	Data bus 11
?B15	?VCC3P3	3.3V power supply	?B16	?GND	Ground
						?B17	?D12	Data bus 12	?B18	?D13	Data bus 13
?B19	?D14	Data bus 14	?B20	?D15	Data bus 15
						?B21	?GND	Ground	?B22	?GND	Ground
?B23	?A0	Address bus 0	?B24	?A1	Address bus 1
						?B25	?A2	Address bus 2	?B26	?A3	Address bus 3
?B27	?A4	Address bus 4	?B28	?A5	Address bus 5
						?B29	?A6	Address bus 6	?B30	?A7	Address bus 7
?B31	?A8	Address bus 8	?B32	?A9	Address bus 9
						?B33	?A10	Address bus 10	?B34	?A11	Address bus 11
?B35	?A12	Address bus 12	?B36	?A13	Address bus 13
						?B37	?A14	Address bus 14	?B38	?GND	Ground
?B39	?A15	Address bus 15	?B40	?A16	Address bus 16
						?B41	?A17	Address bus 17	?B42	?A18	Address bus 18

B43	?A19	Address bus 19	?B44	?GND	Ground
						B45	?nCS0	Chip selection signal 0	?B46	?nCS1	Chip selection signal 1
B47	?INT0	Interrupt request singal 0	?B48	?INT1	Interrupt request singal 1
						B49	?VCC3P3	3.3V power supply	B50	?nRESET	Reset signal (effectively low)
B51	?nWE	Write signal	B52	?nACK	Confirm handshake (from outside load module)
						B53	?nOE	Output enable	B54	?GND	Ground
B55	?nWAIT	Waiting signal	B56	?SDA	The IIC data-signal
						B57	?VCC3P3	3.3V power supply	B58	?arm_nOE	The arm plate enables
B59	?SCL	The IIC clock signal	B60	?dsp_nOE	The dsp plate enables
						B61	?mcu?nOE	The mcu plate enables	B62	?sopc_nOE	The sopc plate enables
B63	?VCC5	The 5V power supply	B64	?VCC5	The 5V power supply

Table 4

Sequence number	Title	Purposes	Sequence number	Title	Purposes
						C1	?VCC5	The 5V power supply	?C2	?GND	Ground
C3	?VD0	Liquid crystal data 0	?C4	?VD1	Liquid crystal data 1
						C5	?VD2	Liquid crystal data 2	?C6	?VD3	Liquid crystal data 3
C7	?VD4	Liquid crystal data 4	?C8	?VD5	Liquid crystal data 5
						C9	?VD6	Liquid crystal data 6	?C10	?VD7	Liquid crystal data 7
C11	?VD8	Liquid crystal data 8	?C12	?VD9	Liquid crystal data 9
						C13	?VD10	Liquid crystal data 10	?C14	?VD11	Liquid crystal data 11
C15	?VD12	Liquid crystal data 12	?C16	?VD13	Liquid crystal data 13
						C17	?VCC3P3	3.3V power supply	?C18	?GND	Ground
C19	?VD14	Liquid crystal data 14	?C20	?VD15	Liquid crystal data 15
						C21	?VD16	Liquid crystal data 16	?C22	?VD17	Liquid crystal data 17
C23	?GND	Ground	?C24	?GND	Ground
						C25	?VD18	Liquid crystal data 18	?C26	?VD19	Liquid crystal data 19
C27	?VD20	Liquid crystal data 20	?C28	?VD21	Liquid crystal data 21
						C29	?GND	Ground	?C30	?GND	Ground
C31	?VD22	Liquid crystal data 22	?C32	?VD23	Liquid crystal data 23
						C33	?VD24	Liquid crystal data 24	?C34	?GND	Ground
C35	?GND	Ground	?C36	?GND	Ground
						C37	?VCC3P3	3.3V power supply	?C38	?VLINE	The capable signal of liquid crystal
C39	?GND	Ground	?C40	?GND	Ground
						C41	?LCD_PWREN	Power supply signal	?C42	?VFRAME	The lcd frame signal
C43	?VCC3P3	3.3V power supply	?C44	?LEND	The liquid crystal signal
						C45	?VCLK	The liquid crystal signal	?C46	?GND	Ground
C47	?GND	Ground	?C48	?VDEN	The liquid crystal signal
						C49	?GND	Ground	?C50	?GND	Ground

C51	?nXPON	Touch screen signal	C52	?HSYNC	The liquid crystal signal
						C53	?XMON	Touch screen signal	C54	?GND	Ground
C55	?nYPON	Touch screen signal	C56	?VSYNC	The liquid crystal signal
						C57	?YMON	Touch screen signal	C58	?GND	Ground
C59	?GND	Ground	C60	?VM	The liquid crystal signal
						C61	?VCC3P3	3.3V power supply	C62	?GND	Ground
C63	?VCC5	The 5V power supply	C64	?GND	Ground

The invention provides an evaluating system bus that can connect 100MHz clock frequency, 200MHz simulating signal.Bus can connect different digital circuit devices and analogue unit circuit, and the user can be provided with its bus, thereby constitutes the device architecture of required emulation, can improve estimating velocity greatly, increases the reliability of integrated circuit (IC) design.

Although disclose specific embodiments of the invention and accompanying drawing for the purpose of illustration, its purpose is to help to understand content of the present invention and implement according to this, but it will be appreciated by those skilled in the art that: without departing from the spirit and scope of the invention and the appended claims, various replacements, variation and modification all are possible.Therefore, the present invention should not be limited to most preferred embodiment and the disclosed content of accompanying drawing, and the scope of protection of present invention is as the criterion with the scope that claims define.

Claims (10)

1, a kind of complicated circuit system universal bus is characterized in that: it comprises system host, system bus, digital module circuit interface, system digits modular circuit and system simulation modular circuit; Described system bus comprises digital parallel system bus and simulation parallel system bus, they are divided into control bus, address bus and data bus, one end of described bus system connects a cutting-off switch, described main frame connects the other end of described cutting-off switch, the digital end of described system host is connected to described digital module circuit interface one end of the described digital parallel bus other end by described cutting-off switch, and the described digital module circuit interface other end is connected to described system digits modular circuit by described digital parallel bus; The analog end of described system host connects the described system simulation modular circuit of the described simulation parallel bus other end by described cutting-off switch.

2, a kind of complicated circuit system universal bus as claimed in claim 1 is characterized in that: the layout of described system bus is three plug sockets, every row's 64 pins, and three rows are totally 192 pins.

3, a kind of complicated circuit system universal bus as claimed in claim 1 is characterized in that: described system bus signal is divided into system's pin signal, address data bus signal, system's control bus signal, iic bus signal, IIS bus signals, self-defined expansion IO, LCD Interface signal, touch screen signal, system module selection signal and power supply signal; Described system pin signal packet is drawn together CLKo, nRESET, CLKi and RESET, described address data bus signal comprises D[15:0] and A[19:0], described system control bus signal comprises nCS[1:0], INT[1:0], nWE, nOE, nACK and nWAIT, described iic bus signal comprises SCL and SDA, described IIS bus signals comprises I2SLRCK, I2SSDO, I2SSDI, I2SSCLK, and CDCLK, described self-defined expansion IO comprises MCUIO[0:9] and PLDIO[0:21], described LCD Interface signal comprises VD[23:0], LCD_PWREN, VCLK, VFRAME, VLINE, VM, VSYNC, HSYNC, VDEN and LEND, described touch screen signal comprises nXPON, XMON, nYPON and YMON, described system module selects signal to comprise arm_nOE, dsp_nOE, mcu_nOE and sopc_nOE, described power supply signal comprises VCC5, VCC12, VCC-12, VCC3P3 and GND.

4, a kind of complicated circuit system universal bus as claimed in claim 2 is characterized in that: described system bus signal is divided into system's pin signal, address data bus signal, system's control bus signal, iic bus signal, IIS bus signals, self-defined expansion IO, LCD Interface signal, touch screen signal, system module selection signal and power supply signal; Described system pin signal packet is drawn together CLKo, nRESET, CLKi and RESET, described address data bus signal comprises D[15:0] and A[19:0], described system control bus signal comprises nCS[1:0], INT[1:0], nWE, nOE, nACK and nWAIT, described iic bus signal comprises SCL and SDA, described IIS bus signals comprises I2SLRCK, I2SSDO, I2SSDI, I2SSCLK, and CDCLK, described self-defined expansion IO comprises MCUIO[0:9] and PLDIO[0:21], described LCD Interface signal comprises VD [23:0], LCD_PWREN, VCLK, VFRAME, VLINE, VM, VSYNC, HSYNC, VDEN and LEND, described touch screen signal comprises nXPON, XMON, nYPON and YMON, described system module selects signal to comprise arm_nOE, dsp_nOE, mcu_nOE and sopc_nOE, described power supply signal comprises VCC5, VCC12, VCC-12, VCC3P3 and GND.

5, as claim 1 or 2 or 3 or 4 described a kind of complicated circuit system universal bus, it is characterized in that: described system host comprises one or more in ARM system, Single Chip Microcomputer (SCM) system, SOPC system and the dsp system, realize communication by Serial Port Line, netting twine or self-defined mode between the described system host, synchronization can only have a described system host to connect described system bus.

6, as claim 1 or 2 or 3 or 4 described a kind of complicated circuit system universal bus, it is characterized in that: described system host module board is provided with level shifting circuit.

7, a kind of complicated circuit system universal bus as claimed in claim 5 is characterized in that: described system host module board is provided with level shifting circuit.

8, as claim 1 or 2 or 3 or 4 or 7 described a kind of complicated circuit system universal bus, it is characterized in that: described data bus is provided with driving circuit, and it is by read-write logic control data outbound course.

9, a kind of complicated circuit system universal bus as claimed in claim 5, it is characterized in that: described data bus is provided with driving circuit, and it is by read-write logic control data outbound course.

10, a kind of complicated circuit system universal bus as claimed in claim 6, it is characterized in that: described data bus is provided with driving circuit, and it is by read-write logic control data outbound course.

Images