CN101079546A

CN101079546A - Surge restraint circuit

Info

Publication number: CN101079546A
Application number: CN 200610060791
Authority: CN
Inventors: 彭敏; 甘小林; 何友光
Original assignee: Hongfujin Precision Industry Shenzhen Co Ltd; Hon Hai Precision Industry Co Ltd
Current assignee: Hongfujin Precision Industry Shenzhen Co Ltd; Hon Hai Precision Industry Co Ltd
Priority date: 2006-05-26
Filing date: 2006-05-26
Publication date: 2007-11-28
Anticipated expiration: 2026-05-26
Also published as: CN100502195C

Abstract

The invention discloses a surge inhibiting circuit, which comprises the following parts: voltage input end, voltage output end, field effect pipe, transistor, capacitance, first resistance, second resistance, wherein the voltage input end connects the source pole of field effect pipe and launching pole of transistor, which also connects the leak pole of field effect pipe through first resistance; the integral electrode of transistor connects ground through the second resistance; the basic pole of transistor connects the integral electrode of transistor and grid and leak pole of field effect pipe; the leak of field effect pipe connects ground through capacitance; the leak pole of field effect pipe connects the voltage output end. The invention can inhibit surge voltage effectively, which reduces the power consumption of stable working effectively due to little inner resistance of transistor and also provides short-circuit load protecting function.

Description

Surge restraint circuit

Technical field

The present invention relates to a kind of power protecting circuit, particularly a kind of surge restraint circuit.

Background technology

Mains switch moment can produce surge voltage and surge current, and surge voltage and surge current are excessive will to damage electrical appliance or power supply inner member.Industry utilizes negative tempperature coefficient thermistor (NTC) to suppress surge voltage usually, utilize NTC under the normal temperature state, to have higher resistance value and come limit inrush currents, power on the back because electric current makes its heating by NTC, thereby its resistance value is reduced to reduce power loss.This kind method is simple, but the problem that exists is that the limit inrush currents performance is influenced by the initial temperature of ambient temperature and NTC, higher or at power-on time at interval very in short-term, NTC does not have the effect of limit inrush currents, promptly can't suppress surge voltage in ambient temperature.

Industry another kind of surge inhibition method commonly used is to adopt series limiting resistor, and the advantage of this method is simple, and the reliability height allows to work in wide environmental temperature range, and its shortcoming is lossy on the current-limiting resistance, has reduced power-efficient.In fact power supply start and be in steady operation after, the metering function of this current-limiting resistance is finished, only plays the negative interaction of consumed power, heating.

Summary of the invention

In view of above content, be necessary to provide a kind of surge restraint circuit, the surge voltage that produces in the time of can effectively suppressing mains switch, and when the power supply steady operation, do not influence voltage output, reduce non-essential power loss.

A kind of surge restraint circuit, comprise a voltage input end, one voltage output end, one field effect transistor, one transistor, one electric capacity, one first resistance and one second resistance, described voltage input end is connected with the source electrode and the described transistorized emitter of described field effect transistor respectively, described voltage input end also is connected with the drain electrode of described field effect transistor by described first resistance, described transistorized collector electrode is by described second grounding through resistance, described transistorized base stage is connected with drain electrode with the grid of described transistorized collector electrode and described field effect transistor respectively, the drain electrode of described field effect transistor is by capacity earth, and the drain electrode of described field effect transistor also is connected with described voltage output end.

The invention provides a kind of surge restraint circuit, can effectively suppress surge voltage, and because the field effect transistor internal resistance is less, the power loss when effectively reducing steady operation can provide the short circuit load protection function in addition.

Description of drawings

Below in conjunction with accompanying drawing and better embodiment the present invention is described in further detail:

Fig. 1 is the circuit diagram of surge restraint circuit better embodiment of the present invention.

Embodiment

Please refer to Fig. 1, surge restraint circuit 10 of the present invention comprises a voltage input end Vin, one voltage output end Vout, one field effect transistor Q1, one transistor Q2, one capacitor C and two resistance R 1 and R2, described field effect transistor Q1 is the N channel power MOS pipe, described transistor Q2 is ambipolar PNP transistor, described voltage input end Vin is connected with the source S of described field effect transistor Q1 and the emitter E of described transistor Q2 respectively, described voltage input end Vin also is connected with the drain D of described field effect transistor Q1 by described resistance R 1, the collector electrode C of described transistor Q2 is by described resistance R 2 ground connection, the base stage B of described transistor Q2 is connected with drain D with the collector electrode C of described transistor Q2 and the grid G of described field effect transistor Q1 respectively, the drain D of described field effect transistor Q1 is by capacitor C ground connection, and the drain D of described field effect transistor Q1 also is connected with described voltage output end Vout.

Described voltage input end Vin is with after an external power source is connected, when external power source is opened, described surge restraint circuit 10 starts, described transistor Q2 conducting, make described field effect transistor Q1 keep disconnecting, till the voltage at described capacitor C two ends is elevated to when being enough to turn-off described transistor Q2, at this moment between in the section, described resistance R 1 provides starting current for other assembly in capacitor C and the surge restraint circuit 10.When described capacitor C both end voltage rising makes the pressure drop of described transistor Q2 be lower than conducting voltage, described transistor Q2 disconnects, described field effect transistor Q1 conducting also provides a low-resistance transmission channel at described resistance R 1 two ends, and the input voltage of described voltage input end Vin exports an electrical appliance to from described voltage output end Vout.Close when external power source and to make voltage input end Vin no-voltage when input, described surge restraint circuit 10 resets with the capacitor C discharge.

In addition, along with the electric current by field effect transistor Q1 increases, the pressure drop at described field effect transistor Q1 two ends also increases owing to there is conducting resistance in its inside, when the voltage at described field effect transistor Q1 two ends is reduced to about 0.6V, when promptly equaling the conducting voltage of described transistor Q2, described transistor Q2 conducting and described field effect transistor Q1 disconnect, and force load current to pass through resistance R 1, and load current is reduced.Therefore, when described electrical appliance was short-circuited, described surge restraint circuit 10 can reduce load current by resistance R 1; effectively protection power supply and electrical appliance are not short-circuited and burn; after short circuit was eliminated, transistor Q2 disconnected and field effect transistor Q1 conducting, and circuit recovers operate as normal.Because the conducting resistance of described field effect transistor Q1 is served as the detection resistor of short circuit load protection function; so the short circuit threshold current can change with the characteristic of described field effect transistor Q1, can adjust the conducting of described field effect transistor Q1 and disconnect threshold values by the on-resistance characteristics of selecting resistance R 1 value and described field effect transistor Q1.

Above-mentioned surge restraint circuit 10 not only can effectively suppress surge voltage; and reduced the power loss of surge circuit; and the short circuit load protection function is provided, and can effectively protect power supply and electrical appliance not influenced by surge voltage, guarantee the steady operation of power supply and electrical appliance.

Claims

1. surge restraint circuit, comprise a voltage input end, one voltage output end, one field effect transistor, one transistor, one electric capacity, one first resistance and one second resistance, described voltage input end is connected with the source electrode and the described transistorized emitter of described field effect transistor respectively, described voltage input end also is connected with the drain electrode of described field effect transistor by described first resistance, described transistorized collector electrode is by described second grounding through resistance, described transistorized base stage is connected with drain electrode with the grid of described transistorized collector electrode and described field effect transistor respectively, the drain electrode of described field effect transistor is by capacity earth, and the drain electrode of described field effect transistor also is connected with described voltage output end.

2. surge restraint circuit as claimed in claim 1 is characterized in that: described field effect transistor is the N channel power MOS pipe.

3. surge restraint circuit as claimed in claim 1 or 2 is characterized in that: described transistor is ambipolar PNP transistor.