CN101079230A - Memory controller and memory control method, rate converting device and method, and image signal processing apparatus and method - Google Patents
Memory controller and memory control method, rate converting device and method, and image signal processing apparatus and method Download PDFInfo
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Abstract
A luminance signal Ya and a color-difference signal Ua/Va constituting an input image signal is transferred to a frame memory (first memory) in the unit of line synchronously with its horizontal synchronous signal and written therein. A memory TG211 reads out a read-out request RRQ. The cycle of this request RRQ is a time computed based on a single vertical effective period of an output image signal Sc and the number of lines objective for rate conversion of an input image signal Sa. The luminance signal Ya and color-difference signal Ua/Va are transferred in the unit of line from the frame memory to rate conversion units (second memory) through buffers. There occurs no deflection in this transfer cycle and in each transfer cycle, the stable data transmission band can be secured.
Description
The application is to be on August 19th, 2004 applying date, and application number is 200410082227.1, and title is divided an application for the patented claim of " memory controller and method, rate converting device and method, image signal processing apparatus and method ".
Technical field
The present invention relates to memory controller, storage controlling method, rate converting device, rate conversion method, image signal processing apparatus, image-signal processing method and be used for carrying out each program of said method.
More specifically, the present invention relates to memory controller more suitable when converting pixel count to another or the like for display.
Background technology
Known display has flat-panel screens, LCD (LCD), plasma display (PDP) etc.The sharpness of the picture quality of these three kinds of displays depends on the quantity of the pixel on its vertical direction and the horizontal direction.For example, there has been standard as XGA (768 * 1024 pixel), SXGA (1024 * 1280 pixel) etc.
In addition, for this picture signal, normally used have 480i signal, 720p signal, a 1080i signal etc.Here, these numeric representation line numbers, " i " expression interlacing type, and " p " represents type line by line.For example, the 480i signal has 720 * 480 resolution, and the 720p signal has 1024 * 720 resolution, and the 1080i signal has 1920 * 1080 resolution.
According to routine, in image display device, convert pixel count to another so that part or all of received image signal is presented on its display.In this case, rate converting device is used for the pixel count on the vertical direction and horizontal direction on the crossover display terminal.
Above-mentioned rate converting device can comprise a first memory and a second memory, and wherein, first memory for example is the high capacity frame memory of burst transmissions type, and second memory is the dual-ported memory of random access type.In this device, received image signal is stored in the first memory temporarily, and continuously this picture signal is sent to second memory from first memory with behavior unit, and writes wherein.Then, in the pixel period and line period after conversion, from second memory, read this picture signal, to obtain output image signal.
Yet,, between first memory and second memory, be difficult to guarantee the stable data transport tape if used such transmission.Thereby such transmission provides less service efficiency.
In addition, in the rate converting device that has as above configuration, realize in first memory, writing picture signal/the read picture signal in the first memory by identical data bus.
In order to guarantee the stable data transport tape between first memory and the second memory, and improve service efficiency in the rate converting device with above-mentioned configuration, can expect, in the image signal transmission of each official hour execution from the first memory to the second memory.Like this, based on wherein writing request, picture signal is sent to first memory from write buffer, and writes therein by data bus.By data bus this picture signal is sent to sense buffer from first memory based on the request of reading on each official hour subsequently.At last, this picture signal is sent to second memory from this sense buffer.
Yet this depended on according to the write time that writes request, to carry out this read operation based on the request of reading of each official hour input.
In addition, in above-mentioned rate converting device, for example use the pixel data string of first picture signal, use the identical continuous mode of pixel data to be created on the pixel data string of the valid pixel part on the horizontal direction of second picture signal with ratio by the magnification ratio of respective number of pixels.
For example, if back level at such rate converting device, use the tap (tap) of some predetermined numbers to be provided for creating image signal processing unit in the horizontal direction corresponding to the new pixel data of each location of pixels of the valid pixel part of the horizontal direction of second picture signal, can imagine that this rate converting device has been created the tap of predetermined number in the horizontal direction corresponding to each location of pixels of the valid pixel part of the horizontal direction of second picture signal.
Yet this depends on the magnification ratio of pixel count, with before rate conversion, and the tap of the predetermined number of acquisition on the horizontal direction of the arrangement of the pixel data of this picture signal (first picture signal).Also based on the magnification ratio of this pixel count, the pixel data string input shift register of the picture signal after rate conversion is up to the tap change output start delay of predetermined quantity on register output horizontal direction for it.
First purpose of the present invention is to guarantee stable data transport tape between first memory and the second memory, and improves the service efficiency of transport tape.
Second purpose of the present invention is to carry out read operation on each official hour is read the basis of input of request, and does not rely on the write time of the request of writing.
The 3rd purpose of the present invention is the tap of the predetermined number on the horizontal direction of the arrangement of the pixel data that obtains picture signal (first picture signal) before the rate conversion, and does not rely on the magnification ratio of this pixel count.
The 4th purpose of the present invention is can fix in the startup output delay from the pixel data string input shift register of picture signal that will be rate conversion after, during up to the tap of exporting predetermined quantity on the horizontal direction from register on each row, and does not rely on the magnification ratio of this pixel count.
Summary of the invention
In order to reach purpose of the present invention, according to a first aspect of the invention, provide a kind of rate converting device.This device comprises: first memory is used for storing a received image signal temporarily; And second memory, be used to store the picture signal that transmits one by one with behavior unit from first memory, and the pixel period after conversion and line period read this picture signal, to obtain output image signal.This device also comprises controller, is used to control writing and reading first and second storeies.This controller is controlled at the transmission of each official hour picture signal that will carry out, from the first memory to the second memory.
According to a second aspect of the invention, provide a kind of rate conversion method.The method comprising the steps of: store received image signal temporarily in first memory, and at each official hour picture signal is sent to second memory with behavior unit from first memory one by one, and write picture signal therein.This method also comprises step: read this picture signal in pixel period after conversion and the line period from second memory, to obtain output image signal.
Relating to program of the present invention makes computing machine can carry out above-mentioned rate conversion method.
Relate to recording medium recording said procedure of the present invention.
According to the present invention, the picture signal of input is stored in the first memory temporarily.Then, second memory is stored the picture signal that sends from first memory with behavior unit one by one.Second memory after conversion pixel period and line period in read this picture signal to obtain output image signal.For example, first memory is to be made of burst transmissions type frame memory, and second memory is to be made of random access type dual-port line storage.
The transmission of the picture signal from the first memory to the second memory is carried out at each official hour.The cycle that is used to transmit is the time span that obtains by the single vertical effective period of dividing this output image signal with the quantity of the capable object of the conversion that is used for this received image signal fifty-fifty.Obtain change-over period t according to an equation, t=mo/mi/fo x no, wherein " fo " is the dot frequency of output image signal, " mi " is the quantity of capable object that is used for the conversion of this received image signal, " mo " is the line number of the single vertical effective period of output image signal, and " no " is the quantity of pixel in every row of described output image signal.
For example, if a plurality of second memories are arranged,, the picture signal of every row is sent to a plurality of second memories from first memory by same data bus in the transmission cycle of each time dividing mode.
When from second memory, reading this picture signal, in order to obtain the pixel of single horizontal cycle in the output image signal, this pixel is corresponding to the pixel of the predetermined quantity on the horizontal direction of received image signal, for example, repeatedly read based on ratio of this pixel count and definite intended pixel or make its thinning dredging.The predetermined quantity of this pixel is equal to or less than the pixel quantity of single image horizontal cycle.
When from second memory, reading this picture signal, in order to obtain the row of single vertical cycle in the output image signal, should be during this row in the row of the predetermined quantity on the vertical direction of received image signal, for example, repeatedly read based on ratio of this row and definite predetermined row by or make its thinning dredging.The predetermined quantity of this row is equal to or less than the quantity of the row of single vertical cycle.
As mentioned above, according to the present invention, input signal is temporarily stored in the first memory, and this picture signal is sent to second memory with behavior unit from first memory one by one.Then, obtain output image signal by reading picture signal from this second memory in pixel period after conversion and the line period.Thereby the transmission of output image signal from the first memory to the second memory carried out at each official hour.This can not cause taking place in the data transfer cycle deviation.Guaranteed that the stable data transport tape is logical between first memory and the second memory, thereby improved its use digit rate.Thereby, can improve in each data transfer cycle the quantity of row that can be sent to the picture signal of second memory from first memory.
If the picture signal of carrying out from the first memory to the second memory at each official hour does not transmit, it is unstable that data transfer cycle can become, so the data transmission band between first memory and the second memory is to lead to be stipulated by the higher level's cycle portions in the data transfer cycle, thereby has hindered the raising of service efficiency.
For example, controller comprises: write buffer, be used for interim memory image signal so that it is write first memory, and sense buffer, be used for the picture signal that interim storage is read from first memory.This controller also comprises and writes scalar/vector, is used to generate writing the address and reading scalar/vector of first memory, is used to generate the address of reading of first memory.This controller further comprises and writing/read-out control unit, be used for controlling this write buffer, sense buffer, write scalar/vector and reading scalar/vector based on the request of when delegation's picture signal is stored in write buffer, submitting to of reading that writes request and submit at every turn at each official hour.
Write/read-out control unit gives the right of priority of the right of priority of a control greater than another control, wherein, before control is based on the request of writing, by data bus picture signal is sent to first memory from write buffer, and picture signal is stored in wherein, that control of back is based on the request of reading, and by this data bus this picture signal is sent to sense buffer from first memory, and this picture signal is stored in wherein.This causes from first memory and reads picture signal, and is not subjected to the influence of the ratio of received image signal.
According to a third aspect of the invention we, provide a kind of image signal processing apparatus here, be used for converting first picture signal to second picture signal by the item design of some pixel datas by the item design of some pixel datas.This image signal processing apparatus comprises: the rate conversion device, with the phase information maker, wherein this rate conversion device is used to obtain to have the 3rd picture signal of pixel data, this pixel data is corresponding to the pixel data of forming this second picture signal based on this first picture signal, this phase information maker is used for generating the phase information of the target location of this second picture signal, this image signal processing apparatus also comprises the pixel data maker, be used for based on phase information by this phase information maker generation, use the 3rd picture signal, generate the pixel data of the target location in this second picture signal.
This rate conversion device comprises: first memory, be used for storing first picture signal temporarily, and second memory, be used for storing first picture signal that sends from this first memory with behavior unit one by one, and read this first picture signal in pixel period after conversion and the line period, to obtain the 3rd picture signal.The rate conversion device also comprises a controller, is used to control writing and reading this first memory and second memory.This controller is controlled at the transmission that each preset time is carried out the picture signal from this first memory to this second memory.
According to a fourth aspect of the present invention, provide a kind of image-signal processing method, be used for converting first picture signal to second picture signal by the item design of some pixel datas by the item design of some pixel datas.This conversion method comprises a rate conversion step, leads in obtaining to have the 3rd picture signal of pixel data, and this pixel data is corresponding to the pixel data of forming this second picture signal based on this first picture signal.This conversion method comprises that also phase information generates step, is used for generating the phase information of the target location of this second picture signal.This conversion method comprises that further pixel data generates step, based on generating the phase information that step generated by this phase information, uses the 3rd picture signal, generates the pixel data of the target location in second picture signal.In this rate conversion step, first picture signal is stored in the first memory temporarily.At each official hour, with behavior unit first picture signal is sent to second memory from first memory one by one, and writes second memory.Then, in the pixel period and line period after conversion, from second memory, read first picture signal, to obtain the 3rd picture signal.
So program according to the present invention makes computing machine can carry out above-mentioned picture signal conversion method.
Relate to recording medium recording said procedure of the present invention.
According to the present invention, change the pixel count of first picture signal, to obtain to have the 3rd picture signal of pixel data, this pixel data is corresponding to the pixel data of forming second picture signal.Further, generate the phase information of the target location in second picture signal.Then, use the 3rd picture signal, generate the pixel data of the target location in second picture signal based on this phase information.
For example use one to estimate that equation realizes the generation of this pixel data.That is to say, generate the coefficient data that uses in the estimation equation corresponding to this phase information.Based on the 3rd picture signal, extract near some projects of the pixel data the target location be arranged in second picture signal.Estimate equation based on this, use some projects of these coefficient datas and pixel data, calculate the pixel data of target location in second picture signal.
When using the coefficient data that obtains by such study processing, this study is handled and is used the teacher signal corresponding to second picture signal, and student signal corresponding to first picture signal, use the pixel data of the pixel data of such estimation equation generation, can have the higher degree of accuracy of pixel data that beguine obtains according to linear interpolation or the like as target location in second picture signal.
According to the present invention, when using this rate conversion device conversion ratio, carry out the transmission of the picture signal from the first memory to the second memory at each official hour.Because the cycle that these data transmit does not have deviation, can guarantee that the stable data transport tape between first memory and the second memory is logical, thereby improve its service efficiency.Thus, can increase in each cycle that data transmit, be sent to the line number of the picture signal of second memory from first memory, so that the pixel data maker can use more multirow, with higher degree of accuracy, generate the pixel data of the target location in second picture signal.
According to a fifth aspect of the invention, provide the memory controller that is used for control store, wherein by identical data bus, writing and reading this storer carries out image signal.This memory controller comprises write buffer, is used for storing received image signal so that this picture signal is write this storer temporarily, and sense buffer, and one is used for the output image signal that interim storage is read from this storer.This memory controller also comprises and writes scalar/vector, is used to generate the address that writes of described storer, and reads scalar/vector, is used to generate the address of reading of this storer.This memory controller further comprises a control module, be used for based on the request of at every turn when the received image signal of predetermined quantity is stored in this write buffer, submitting to that writes with in the request of reading of each official hour submission, control this write buffer, this sense buffer, this writes scalar/vector and this reads scalar/vector.First control writes request based on this, by data bus control received image signal is sent to this storer and stores this received image signal therein from this write buffer, second control is read request based on this, by the control of this data bus this output image signal is sent to this sense buffer and stores this output image signal therein from this storer, this control module is given in these two controls any with a right of priority greater than another one.
According to a sixth aspect of the invention, provide a kind of storage controlling method.This storage controlling method comprises first controlled step, when the picture signal of predetermined quantity is stored in this write buffer,, pass through data bus based on the request that writes of each submission, this picture signal is sent to a storer from this write buffer, and writes this picture signal therein.This method also comprises second controlled step, and the request of reading based on each official hour is submitted to is sent to sense buffer with this picture signal from this storer by this data bus, and writes this picture signal therein.In the method, write first controlled step of request based on this and be performed with a right of priority greater than another one based in second controlled step of the request of reading any.
Program related to the present invention makes computing machine can carry out above-mentioned storage controlling method.
The said procedure that related to recording medium recording of the present invention.
According to the present invention, when the picture signal of predetermined quantity is stored in this write buffer, write request based on of each submission, pass through data bus, this received image signal is sent to this storer from this write buffer, and writes this received image signal therein.Further, the request of reading based on each official hour is submitted to by this data bus, is sent to this sense buffer with output image signal from this storer, and writes wherein.
For example, storer comprises burst transmissions type frame memory, for example a SDRAM.If this storer is SDRAM, for instance, execution refreshes in the vertical blank cycle.For example, write in the request one corresponding to this, the individual picture signal of n (n is an integer) of single horizontal cycle is write this storer, and read in the request one corresponding to this, (m is an integer and m＞n) individual picture signal is read from this storer with the m of single horizontal cycle.
In this case, write control (first control) and read in the control (second controls) any based on this of writing request and have right of priority greater than another based on this of reading request.This makes by performed the writing and read modification and can be performed well of identical data bus, thereby can read output image signal based on the input of the request of reading at each official hour, and does not rely on the write time that this writes request.
For example, with one greater than giving based on the control that writes that writes request based on the right of priority of reading control of the request of reading.For example, when submission simultaneously writes request and reads request, write request based on this write operation is carried out in the storer, and hang up the request of reading.After write operation finishes,, carry out read operation from storer based on this request of reading that is suspended.
Read request if in the process of write store, submitted one to, then hang up this request of reading and after write operation finishes,, carry out read operation from this storer based on this request of reading that is suspended.Further, write request, then suspend this read operation, and write request, carry out writing this storer based on this if the process of reading, submitted one to from storer.After write operation finishes, read and be stopped the remainder of reading.
Because will read reading the stand-by period of request so can generate greater than giving based on the control that writes that writes request based on the right of priority of reading control of the request of reading based on this.For example, if write request corresponding to individual signals, " n " individual picture signal of single horizontal cycle is written into storer, and read request corresponding to individual signals, (m＞n) individual picture signal is read out " m " of single horizontal cycle, maximum latency becomes the cycle that is used for handling " n " picture signal so, under will be greater than the situation of reading control of giving based on the right of priority that writes control that writes request based on the request of reading, this period ratio be short based on the maximal value that writes the stand-by period (equaling m) that writes request.
According to a seventh aspect of the invention, provide another kind of rate converting device.This rate converting device comprises: first memory, be used for storing received image signal temporarily, and second memory, be used for storing the picture signal that sends from this first memory with behavior unit one by one, and read this received image signal in pixel period after conversion and the line period, to obtain output image signal.This device also comprises controller, is used to control writing and reading this first memory and second memory.
This controller comprises: write buffer, be used for storing received image signal so that this received image signal is write this first memory temporarily, and sense buffer, be used for the output image signal that interim storage is read from this first memory.This controller also comprises and writes scalar/vector, is used to generate the address that writes of this first memory, and reads scalar/vector, is used to generate the address of reading of this first memory.This controller comprises that further one writes/read-out control unit, be used for based on the request of at every turn when the received image signal of predetermined quantity is stored in this write buffer, submitting to that writes with in the request of reading of each official hour submission, control this write buffer, this sense buffer, this writes scalar/vector and this reads scalar/vector.First control writes request based on this, by data bus control received image signal is sent to this first memory and stores this received image signal therein from this write buffer, second control is read request based on this, by the control of this data bus this output image signal is sent to this sense buffer and stores this output image signal therein from this first memory, this control module is given in these two controls any with a right of priority greater than another one.
According to an eighth aspect of the invention, provide another kind of image signal processing apparatus here, be used for converting first picture signal to second picture signal by some item designs of pixel data by some item designs of pixel data.This device comprises: the rate conversion device, and phase information maker, wherein this rate conversion device is used to obtain to have the 3rd picture signal of pixel data, this pixel data is corresponding to the pixel data of forming this second picture signal based on this first picture signal, and this phase information maker is used for generating the phase information of the target location of this second picture signal.This device also comprises the pixel data maker, is used for using the 3rd picture signal based on the phase information by this phase information maker generation, generates the pixel data of the target location in this second picture signal.This rate conversion device comprises first memory, be used for storing this first picture signal temporarily, and second memory, be used for storing first picture signal that sends from this first memory with behavior unit one by one, and read this first picture signal in pixel period after conversion and the line period, to obtain the 3rd picture signal.This rate conversion device also comprises a controller, is used to control writing and reading this first memory and second memory.
This controller comprises: write buffer, be used for storing first picture signal so that it is write first memory temporarily, and sense buffer, be used for first picture signal that interim storage is read from this first memory.This controller also comprises and writes scalar/vector, is used to generate the address that writes of this first memory, and reads scalar/vector, is used to generate the address of reading of this first memory.This controller further comprises and writing/read-out control unit, be used for based on the request of at every turn when the received image signal of predetermined quantity is stored in this write buffer, submitting to that writes with in the request of reading of each official hour submission, control this write buffer, this sense buffer, this writes scalar/vector and this reads scalar/vector.First control writes request based on this, by data bus control first picture signal is sent to this first memory and stores this first picture signal therein from this write buffer, second control is read request based on this, by data bus control this first picture signal is sent to this sense buffer and stores this first picture signal therein from this first memory, this control module is given in these two controls any with a right of priority greater than another one.
According to the present invention, the pixel count of first picture signal is converted, and the result is, has obtained to have the 3rd picture signal of pixel data, and this pixel data is corresponding to the pixel data of forming second picture signal.Further, generate the phase information of target location in second picture signal.Then, based on this phase information, use the 3rd picture signal to generate the pixel data of target location in second picture signal.
Equally, use and for example estimate equation, realize the generation of this pixel data.That is to say, generate the coefficient data that uses in the estimation equation corresponding to this phase information.Based on the 3rd picture signal, extract near some projects of the pixel data that is arranged in the second picture signal target location.Thereby, estimate equation based on this, by using some projects of these coefficient datas and pixel data, calculate the pixel data of target location in second picture signal.
When using the coefficient data that obtains by such study processing, wherein should study handle teacher signal of use corresponding to second picture signal, and student signal corresponding to first picture signal, use the pixel data of the pixel data of such estimation equation generation, can have the higher degree of accuracy of pixel data that beguine obtains according to linear interpolation or the like as target location in second picture signal.
According to the present invention, when using this rate conversion device conversion ratio, carry out the transmission of the picture signal from the first memory to the second memory at each official hour.Thereby the cycle that these data transmit does not have deviation, thus can guarantee that the stable data transport tape between first memory and the second memory is logical, thereby improved its service efficiency.Therefore, can increase in each cycle of data transmission, be sent to the line number of the picture signal of second memory from first memory.The pixel data maker can use more multirow, with higher degree of accuracy, generates the pixel data of the target location in second picture signal.
Further, when the picture signal of predetermined quantity is stored in write buffer,,, picture signal is sent to first memory from this write buffer, and writes wherein by this data bus based on the request that writes of each submission.Further, the request of reading based on each official hour is submitted to by this data bus, is sent to sense buffer with picture signal from first memory, and writes wherein.
In this case, write control (first control) and have right of priority based on one that writes request greater than another based on any of reading in the control (second controls) of the request of reading.This makes by performed the writing and read modification and can be performed well of identical data bus, thereby can read this picture signal based on the input of the request of reading at each official hour, and does not rely on the write time that this writes request.
According to a ninth aspect of the invention, further provide a kind of rate converting device.This rate converting device comprises the rate conversion device, be used for using the part or all of converting objects pixel data string of valid pixel part on the first viewdata signal horizontal direction, generate the suitable pixel data string of valid pixel part on the second image signal level direction, wherein first viewdata signal has by the continuous same pixel data of ratio corresponding to the magnification ratio of pixel count, and is used for further obtaining an amended pixel data string by revising this suitable pixel data string.This device comprises that also a displacement triggers maker, and the displacement that is used for generating corresponding to the change position of pixel data in this amended pixel data string that obtains at this rate conversion device triggers.This device comprises that further a tap sets up part, this part has a shift register of being made up of the register identical with the quantity of the tap that will set up in the horizontal direction, be used to use and trigger the displacement triggering that maker generated by this displacement, the pixel data of the change position of the amended pixel data string that will be obtained by this rate conversion device is put into shift register, and is used to set up the tap corresponding to the predetermined quantity in the horizontal direction of each location of pixels of the valid pixel part of the horizontal direction of this second picture signal.Consistent in order to make this tap set up the centre tapped change of tap of the predetermined quantity on the horizontal direction that part set up with the arrangement of the suitable pixel data string that is generated by this rate conversion device, be to obtain by pixel data string after the modification of this rate conversion device acquisition by the change position of revising the pixel data in the suitable pixel data string.
According to the tenth aspect of the invention, further provide a kind of rate conversion method.This rate conversion method comprises: the rate conversion step, use on the first image signal level direction at least a portion converting objects pixel data string in the valid pixel part, generate the suitable pixel data string of valid pixel part on the second image signal level direction, wherein first viewdata signal has by the continuous same pixel data of ratio corresponding to the magnification ratio of pixel count, and revises this suitable pixel data string so that obtain an amended pixel data string.This method also comprises: displacement triggers and generates step, is used for generating the displacement triggering corresponding to the change position of the pixel data in this modification back pixel data string that obtains in this rate conversion step.This method further comprises a tap establishment step, use is triggered by this displacement and generates the displacement triggering that is generated in the step, the pixel data of the change position of the amended pixel data string that will obtain in this rate conversion step is put into the shift register of being made up of the identical register of the quantity of the tap that will set up with horizontal direction, and sets up the tap corresponding to the predetermined quantity in the horizontal direction of each location of pixels of the valid pixel part of the horizontal direction of this second picture signal.Consistent with the arrangement of the suitable pixel data string that is generated by this rate conversion step for the centre tapped change of the tap that makes the predetermined quantity on the horizontal direction that this tap establishment step set up, the pixel data string is that the change position of the pixel data by revising suitable pixel data string obtains after the modification that obtains in this rate conversion step.
Program related to the present invention makes computing machine can carry out above-mentioned rate conversion method.
The said procedure that related to recording medium recording of the present invention.
According to the present invention, the suitable pixel data string of valid pixel on the horizontal direction of second picture signal part is that the part or all of converting objects pixel data of the valid pixel part on the horizontal direction of first picture signal is concatenated.In this case, the same pixel data by making converting objects pixel data string keeps continuously with the ratio corresponding to the magnification ratio of pixel count, to increase pixel quantity.
In this way in fact the suitable pixel data string of Sheng Chenging does not submit to shift register, but can submit to shift register by the amended pixel data string of revising this suitable pixel data string acquisition.Should trigger in the displacement of the change position of the pixel data in revising back pixel data string when further, submitting to one in this shift register.
This shift register be by with horizontal direction on the register of the number of taps equal number that will set up constitute.Displacement triggers the pixel data of the change position that will revise back pixel data string and puts into this shift register one by one.The tap of the predetermined quantity on this horizontal direction that makes can obtain by the shift register corresponding to each location of pixels partly of the valid pixel in second picture signal.
In this case, consistent with the arrangement of suitable pixel data string for making centre tapped change, the change position of the pixel data by revising suitable pixel data string obtains amended pixel data string.The result, centre tapped change is consistent with the arrangement of this suitable pixel data string, thereby the tap of the predetermined quantity on the horizontal direction that the pixel data that obtains picture signal (first picture signal) before the rate conversion is arranged, and do not depend on the magnification ratio of pixel count.
When an output terminal at shift register provides " no " individual register, and an input end at it provides about being used to export " ni " individual register of this centre tapped register, regards the result who changes (no+ni) individual pixel data at first continuously as revising back pixel data string.Then, (no+ni) the individual project that changes continuously at first with pixel data is placed in the shift register of every row.Thus, be imported into this shift register from the pixel data string of picture signal that will be after rate conversion, the output start delay of the tap of predetermined quantity can be fixed on the individual clock time of every row (no+ni) and not depend on the magnification ratio of this pixel count on the register output horizontal direction given from this.
According to an eleventh aspect of the invention, further provide an image signal processing apparatus, be used for converting first picture signal to second picture signal by some item designs of pixel data by some item designs of pixel data.This device comprises: the rate conversion device, with the phase information maker, wherein this rate conversion device is used to obtain to have the 3rd picture signal of pixel data, this pixel data is corresponding to the pixel data based on this second picture signal of composition of this first picture signal, and this phase information maker is used for generating the phase information in the target location of this second picture signal of the location of pixels that is relevant to this first picture signal.This device also comprises a pixel data maker, is used for using the 3rd picture signal that is obtained by this rate conversion device based on the phase information by this phase information maker generation, is created on the pixel data of the target location in this second picture signal.
This rate conversion device comprises a rate conversion unit, be used for using the part or all of converting objects pixel data string of valid pixel part on the first viewdata signal horizontal direction, generate in the 3rd picture signal suitable pixel data string of valid pixel part on the horizontal direction, wherein first viewdata signal has by the continuous same pixel data of ratio corresponding to the magnification ratio of pixel count, and is used for further obtaining an amended pixel data string by revising this suitable pixel data string.This converter comprises that also a displacement triggers generation unit, is used for generating the displacement triggering corresponding to the change position of the pixel data in this modification back pixel data string that obtains in this rate conversion unit.This rate conversion device comprises that further a tap sets up part, it has a shift register of being made up of the register identical with the quantity of the tap that will set up on the horizontal direction, be used to use and trigger the displacement triggering that maker generated by this displacement, the pixel data of the change position of the amended pixel data string that will be obtained by this rate conversion device is inserted shift register, and is used to set up the tap corresponding to the predetermined quantity in the horizontal direction of each location of pixels of the valid pixel part of the horizontal direction of the 3rd picture signal.
Consistent with the arrangement of the suitable pixel data string that is generated by this rate conversion unit in order to make this tap set up the centre tapped change of tap of the predetermined quantity on the horizontal direction of setting up the unit, the amended pixel data string that is obtained by the rate conversion unit is to obtain by the change position of revising the pixel data in the suitable pixel data string.
According to the present invention,, obtain having the 3rd picture signal corresponding to the pixel data of the pixel data that constitutes second picture signal by changing the pixel count of first picture signal.
In this case, the suitable pixel data string of the valid pixel on the horizontal direction in the 3rd picture signal part is that the converting objects pixel data string of the part or all of valid pixel part on the horizontal direction of first picture signal obtains.Same pixel data by making converting objects pixel data string keep continuously with the ratio corresponding to the magnification ratio of pixel count, to increase pixel count.
In fact the suitable pixel data string of Sheng Chenging does not submit to shift register by this way, but can submit to shift register by the amended pixel data string of revising this suitable pixel data string acquisition.Further, submitting to displacement corresponding to the change position of revising the pixel data in the pixel data string of back of this shift register triggers.
This shift register is made up of the register identical with the number of taps that will set up in the horizontal direction.Displacement triggers the change position of amended pixel data string is inserted shift register one by one.The tap of the predetermined quantity on this horizontal direction that makes can obtain by the shift register corresponding to each pixel partly of the valid pixel in the 3rd view data.
In this case, consistent with the arrangement of suitable pixel data string for making centre tapped change, the change position by the pixel data by revising suitable pixel data string obtains revising back pixel data string.The result, centre tapped change is consistent with the arrangement of this suitable pixel data string, thereby the tap of the predetermined quantity on the horizontal direction that the pixel data that obtains picture signal (first picture signal) before the rate conversion is arranged, and do not depend on the magnification ratio of pixel quantity.
When the output terminal at shift register provides " no " individual register, and provide when being used to export " ni " individual register of a described centre tapped register at its input end, regard the result who changes (no+ni) individual pixel data at first continuously as revising back pixel data string.Then, (no+ni) the individual project that changes continuously at first with pixel data is placed in the shift register of every row.Thus, be imported into this shift register from the pixel data string of picture signal that will be after rate conversion, the output start delay of the tap of predetermined quantity can be fixed on (no+ni) individual clock time of every row and not depend on the magnification ratio of this pixel count on the register output horizontal direction given from this.
Generate the phase information of target location in second picture signal relevant with the location of pixels of first picture signal.Based on this phase information, use above-mentioned the 3rd picture signal, generate the pixel data of the target location of second picture signal.
Equally, use and for example estimate equation, realize the generation of this pixel data.That is to say, generate the coefficient data that uses in the estimation equation corresponding to this phase information.Based on the 3rd picture signal, extract near some projects of the pixel data that is arranged in the second picture signal target location.Thereby, estimate equation based on this, by some projects of coefficient of performance data and pixel data, calculate the pixel data of target location in second picture signal.
When using the coefficient data that obtains by such study processing, wherein should study handle teacher signal of use corresponding to second picture signal, and student signal corresponding to first picture signal, the pixel data that uses such estimation equation to generate, as the pixel data of target location in second picture signal, can have the higher degree of accuracy of pixel data that beguine obtains according to linear interpolation or the like.
Thereby, before rate conversion, the tap of the predetermined quantity in the horizontal direction that obtains corresponding to each location of pixels of the valid pixel of the 3rd picture signal part obtains in the arrangement of the pixel data of this picture signal (in first picture signal), and does not depend on the magnification ratio of this pixel count.If even the magnification ratio of pixel count changes, the corresponding relation on the horizontal direction between the tap of predetermined quantity and this phase information can not damage yet, so can obtain the pixel data of target location in second picture signal admirably.
As mentioned above, be imported into this shift register from the pixel data string of picture signal that will be after rate conversion, the output start delay of the tap of predetermined quantity to be being fixed on the individual clock time of every row (no+ni) on the register given from this output horizontal direction, and do not rely on the magnification ratio of pixel quantity.Thereby, there is no need to provide any variable delay circuit that can change time delay that depends on the magnification ratio of pixel quantity, be used for the tap and for example adjusting of the time between the phase information of predetermined quantity in the horizontal direction.
The latter end of this instructions particularly points out and has directly required theme of the present invention.Yet, read the remainder of instructions in conjunction with the drawings, the wherein similar similar parts of Reference numeral indication, those skilled in the art can understand structure of the present invention and method of operating best, and its more advantage and purpose.
Description of drawings
Fig. 1 is a block diagram, shows the configuration according to an embodiment of image signal processing apparatus of the present invention;
Fig. 2 A shows the line number of 480i signal and the diagrammatic sketch of Horizontal number of pixels;
Fig. 2 B shows the line number of 1080i signal and the diagrammatic sketch of Horizontal number of pixels;
Fig. 3 shows the block diagram of the configuration of rate conversion circuit;
Fig. 4 is used to illustrate the diagrammatic sketch of rate conversion;
Fig. 5 shows at each official hour when reading the converting objects row from frame memory, the corresponding diagrammatic sketch between the row in the single vertical effective period of output image signal and the converting objects row of received image signal;
Fig. 6 A, 6B show at each official hour when reading the converting objects row from frame memory, read the diagrammatic sketch of the contact between received image signal and the output image signal;
Fig. 7 shows when synchronously reading the converting objects row from frame memory with the row of output image signal, the corresponding diagrammatic sketch between the row in the single vertical effective period of output image signal and the converting objects row of received image signal;
Fig. 8 A, 8B show when synchronously reading the converting objects row from frame memory with the row of output image signal, read the diagrammatic sketch of the contact between received image signal and the output image signal;
Fig. 9 shows the example of luminance signal rate conversion, promptly, from the rate conversion object unit AT of level 720 pixels and vertical 240 pixels of brightness signal Y a, obtain level 1920 pixels of brightness signal Y c and the valid pixel part of vertical 480 pixels, the diagrammatic sketch of the example of this situation;
Figure 10 shows the example of the rate conversion of colour difference signal, in other words, rate conversion object unit AT from level 360 pixels and vertical 240 pixels of colour difference signal Ua (Va), obtain level 1920 pixels of colour difference signal Uc (Vc) and the valid pixel part of vertical 480 pixels, the diagrammatic sketch of the example of this situation;
Figure 11 A-F is the time diagram of luminance signal amount of pixels conversion in the horizontal direction;
Figure 12 A-G is the time diagram of colour difference signal amount of pixels conversion in the horizontal direction;
Figure 13 A-F is the time diagram of the line number conversion of vertical direction;
Figure 14 A shows and is used for by the luminance signal of rate conversion circuit in acquisition, the diagrammatic sketch of the example of a tap region of extraction class tap and prediction tapped;
Figure 14 B shows and is used for by the colour difference signal of rate conversion circuit in acquisition, the diagrammatic sketch of the example of a tap region of extraction class tap and prediction tapped;
Figure 15 A shows and is used for by the luminance signal of rate conversion circuit in acquisition, the diagrammatic sketch of the example of a tap region of extraction class tap and prediction tapped;
Figure 15 B shows and is used for by the colour difference signal of rate conversion circuit in acquisition, the diagrammatic sketch of the example of a tap region of extraction class tap and prediction tapped;
Figure 16 A-C shows the diagrammatic sketch of an operation model, the theoretical value of the memory capacity that the SRAM that this model is used for obtaining having a ring structure at the rate conversion device should have for each signal;
Figure 17 shows the block diagram that the configuration of circuit is set up in the Y tap;
Figure 18 A-E shows the diagrammatic sketch of operation (with the fixed integer amount of pixels conversion doubly) example of tap foundation;
Figure 19 A-F shows the diagrammatic sketch of operation (with the amount of pixels conversion of any zoom ratio) example of tap foundation;
Figure 20 A-C is used for illustrating the change of shift register state of operational instances of Figure 19 and the diagrammatic sketch of centre tapped change;
Figure 21 A-C is used to illustrate under the register quantity that constitutes shift register has increased by one situation the change of shift register state and the diagrammatic sketch of centre tapped change;
Figure 22 A-G shows providing and reads in advance to trigger, and changes the diagrammatic sketch that the example of operation (with the amount of pixels conversion of zoom ratio arbitrarily) is set up in tap under the centre tapped situation to allow arrangement according to intensity data among the brightness signal Y c of conversion back;
Figure 23 A-C shows in the operational instances of Figure 22, the change of shift register state and the diagrammatic sketch of centre tapped change;
Figure 24 A-G shows the intensity data of predetermined item is being put into shift register, handles the diagrammatic sketch that the example of operation (with the amount of pixels conversion of zoom ratio arbitrarily) is set up in the tap have under the situation of ratio of output image signal Sc that the output start delay is provided with constant;
Figure 25 shows the block diagram of configuration of the sdram controller of component ratio change-over circuit;
Figure 26 shows the block diagram of the configuration of the read/write controller that constitutes sdram controller;
Figure 27 A-J is the time diagram that is used to illustrate the operation of Writing/Reading controller;
Figure 28 shows the process flow diagram (1/2) of the processing procedure of the operation of using software to finish the Writing/Reading controller;
Figure 29 shows the process flow diagram (2/2) of the processing procedure of the operation of using software to finish the Writing/Reading controller;
Figure 30 A, 30B show the diagrammatic sketch of an example of the data transmission state of the time of received image signal Sa and SDRAM bus;
Figure 31 shows the diagrammatic sketch of example of the generation method of coefficient seed data;
Figure 32 shows the diagrammatic sketch of the relation between the location of pixels of the location of pixels of 525i signal (SD signal) and 1050i signal (HD signal);
Figure 33 is the diagrammatic sketch that is used to illustrate in eight steps of vertical direction phase-shifts;
Figure 34 is used to illustrate the diagrammatic sketch of eight steps of phase-shifts in the horizontal direction;
Figure 35 shows the diagrammatic sketch of the phase relation between SD signal (525i signal) and the HD signal (1050i signal);
Figure 36 shows the diagrammatic sketch of example of the generation method of coefficient seed data;
Figure 37 shows the block diagram of the configuration of coefficient seed data generating apparatus;
Figure 38 shows the block diagram that uses software to finish the configuration of coefficient seed data generating apparatus;
Figure 39 shows the process flow diagram of the process of picture signal processing;
Figure 40 shows the process flow diagram that the coefficient seed data generates the process of handling;
Figure 41 A, 41B show luminance signal and the colour difference signal that is used in the acquisition of rate conversion circuit, the diagrammatic sketch of the example of the tap region of extraction class tap and prediction tapped; And
Figure 42 A, 42B show luminance signal and the colour difference signal that is used in the acquisition of rate conversion circuit, the diagrammatic sketch of the example of the tap region of extraction class tap and prediction tapped.
Embodiment
Hereinafter, will describe the preferred embodiments of the present invention with reference to the accompanying drawings.Fig. 1 shows the configuration according to an embodiment of image signal processing apparatus 100 of the present invention.This image signal processing apparatus 100 converts received image signal Sa to output image signal Sb.Though for the convenience of explaining, describing below is to be that 480i signal and picture signal Sb carry out under the situation of 1080i signal at supposition picture signal Sa, the present invention is not limited to this example.The 480i signal is an interlacing type image signal, and wherein the quantity of scan line is 525, and the quantity of active line is 480, the valid pixel number is laterally * vertically=720 * 480, and sample frequency is 13.5MHz (seeing Fig. 2 A).The 1080i signal is the interlacing type image signal, and wherein the quantity of scan line is 1125, and number of active lines is 1080, the valid pixel number is laterally * vertically=1920 * 780, and sample frequency is 74.25MHz (seeing Fig. 2 B).
Image signal processing apparatus 100 comprises a microcomputer, and it comprises system controller 101, is used for the operation of total system, and remote control signal receiving circuit 102, is used for the receiving remote control signal.This remote control signal receiving circuit 102 is connected to system controller 101, and receiving remote control signal RM, this remote control signal RM remote control signal transmitter 103 is exported corresponding to user's operation, is used for the operation signal corresponding to this signal RM is offered system controller 101.
Further, image signal processing apparatus 100 comprises: image signal processing unit 106, and outlet terminal 107, wherein, image signal processing unit 106 generates picture signal Sb based on the picture signal Sc that obtains by rate conversion circuit 105, and output image signal Sb, and outlet terminal 107 is used to export the picture signal that obtains by this image signal processing unit 106.
Below image signal processing apparatus shown in Figure 1 100 will be described.As the picture signal Sa of 480i signal, be provided for entry terminal 104 and this picture signal Sa is provided for rate conversion circuit 105.The horizontal pixel of this rate conversion circuit 105 converted image signal Sa and the quantity of vertical pixel are to generate the picture signal Sc as the 1080i signal.
According to present embodiment, the user can select normal mode and amplification mode by remote control signal being penetrated the operation of machine 103.Under normal mode, all valid pixel parts of picture signal Sa all are the objects of rate conversion, to generate picture signal Sc.Under the situation of amplification mode, the object that is used to change in the valid pixel of the picture signal Sa part changes corresponding to the magnification ratio of user's defined, so that generate the picture signal Sc corresponding to the magnification ratio of this image.In this case, along with the magnification ratio growth of image, the object that is used to change in the valid pixel part of picture signal Sa has narrowed down.
The picture signal Sc that is obtained by rate conversion circuit 105 is submitted to image signal processing unit 106.This image signal processing unit 106 generates picture signal Sb based on this picture signal Sc.Picture signal Sb is transfused to outlet terminal 107.Above-mentioned rate conversion circuit 105 is repeatedly read predetermined pixel, and by repeatedly reading predetermined row, degree of switching and vertical pixel.Corresponding in the project of the pixel data of composing images signal Sc each, this image signal processing unit 106 is estimated equation according to one, calculate each pixel data of composing images signal Sb, image signal processing unit 106 has used the coefficient data corresponding to this pixel data phase information in calculating, and the some projects that are positioned near the pixel data this pixel data.
The user can send out the operation of phase machine 103 to remote control signal by him or she, regulates image resolution ratio and the noise removing level of picture signal Sb.In image signal processing unit 106, as mentioned above, estimate equation, each pixel data of calculating composing images signal Sb according to one.Estimate the coefficient data of equation as this, use the data that generate the equation generation according to, these data comprise the parameter g of the parameter f and the regulation noise removing level of regulation resolution.The user is by adjusted parameter f, g to remote control signal transmitter 103.Correspondingly, image resolution ratio and the noise removing level about picture signal Sb that is generated by image signal processing unit 106 also becomes corresponding to parameter f, g after regulating.
Next, will describe rate conversion circuit 105 in detail.Fig. 3 shows the configuration of rate conversion circuit 105.
This rate conversion circuit 105 has sdram controller 202, is used for control writing and reading this frame buffer (SDRAM) 201.This sdram controller 202 is connected to this frame memory 201 by SDRAM bus (data bus) 203 or the like.
Here, the some clock signal formed by blue difference signal Ua and red color difference signal Va of colour difference signal Ua/Va.That is, the sampling ratio of brightness signal Y a is 13.5MHz, and the sampling ratio of colour difference signal Ua, Va is 13.5/2MHz.Impact damper 204Y, 204C are made of the static RAM (SRAM) (SRAM) that is used for two row respectively.Use the reason of two SRAMs that go as follows.
That is, write a side buffer and need receive received image signal Sa continuously.If SDRAM bus 203 is by the data occupancy under the read operation, all the elements of impact damper just can not be sent to frame memory 201.Thereby, if impact damper 204Y, 204C are made of the SRAM of single file, will conflict by time of origin.For this reason, according to present embodiment, 204Y, 204C are made up of the SRAM of two row, and if SDRAM bus 203 is read out the data occupancy under operating, the operation that the content of impact damper is sent to frame memory 201 can be in waiting status, conflicts to avoid time of origin.
Synchronous with the input clock Cki of 13.5MHz, brightness signal Y a and colour difference signal Ua/Va are written among impact damper 204Y, the 204C one by one.In this case, only write the valid pixel part, so that every row (720 pixel) awaits writing in 720 clock period according to input clock Cki.
The mode of dividing with the time, the brightness signal Y a and the colour difference signal Ua/Va that synchronously will write every row of these impact dampers 204Y, 204C with the memory clock CKm of 108MHz read, and it is write frame memory 201.In this case, 8 data are converted into 32 data, and are transmitted.That is to say, handle four pixels concurrently, and, in the cycle of 180 clocks, every row (720 pixel) is sent to frame memory 201 from impact damper 204Y, 204C, and writes wherein according to memory clock CKm.
Further, provide impact damper 205Y, 205C as sense buffer for sdram controller 202.The picture signal that the interim storage of impact damper 205Y, 205C is read from frame memory 201, i.e. luminance signal and colour difference signal.These impact dampers 205Y, 205C are connected to SDRAM bus 203.
The brightness signal Y a and the colour difference signal Ua/Va that write every row of frame memory 201 are synchronously read by the memory clock CKm with 108MHz, and write buffer 205Y, 205C.In this case, handle four pixels concurrently, so that, in 180 clock period, every row (720 pixel) is sent to impact damper 205Y, 205C from frame memory 201, and writes wherein according to memory clock CKm.
In this case, mode with the time division, by SDRAM bus 203, transmit the brightness signal Y a of every row of the SRAM that will write each 10 row that constitutes impact damper 205Y and the colour difference signal Ua/Va of every row that will write the SRAM of each 2 row that constitutes impact damper 205C from frame memory 201.
Further, sdram controller 202 comprises a control module 206.The request that writes WRQ corresponding to the incoming timing signal generator that will describe from below (input TG) 207 submissions, this control module 206 generate to be submitted to impact damper 204Y, 204C read address RADi, and one to be submitted to frame memory 201 write address WADm.Further, the request of reading RRQ corresponding to the storer timing generator that will describe from below (storer TG) 211 submissions, control module 206 generate to be submitted to frame memory 201 read address RADm, and to be submitted to impact damper 205Y, 205C write address WADo.
Vertical counter 209 usefulness vertical synchronizing signal VDi are reset to count value " 0 ", and when submitting horizontal-drive signal HDi to, it increases count value, and this count value is submitted to horizontal counter 208 at every turn.
Horizontal counter 208 usefulness horizontal-drive signal HDi are reset to count value " 0 ", and when submitting input clock Cki to, it increases count value at every turn.Based on count value from the count value of vertical counter 209 and it self, corresponding to the valid pixel part on part of the valid pixel on the vertical direction and the horizontal direction, horizontal counter 208 synchronously generates at every row and input clock Cki and writes address WADi, and it is submitted to impact damper 204Y, 204C in the sdram controller 202.
Further, at horizontal counter 208 corresponding to the effective pixel parts on the vertical direction, for the valid pixel on every capable horizontal direction partly generate one write address WADi after, horizontal counter 208 synchronously generates one with horizontal-drive signal HDi and writes request WRQ, and this request is submitted to control module 206 in the sdram controller 202.
Vertical counter 213 uses vertical reset signal VRS count value to be reset to " 0 ", and when having submitted to one to read request RRQ, vertical counter 213 increases this count value, and the count value after will increasing is submitted to request counter 212.When count value was in 0-N-1, request counter 212 was based on the count value from vertical counter 213, generated each and read request RRQ, and it is submitted to control module 206 in the sdram controller 202, then it was submitted to vertical counter 213.
Although in this case, when the count value from vertical counter 213 became " 0 ", request counter 212 generates read request RRQ, afterwards, when counting down to " n " individual memory clock CKm, generated and read request RRQ.
When execution is used for when the part or all of valid pixel part of the received image signal Sa shown in Fig. 4 obtains the rate conversion of valid pixel part of output image signal Sc, be a unit (rate conversion object unit AT) of the ah pixel (ah≤720) on av capable (av≤240) and the horizontal direction on the vertical direction, aforesaid N becomes av.Simultaneously, because Fig. 4 shows individual domain, the pixel quantity on the vertical direction of the valid pixel of each received image signal Sa and output image signal Sc part (quantity of row) is half of pixel quantity (quantity of row) shown in Figure 2.
When request RRQ is read in one of each generation, read the brightness signal Y a of 10 row and the colour difference signal Ua/Va of 2 row from frame memory 201, and these signals are submitted to impact damper 205Y, 205C.In this case, when image signal processing unit 106 is obtained the intensity data of target location of brightness signal Y b, use the brightness signal Y a of 10 row that will be described below to obtain prediction tapped and class tap.Similarly, will describe as the back, when image signal processing unit 106 was obtained the chromatism data of target location of colour difference signal Ub/Vb, the colour difference signal Ua/Va that use 2 row were to obtain prediction tapped and class tap.
When carrying out rate conversion as shown in Figure 4,10 row brightness signal Y a and 2 circumstances in which people get things ready for a trip difference signal Ua/Va corresponding to the first capable row of the av of the rate conversion object unit AT of received image signal Sa are read from frame memory 201, when being " 0 " corresponding to count value when vertical counter 213, read request RRQ, and brightness signal Y a and colour difference signal Ua/Va are submitted to impact damper 205Y, 205C for one that generates.The request of reading PPQ for the correspondence generation, when the count value of vertical counter 213 is 1-N-1, corresponding to the brightness signal Y a of 10 capable row of the second capable row-N of the av of the rate conversion object unit AT of this Sa of this received image signal and the colour difference signal Ua/Va of two row, read and be submitted to impact damper 205Y, 205C from this frame memory 201.
The cycle of the request of the reading RRQ that generates in request counter 212 is the time that obtains by with the single vertical effective period of dividing this output image signal Sc as the line number of the object of the rate conversion that is used for this received image signal Sa fifty-fifty.Promptly, suppose that the cycle is " t ", the dot frequency of output image signal Sc is " fo ", the line number that is used for the object of received image signal Sa rate conversion is " mi ", the line number of the single vertical effective period of output image signal Sc is " mo ", and the pixel quantity of the every row of output image signal Sc is " no ", has one to concern t=mo/mi/fo * no here.
As mentioned above, when counting down to " n " individual memory clock CKm, request counter 212 generates reads request RRQ.This " n " obtains by divide the above-mentioned cycle " t " with the cycle of memory clock CKm.That is, because memory clock CKm is 1/108MHz, it becomes n=mo/mi * 108MHz/fo * no.
For the ease of understanding, Fig. 5 shows, when each official hour is read the capable object that is used to change from frame memory 201, the quantity " mi " of supposing the capable object that received image signal Sa is used to change is 5, and the quantity " mo " of the row in the single vertical effective period of output image signal Sc is under 12 the situation, correspondence between the capable object that row in the single vertical effective period of output image signal Sc and received image signal Sa are used to change is with reference to Fig. 5, the row of solid line " a " expression output image signal Sc, and the capable object that dot-and-dash line " b " expression received image signal Sa is used to change.
Fig. 6 A shows each row object that will be used to change from the received image signal Sa that frame memory 201 is read.Fig. 6 B shows each row in the single vertical effective period of output image signal Sc.In this case, because the data transfer cycles from frame memory 201 to impact damper 205Y, 205C does not have deviation, can guarantee that the stable data travelling belt is logical.
Different with present embodiment, Fig. 7 shows with the row of output image signal Sc and synchronously reads under the situation of the capable object that is used to change the correspondence between the capable object that the row of the single vertical effective period of output image signal Sc and received image signal Sa are used to change from frame memory 201.In Fig. 7, the row of solid line " a " expression output image signal Sc, dot-and-dash line " b " expression is used for the capable object of the conversion of received image signal Sa.
Fig. 8 A shows a poison row object of the conversion that is used for received image signal Sa that will read from frame memory 201.Fig. 8 B shows every row of the single vertical effective period of output image signal Sc.In this case, because the fluctuation of the data transfer cycle from frame memory 201 to impact damper 205Y, 205C comes the logical service efficiency of specified data transport tape by its (the transmission cycle) short element.
Corresponding to reading request RRQ, brightness signal Y a and colour difference signal Ua/Va are sent to impact damper 205Y, 205C from frame memory 201, and be stored in wherein, after this, the request counter 212 of storer TG211 generate to submit to impact damper 205Y, 205C read address RADo, and to submit to rate conversion unit 215Y, 215C write address WADr, rate conversion unit 215Y, 215C are as the second memory that will be described later.
Further, rate conversion circuit 105 has rate conversion unit 215Y, 215C.Above-mentioned impact damper 205Y is made of the SRAM of 10 row, and therewith correspondingly, rate conversion unit 215Y is made of the 10 dual-port line storages (SRAM) of going.Similarly, above-mentioned impact damper 205C is made of 2 SRAM that go, and therewith correspondingly, rate conversion unit 215C is made of the dual-port line storages (SRAM) of 2 row.The SRAM of each system has a ring structure, and it has the capacity greater than the memory capacity of prediction, so that in rate conversion was handled, write operation can not surpass read operation.
As mentioned above, read address RADo and be submitted to impact damper 205Y, 205C, write address WADr and be submitted to rate conversion unit 215Y, 215C from storer TG211.Therefore, read request RRQ corresponding to each, the colour difference signal Ua/Va of the brightness signal Y a of 10 row and 2 row, mode with the time division, after being sent to impact damper 205Y, 205C from frame memory 201, further be transferred to rate conversion unit 215Y, 215C concurrently, and be stored in wherein.
Further, rate conversion circuit 105 has output timing generator (output TG) 217.This output TG217 comprises scalar/vector 218 and vertical counter 219.Be submitted to scalar/vector 218 with the output clock Cko of the synchronous 74.25MHz of output image signal Sc.Scalar/vector 218 generates and the synchronous horizontal-drive signal HDo of output image signal Sc by output clock Cko is counted.Horizontal-drive signal HDo is submitted to vertical counter 219.
Further, be submitted to vertical counter 219 with the synchronous vertical synchronizing signal VDo of output image signal Sc.Vertical counter 219 usefulness vertical synchronizing signal VDo reset to count value " 0 ", and when submitting a horizontal-drive signal HDo to, increase this count value.Then, vertical counter 219 is based on this count value, valid pixel initial location of pixels partly in output image signal Sc vertical direction generates above-mentioned vertical reset signal VRS, and vertical reset signal VRS is submitted to the vertical counter 213 of storer TG211.
The count value of vertical counter 219 is submitted to scalar/vector 218.This scalar/vector 218 generates and reads address RADr, and it is submitted to rate conversion unit 215Y, 215C corresponding to an effective unit of the horizontal direction of the every row of valid pixel part of output image signal Sc vertical direction.
In this case, scalar/vector 218 generates a reference address RADr0 at the valid pixel initial location of pixels (seeing the some P among Fig. 4) partly of horizontal direction and the vertical direction of output image signal Sc.This reference address RADr0 represents that this reference position is the reference position of the rate conversion object unit AT of the received image signal Sa in rate conversion unit 215Y, 215C corresponding to the record position of the pixel data of reference position (seeing the some Q of Fig. 4).
Because the phase information of the initial location of pixels of valid pixel part is 0 on the horizontal direction, scalar/vector 218 will be exported anti-several Mh that clock Cko is added to the horizontal extension ratio of each location of pixels that will submit to.If the value of adding up is littler than 4096, this value of adding up is counted as the phase information h of the horizontal direction of location of pixels.On the other hand, if the interpolation value is little unlike 4096, carry taking place, regards phase information h on the horizontal direction of this location of pixels as so that will deduct 4096 values that obtain by the value of adding up from this.Simultaneously, this phase information " h " is, for example, by the time numeral below the zero point value that rounds up and obtain.This for the phase information on the vertical direction " v " too.
If this value of adding up is littler than 4096, and carry does not take place, as corresponding to this location of pixels read address RADr, scalar/vector 218 outputs and a value that just in front location of pixels is identical are as location of pixels.On the other hand, if carry takes place, as reading address RADr, advance from front the address of the location of pixels just address in 1 step of its output corresponding to this location of pixels.
As mentioned above, when additive value littler and when not having carry than 4096, output and in front the identical value of location of pixels just as location of pixels, as reading address RADr corresponding to of this location of pixels, and in this position, from rate conversion unit 215Y, 215C reads and in front the identical pixel data of location of pixels just, correspondingly, can increase the quantity of pixel on the horizontal direction.
Here, can be according to an equation Mh=(pixel quantity on the horizontal direction of the rate conversion object unit AT of received image signal Sa)/(pixel quantity on the valid pixel part of horizontal direction of output image signal Sc) * generalized constant, anti-several Mh of the ratio that is expanded.According to present embodiment, generalized constant is 4096.This is that pixel on the received image signal Sa horizontal direction is by the reason of 4096 five equilibriums, so that determine the phase place of horizontal direction of each pixel of output image signal.For example, if carried out rate conversion as shown in Figure 4, just it becomes Mh=ah/1920 * 4096.
Because the phase information of the initial location of pixels of the valid pixel of vertical direction part is 0, scalar/vector 218 adds at every row and anti-several Mv of extends perpendicular ratio has wherein generated horizontal-drive signal HDo at each row.When the value of adding up than 4096 hours, this additive value is counted as the phase information on the vertical direction " v " in this row.On the other hand, if this value of adding up is little unlike 4096, carry taking place, and will regard phase information " v " on the vertical direction of this row as by deduct 4096 values that obtain from this additive value.
When this value of adding up littler and when carry not taking place than 4096, as reading address RADr, these scalar/vector 218 outputs and in front the identical value of row just in time corresponding to this row.On the other hand, if carry has taken place, as corresponding to this row read address RADr, a value behind its output modifications is to read out in the pixel data of received image signal Sa next line.
Here, can be according to equation Mv=(pixel quantity on the vertical direction of the rate conversion object unit AT of received image signal Sa)/(pixel quantity on the valid pixel part vertical direction of output image signal Sc) * generalized constant, anti-several Mv of the ratio that is expanded.According to this embodiment, generalized constant is 4096.This is that pixel on the vertical direction of received image signal Sa is by the reason of 4096 five equilibriums, to determine each pixel phase place in vertical direction of output image signal.For example, when the rate conversion carried out as shown in Figure 4, it just becomes Mv=av/540 * 4096.
As mentioned above, when this additive value littler and when not generating carry than 4096, output and in front the identical value of row just in time, as reading address RADr corresponding to this row, and read from rate conversion unit 215Y, 215C at this row, as with in front the identical pixel data of row just in time.Accordingly, can increase pixel quantity on the horizontal direction (quantity of row).
Fig. 9 shows an embodiment from the brightness signal Y a of received image signal Sa to the rate conversion of the brightness signal Y c of output image signal Sc.According to this embodiment, obtain level 1920 pixels of brightness signal Y c and the valid pixel part of vertical 480 pixels from level 720 pixels of brightness signal Y a and the rate conversion object unit AT of vertical 240 pixels.
In this case, the anti-number " Mh " of extensive ratio is Mh=720/1920 * 4096=1536 on the horizontal direction, thus the phase information of each location of pixels on the horizontal direction of brightness signal Y c " phy " from 0 to 1536 to 3072 to 512 (=4608-4096) to 2046 to ... change.Further, the anti-number " Mv " of the extensive ratio on the vertical direction is Mv=240/540 * 4096 ≈ 1820, and the phase information of each location of pixels " pvy " from 0 to 1820 to 3640 to 1364 on the vertical direction of brightness signal Y c (=5460-4096) to 3184 to ... change.
Figure 10 shows the embodiment from the colour difference signal Ua (Va) of received image signal Sa to the rate conversion of the colour difference signal Uc of output image signal Sc.According to this embodiment, obtain level 1920 pixels of colour difference signal Uc (Vc) and the valid pixel part of vertical 480 pixels from level 360 pixels of colour difference signal Ua (Va) and the rate conversion object unit AT of vertical 240 pixels.Simultaneously, as mentioned above, the blue difference signal Ua of received image signal Sa and red difference letter signal Va are the point sequence signals, and the pixel quantity of each is half of brightness signal Y a.Thereby level 360 pixels of colour difference signal Ua (Va) are corresponding to level 720 pixels of above-mentioned luminance signal.
In this case, the anti-number " Mh " of extensive ratio is Mh=360/1920 * 4096=768 on the horizontal direction.Like this phase information " phc " from 0 to 768 to 1536 to 2304 to 3072 to 3840 to 512 of each location of pixels on the horizontal direction of colour difference signal Uc (Vc) (=4608-4096) to 1280 to ... and change.Further, the anti-number " Mv " of the extensive ratio on the vertical direction is Mv=240/540 * 4096 ≈ 1820, and on the vertical direction of colour difference signal Uc (Vc) each location of pixels positional information " pvc " from 0 to 1820 to 3640 to 1364 (=5460-4096) to 3184 to ... and change.
As mentioned above, the blue difference signal Ua of received image signal Sa and red color difference signal Va are the point sequence signals, and in rate conversion unit 215C, this point sequence signal are write in two systems of SRAM each.Yet, when when output, output blue difference signal Uc and red color difference signal Vc are independently arranged at rate conversion unit 215C.In this case, provide a port of reading that is used for blue difference signal Uc to rate conversion unit 215C,, and the port of reading that is used for red color difference signal Vc.Submit the address of blue difference signal Uc and red color difference signal Vc independently to, as will be from scalar/vector 218 output of output TG217 read address RADr.
Figure 11 A-F shows the time diagram that is used to change corresponding to the pixel quantity of the horizontal direction of the luminance signal of the example shown in Fig. 9.Figure 11 A shows the horizontal-drive signal HDi synchronous with brightness signal Y a.Figure 11 B shows the row of brightness signal Y a, numeral 1,2,3 ..., represent first pixel data, second pixel data, the 3rd pixel data ..., it has constituted rate conversion object unit AT.
Figure 11 C shows the request of the reading RRQ from storer TG211 output, and submits to the control module 206 in the sdram controller 202.Figure 11 D shows corresponding to reading request RRQ, and from the brightness signal Y a that frame memory 201 is read, by impact damper 205Y, brightness signal Y a is transfused to rate conversion unit 215Y.
Figure 11 E shows the horizontal-drive signal HDo synchronous with brightness signal Y c.Figure 11 F shows the row that comprises brightness signal Y c, and brightness signal Y c exports from rate conversion unit 215Y.Numeral 1,2,3 ..., represent the pixel data of first pixel data, second pixel data, the 3rd pixel data or the like of brightness signal Y a respectively, they have constituted rate conversion object unit AT.
Figure 12 A-G shows the time diagram corresponding to the conversion of the pixel quantity of the colour difference signal horizontal direction of Figure 10.Figure 12 A shows the horizontal-drive signal HDi synchronous with colour difference signal Ua/Va.Figure 12 B shows a row that comprises colour difference signal Ua/ Va.Numeral 1,2 ..., first pixel data, second pixel data of expression blue difference signal Ua ..., it has constituted rate conversion object unit AT.Numeral 1,2 ... first pixel data, second pixel data of expression red color difference signal Va ..., it has constituted rate conversion object unit AT.
Figure 12 C shows the request of the reading RRQ from storer TG211 output, and it is submitted to the control module 206 of sdram controller 202.Figure 12 D shows colour difference signal Ua/Va, and it is read from frame memory 201 corresponding to reading request RRQ, and by impact damper 205C, is transfused to rate conversion unit 215C.
Figure 12 E shows and blue difference signal Uc and the synchronous horizontal-drive signal HDo of red color difference signal Vc.Figure 12 F shows the delegation that comprises from the blue difference signal Uc of rate conversion unit 215C output.Numeral 1,2,3 ..., expression is corresponding to first pixel data, second pixel data, the 3rd pixel data of blue difference signal Ua ... pixel data, it has constituted rate conversion object unit AT.Figure 12 G shows the delegation that comprises from the red color difference signal Vc of rate conversion unit 215C output.Numeral 1,2,3 ..., expression is corresponding to first pixel data, second pixel data, the 3rd pixel data of red color difference signal Va ... pixel data, it has constituted rate conversion object unit AT.
Figure 13 A-F shows the conversion (conversion of the quantity of pixel) of the line number of relevant picture signal (luminance signal, colour difference signal) vertical direction.Figure 13 A shows the synchronous vertical synchronizing signal VDi with picture signal Sa (brightness signal Y a, colour difference signal Ua/Va).Figure 13 B shows the continuous row of picture signal Sa, numeral 1,2,3 ... first row of expression component ratio converting objects unit AT, second row, the third line or the like.
Figure 13 C shows and reads request RRQ, and it is from storer TG211 output and be submitted to control module 206 sdram controller 202.Figure 13 D shows picture signal Sa, and it is read out from frame memory 201 corresponding to reading request RRQ, and by impact damper 205Y, 205C, is transfused to rate conversion unit 215Y, 215C.
Figure 13 E shows the synchronous vertical synchronizing signal VDo with picture signal Sc (brightness signal Y c, blue difference signal Uc, red color difference signal Vc).Figure 13 F shows from the continuous row of the picture signal Sc of rate conversion unit 215Y, 215C output.Numeral 1,2,3 ... expression is corresponding to first row, second row, the third line of the picture signal Sa of component ratio converting objects unit AT ... those the row.
Get back to Fig. 3, as mentioned above, rate conversion unit 215Y is made up of the SRAMs of 10 row and based on the brightness signal Y c that the parallel output of address RADr 10 is gone that reads that is generated by output TG217.In addition, its also parallel output has 8 luminance signals of going that row postpones.In this case, the SRAM of every row of rate conversion unit 215Y has a ring structure, so that read a little address by the another port from a certain port address of reading by the pixel count with single row only, obtains to have the luminance signal that row postpones.
At last, the brightness signal Y c that from rate conversion unit 215Y, obtain 18 row that walk abreast.When having obtained on the target location of image signal processing unit as described below 106 in brightness signal Y b to constitute the intensity data of output image signal Sb, use the brightness signal Y c of 18 row to extract prediction tapped and class tap.
Figure 14 A shows the example of the tap region of luminance signal, and the 10 row 0-9s represented by white circle represent the not row of row delay, and represent to have the row that row postpones by 8 represented row 10-17 of the circle of band shade.In this case, for example, row 13 is positioned at the center.
Figure 15 A shows another example of the tap region of luminance signal, and the 10 row 0-9s represented by white circle represent the not row of row delay, and represent to have the row that row postpones by 8 represented row 10-17 of the circle of band shade.In this case, for example, row 13 is positioned at the center.
Rate conversion unit 215C is that the SRAM by aforesaid 2 row constitute, and reads address RADr based on what generated by output TG217, and line output is about 2 circumstances in which people get things ready for a trip difference signals of blue difference signal Uc and red color difference signal Vc.Further, it export concurrently have that row postpones, about 2 circumstances in which people get things ready for a trip difference signals of blue difference signal Uc and red color difference signal Vc.In this case, the SRAM of every row of rate conversion unit 215C has a ring structure, so that read a little address by the another port from a certain port address of reading by the pixel count with single row only, obtains to have the luminance signal that row postpones.
At last, the acquisition from rate conversion unit 215C that walks abreast is about the colour difference signals of 4 row of each blue difference signal Uc and red color difference signal Vc.When obtaining to constitute the chromatism data of output image signal Sb on the target location of image signal processing unit as described below 106 in colour difference signal, the colour difference signal that uses 4 row is to extract prediction tapped and class tap.
Figure 14 B shows an example of the tap region of colour difference signal.By represented two row 0,1 expression of the white circle row that postpones of row, and have the row that row postpones by represented two row, 2,3 expressions of the circle of band shade.For example, in this case, row 2 is positioned at the center.
Figure 15 B shows another example of the tap region of colour difference signal.By represented two row 0,1 expression of the white circle row that postpones of row, and have the row that row postpones by represented two row, 2,3 expressions of the circle of band shade.For example, in this case, row 2 is positioned at the center.
As mentioned above, the every capable SRAM that has of rate conversion unit 215Y, 215C has a ring structure.In this case, how much memory capacity every guild of SRAM needs, by guaranteeing with operation model and the actual service conditions shown in the theoretical value simulation drawing 16A-C.
Figure 16 B shows the line of input of rate conversion unit and Figure 16 C shows its output row.Figure 16 A shows corresponding to the transformation that writes the address (dotting) of line of input and corresponding to the transformation of reading the address (representing with solid line) of exporting row.Figure 16 A has shown that the memory capacity of every capable SRAM needs W or more.
Turn back to Fig. 3 once more, rate conversion circuit 105 has tap and sets up circuit 221Y, 221C.When the image signal processing unit 106 that can illustrate when the back obtains constituting the intensity data of output image signal Sb on the target location of brightness signal Y b, tap is set up circuit 221Y and is selected and set up a horizontal tap, this horizontal tap is as prediction tapped and class tap about each 18 brightness signal Y c that go, and this brightness signal Y c obtains by rate conversion unit 215Y.
When the image signal processing unit 106 that can illustrate when the back obtains constituting the chromatism data of output image signal Sb in the target location of blue color difference signal Ub, tap is set up circuit 221C and is selected and set up a horizontal tap, this horizontal tap is as prediction tapped and class tap about each 4 blue difference signal of going, and this blue difference signal obtains by rate conversion unit 215C.
Further, when the image signal processing unit 106 that can illustrate when the back obtains constituting the chromatism data of output image signal Sb in the target location of red color difference signal Vb, tap is set up circuit 221C and is selected and set up a horizontal tap, this horizontal tap is as prediction tapped and class tap about each 4 red color difference signal of going, and this red color difference signal Vc obtains by rate conversion unit 215C.
To describe tap below in detail and set up circuit 221Y.
As shown in figure 17, this tap is set up circuit 221Y and is had 18 shift register 222-1 of brightness signal Y c corresponding to 18 row to 222-8, and this brightness signal Y c obtains by rate conversion unit 215Y.The quantity that constitutes the tap that will set up on quantity and the horizontal direction of register of each shift register is identical.According to present embodiment, set up 5 taps of level.
Consider such situation, wherein corresponding to the valid pixel part of every row, have only the intensity data string of the brightness signal Y c that obtains after process as the above-mentioned rate conversion, promptly its suitable intensity data string is transfused to shift register.Simultaneously, suppose that change displacement corresponding to the intensity data of the intensity data string of brightness signal Y c triggers STR and is submitted to shift register, so that obtain the intensity data of change position of the intensity data string of brightness signal Y c continuously.
At first, below such a case will be described: convert pixel count on the horizontal direction to integer time, for example a twice with rate conversion unit 215Y.In this case, obtain the state shown in Figure 18 A-E.Figure 18 B shows the delegation that comprises the brightness signal Y c after the rate conversion, numeral 1,2,3 ... expression is corresponding to first intensity data, second intensity data, the 3rd intensity data ... intensity data, it has constituted the rate conversion object unit AT of brightness signal Y a before the rate conversion.Figure 18 C shows corresponding to the change point of intensity data and the displacement that generates triggers STR.Figure 18 A shows the arrangement of each project of the intensity data of the brightness signal Y a before the rate conversion, the change position consistency of the intensity data of the intensity data string of itself and brightness signal Y c.
When using tap to set up circuit 221Y to set up 5 taps of level, centre tapped change is shown in Figure 18 E.Simultaneously, Figure 18 D shows the centre tapped change time.
In this case and since centre tapped change corresponding to rate conversion after the arrangement of intensity data string of brightness signal Y c, can be before rate conversion in the arrangement of the intensity data of brightness signal Y a, obtain 5 taps of level.
Meanwhile, will regard the output start delay as from cycle of beginning unit 221Y is set up in brightness signal Y c input tap to time in cycle of the intensity data of 5 taps of level being inserted shift register and exporting 5 taps of first level.Will from cycle of centre tapped intensity data being inserted shift register to regarding above-mentioned intensity data as system delay as the time in the cycle of center tap output.
The deviation of output start delay depends on the conversion magnification ratio of pixel count.Thereby, if use 5 taps of setting up the level of the brightness signal Y c that sets up among the circuit 221Y in tap, the image signal processing unit 106 of a little explanations in evening needs a variable delay circuit, this circuit can depend on the conversion magnification ratio of pixel quantity, and change time delay, come the execution time to regulate with the signal that uses other system.
Next, will describe such a case below, convert the pixel quantity of horizontal direction to a magnification ratio arbitrarily by rate conversion unit 215Y, for example, 7/3 magnification ratio.
In this case, the state shown in Figure 19 A-F appears.Figure 19 B shows the row that comprises the brightness signal Y c after the rate conversion, and numeral 1,2,3 ... expression constitutes first intensity data, second intensity data, the 3rd intensity data corresponding to the rate conversion object unit AT of brightness signal Y a ... intensity data.Figure 19 C shows corresponding to the change point of intensity data and the displacement that takes place triggers STR.Figure 19 A show with the change position consistency of the intensity data of the intensity data string of brightness signal Y c, the arrangement of each project of the intensity data of brightness signal Y a before the rate conversion.
When setting up circuit 221Y with tap and set up 5 taps of level, centre tapped changing shown in Figure 19 E.Meanwhile, Figure 19 D shows centre tapped change.
In this case, generated a unit here, in this unit, the arrangement of the intensity data string of centre tapped change and rate conversion 1 back brightness signal Y c is inconsistent.That is to say, at time t
A, the state of shift register shown in Figure 20 A, and the output intensity data " 4 as center tap.So owing to submit to shift LD to trigger STR at ensuing time X, the change of the state of shift register shown in Figure 20 B, and the output intensity data " 5 as center tap.Further, because at ensuing time t
B, submit to displacement to trigger, the state of shift register is shown in Figure 20 C, and is similar to the state of time X, and the output intensity data " 5 as center tap.
Figure 19 F shows the centre tapped change of expectation, and at time X, what export as center tap is not intensity data " 4, but intensity data " 5.Thereby, in this case, can not be before rate conversion the arrangement of the intensity data of brightness signal Y a, obtain 5 taps of level.
Consider that so the quantity that constitutes the register of shift register only increases by 1, so that obtain 6, and 5 taps of setting up level subsequently by mask register from shift register.In this case, at time t
A, the state of shift register is shown in Figure 21 A, and the output of register 1-5 exports as a tap, so that center tap has intensity data " 4.Owing at ensuing time X, submitted to displacement to trigger STR, the change of the state of shift register is shown in Figure 21 B, and tap of register 2-6 output, so that center tap has intensity data " 4.Further, because ensuing time t
S, do not submit to displacement to trigger, the state of shift register is shown in Figure 21 C, and is similar to the state of time X.Thereby register 1-5 exports a tap, so that center tap has intensity data " 5.
Therefore, after centre tapped change and the rate conversion arrangement of the intensity data string of brightness signal Y c corresponding so that before obtaining rate conversion, 5 taps of the level in the arrangement of the intensity data of brightness signal Y a.Yet, in this case, need a circuit, be used to calculate the position of phase place and designated centers tap.Equally, in this case, the change of output start delay depends on the conversion magnification ratio of pixel quantity.
Next, what consider is the change position of intensity data of revising the intensity data string of brightness signal Y c, and with amended intensity data string input shift register, so that the arrangement of the intensity data string of brightness signal Y c after making centre tapped change corresponding to rate conversion.
In this case, will be submitted to tap from rate conversion unit 215Y and set up unit 221Y by revising the brightness signal Y c ' shown in Figure 22 E that brightness signal Y c (shown in Figure 22 B) obtains.In this case, shown in Figure 22 D, set up the shift register of unit 221Y to tap from rate conversion unit 215Y, submit to a displacement to trigger STR ' rather than displacement triggering STR, this displacement triggers the change position (as Figure 22 C shown in) of STR ' corresponding to the intensity data of the intensity data string of brightness signal Y c '.
Exported centre tapped register corresponding to shift register, provide " no " register, and provide " ni " register at its input end at its output terminal.As mentioned above, when having set up 5 taps of level, the relation here is no=ni=2.Displacement triggers STR ' to have ni displacement of reading in advance to trigger at its head to trigger STR.The timing method of reading to trigger in advance is not limited to the timing method shown in Figure 22 D, if but intensity data " 1, " 2 is inserted shift register, just satisfied its requirement.
When 5 taps of the level of having set up among the circuit 221Y were set up in tap, centre tapped change was shown in Figure 22 G.Figure 22 F shows the centre tapped change time.Figure 22 A shows with the change position consistency of the intensity data of the intensity data string of brightness signal Y c, the arrangement of each project of the intensity data of brightness signal Y a before the rate conversion.
In this case, at time t
AThe state of shift register shown in Figure 23 A, and output is as centre tapped intensity data " 4.Because at ensuing time X, do not submit to displacement to trigger STR, the state of shift register is shown in Figure 23 B, with t
AState similar, and output as centre tapped intensity data " 4.Further, because at ensuing time t
BSubmit to a displacement to trigger STR ', the change of its shift register state is shown in Figure 23 B, and output is as centre tapped intensity data " 5.
Be submitted to tap and set up circuit 221Y by brightness signal Y c ' (shown in Figure 22 E) and displacement being triggered STR ' (shown in Figure 22 D) from rate conversion unit 215Y, centre tapped change corresponding to rate conversion after the arrangement of intensity data string of brightness signal Y c, so that in the arrangement of the intensity data of the brightness signal Y a before rate conversion, obtain 5 taps of level.
Yet the change of output start delay depends on the conversion magnification ratio of pixel quantity.Thereby, when using when setting up 5 taps of level of the brightness signal Y c that circuit 221Y sets up by tap, image signal processing unit 106 needs a variable delay circuit, this variable delay circuit can change time delay according to the conversion magnification ratio of pixel quantity, to use other signal to come the adjusting time, for example, the phase information (phy, pvy) (phc, pvc) that will describe of back.
Thereby, according to this embodiment, will export start delay and be modified as constant, and not rely on the conversion magnification ratio of pixel quantity.
Thereby, what consider is, when the register with the tap of a shift register output center as one man provides " no " individual register and provides " ni " individual register at input end at output terminal, to shift register input intensity serial data, wherein (no+ni) item at first of intensity data changes continuously.When having set up 5 taps of level as mentioned above, the no=ni=2 of relation and no+ni=4 are arranged here.
In this case, shown in Figure 24 E, will " be submitted to tap from rate conversion unit 215Y and set up unit 221Y by the brightness signal Y c that modification brightness signal Y c (shown in Figure 24 B) obtains.In this case, shown in Figure 24 D, trigger STR corresponding to the brightness signal Y c displacement of change position of intensity data of intensity data string " trigger STR " rather than displacement, be submitted to tap to set up the shift register of unit 221Y (shown in Figure 24 C) from rate conversion unit 215Y.
If use tap to set up 5 taps that circuit 221Y has set up level, centre tapped change is shown in Figure 24 G.Figure 24 F shows the centre tapped change time.Figure 24 A shows the arrangement of each project of the intensity data of brightness signal Y a before the rate conversion with the change position consistency of the intensity data of the intensity data string of brightness signal Y c.
By the intensity data string of shift register input to every row, wherein (no+ni) project at first of intensity data changes continuously, and the output start delay can be fixed on the clock time (no+ni) of output clock Cko.
And in this case, centre tapped change corresponding to rate conversion after the arrangement of intensity data string of brightness signal Y c so that before rate conversion, obtain 5 taps of level the arrangement of the intensity data of brightness signal Y a.
Though described above, can from rate conversion unit 215Y, obtain displacement and trigger STR ', STR ", can also obtain STR ', STR from other unit outside the rate conversion unit 215Y ", for example, output TG217.This output TG217 will read address RADr and submit to rate conversion unit 215Y, thereby may obtain at an easy rate and brightness signal Y c ', Yc " the relevant information in change position of intensity data of intensity data string.
Though ignored detailed description, tap is set up the mode of setting up of circuit 221C and is set up the identical of circuit 221Y with above-mentioned tap." be submitted to tap from rate conversion unit 215C and set up circuit 221C, colour difference signal Uc ", Vc " and displacement trigger STR " modification and above-mentioned brightness signal Y c " STR are " similar with the triggering that is shifted in this case, colour difference signal Uc ", Vc " and displacement to be triggered STR.Then, circuit 221C is set up in tap can be in 5 taps that obtain level before the rate conversion in the arrangement of colour difference signal Ua, Va, and fixing output start delay.
Next, will the operation of rate conversion circuit 105 shown in Figure 3 be described.
Be submitted to impact damper 204Y, 204C in the sdram controller 202 with constituting the brightness signal Y a of the picture signal Sa to be input to entry terminal 104 (see figure 1)s and colour difference signal Ua/Va.Corresponding to the valid pixel part of horizontal direction, be submitted to the impact damper 204Y of every row, each of 204C with writing address WADi from input TG207, and write brightness signal Y a and colour difference signal Ua/Va continuously.
After the valid pixel of the horizontal direction of every row partly finishes, write request WRQ from input TG207 generation.This is write the control module 206 that request WRQ submits to sdram controller 202.Control module 206 generate to be submitted to impact damper 204Y, 204C read address RADi, and to be submitted to frame memory 201 write address WADm.
The address RADi that reads that generates in control module 206 is submitted to impact damper 204Y, 204C.The address WADm that writes that generates in control module 206 is submitted to frame memory 201.Correspondingly, the mode of dividing with the time from impact damper 204Y, 204C is read the brightness signal Y a that temporarily is stored among impact damper 204Y, the 204C and the valid pixel part of colour difference signal Ua/Va, send it to frame memory 201 by SDRAM bus 203, write a presumptive address of this frame memory 201 then.
Further, generate one from storer TG211 and read request RRQ.Generate this at each official hour and read request RRQ (seeing Fig. 5,6A, B).Use vertical reset signal VRS, the vertical counter 213 of storer TG211 is reset to " 0 ", this vertical reset signal VRS submits to from start time of the valid pixel part of the vertical direction of the output image signal Sc of output TG217 the time.Although " 0 the time, this is read request RRQ and generates at first, after this, generates it when this memory clock CKm (108MHz) counts to n when the count value of this vertical counter 213 becomes.
In this case, the cycle " t " of reading request RRQ is one and divides the time that obtains the single vertical effective period of output image signal Sc by the quantity that is used for the capable object of rate conversion with this received image signal Sa.That is to say, when the cycle is " t ", the dot frequency of output image signal Sc is " fo ", the quantity of the capable object that is used to change of received image signal Sa is " mi ", the quantity of the row in the single vertical effective period of output image signal Sc is " mo ", and the quantity of the pixel of every row of output image signal Sc is " no ", and the t=mo/mi/fo of relation * no is arranged here.Thereby above-mentioned n becomes n=t * 108MHz.
The request of the reading RRQ that storer TG211 is generated is submitted to the control module 206 in the sdram controller 201.Corresponding to reading request RRQ, control module 206 generate one to submit to frame memory 201 read address RADm, and one to submit to impact damper 205Y, 205C write address WADo.The address RADm that reads that control module 206 is generated is submitted to frame memory 201.Further, the address WADo that writes that control module 206 is generated is submitted to impact damper 205Y, 205Y.
Correspondingly, when request RRQ was read in generation, the colour difference signal Ua/Va of the brightness signal Y a of 10 row and 2 row was synchronously read from frame memory 201 with store clock CKm (108MHz), and is submitted to impact damper 205Y, 205C by SDRAM bus 203.In this case, the mode of dividing with the time transmits the brightness signal Y a of 10 row and the colour difference signal Ua/Va of 2 row, the i.e. signal of 12 row.
Each brightness signal Y a that are submitted to 10 row of impact damper 205Y is written into each of SRAM of 10 row that constitute impact damper 205Y.Similarly, the colour difference signal Ua/Va that are submitted to 2 row of impact damper 205C are written into each of SRAM of 2 row that constitute impact damper 205C.
Corresponding to reading request RRQ is sent to brightness signal Y a and colour difference signal Ua/ Va impact damper 205Y, 205C and writes wherein from frame memory 201 after, storer TG211 generate to be submitted to impact damper 205Y, 205C read address RADo, and to be submitted to rate conversion unit 215Y, the 215C that will be described later write address WADr.Address RADo be will read and impact damper 205Y, 205C will be submitted to.Further, address WADr be will write and rate conversion unit 215Y, 215C will be submitted to.
When request RRQ is read in one of generation, it is sent out from frame memory 201, and be stored in impact damper 205Y, 205C temporarily.The colour difference signal Ua/Va of the brightness signal Y a of 10 row and 2 row synchronously is sent to rate conversion unit 215Y, 215C with output clock CKm (108MHz), is written into rate conversion unit 215Y, 215C then.
Corresponding to effective unit of horizontal direction of each row of the valid pixel part of the vertical direction of output image signal Sc, generate from the scalar/vector 218 of output TG217 and to read address RADr.Address RADr be will read and rate conversion unit 215Y, 215C will be submitted to.
In this case, scalar/vector 218 generates a reference address RADr0 at the valid pixel initial location of pixels (seeing the some P of Fig. 4) partly of horizontal direction and the vertical direction of output image signal Sc.This reference address RADr0 represents the record position of the pixel data of a reference position corresponding to the rate conversion object unit AT of the received image signal Sa of rate conversion unit 215Y, 215C (seeing the some Q of Fig. 4).
Because the phase information of the initial location of pixels of horizontal direction valid pixel part is 0, scalar/vector 218 uses output clock Cko, add anti-several Mh of a horizontal extension ratio for each location of pixels that will submit to, if the value of adding up is littler than 4096, this value of adding up is counted as the phase information " h " of the horizontal direction of location of pixels.On the other hand, if the value of adding up is little unlike 4096, carry taking place, deducts the phase information " h " on the horizontal direction that 4096 values that obtain are counted as this location of pixels like this from the value that this is added up.
If this value of adding up is littler than 4096, and carry does not take place, as reading address RADr, scalar/vector 218 outputs and in front an identical value of location of pixels just corresponding to this location of pixels.On the other hand, if carry takes place, as reading address RADr, advanced from front the address of location of pixels just 1 address of its output corresponding to this location of pixels.
Correspondingly, if the value of adding up is littler than 4096, and carry does not take place, as reading address RADr corresponding to this location of pixels, use and in front the identical value of location of pixels just, and this location of pixels from rate conversion unit 215Y, 215C reads and in front the identical pixel data of location of pixels just.Thereby, rate conversion unit 215Y, 215C obtain brightness signal Y c and the colour difference signal Uc/Vc after the rate conversion, wherein on the horizontal direction pixel quantity with respect to rate conversion before brightness signal Y a and colour difference signal Ua/Va, corresponding to the extensive ratio of horizontal direction and increase.
Because the phase information of the initial location of pixels of vertical direction valid pixel part is 0, scalar/vector 218 has wherein generated horizontal-drive signal HDo at anti-several Mv of an extends perpendicular ratio of every row interpolation in this row.If the value of adding up is littler than 4096, this value of adding up is counted as the phase information " v " of the vertical direction of this row.On the other hand, if the value of adding up is little unlike 4096, carry taking place, deducts the phase information " v " on the vertical direction that 4096 values that obtain are counted as this row like this from the value that this is added up.
If this value of adding up is littler than 4096, and carry does not take place, as reading address RADr, scalar/vector 218 outputs and in front an identical value of row just corresponding to this row.On the other hand, if carry takes place, as corresponding to this row read address RADr, a value behind scalar/vector 218 output modifications is with the pixel data of the next line that reads out in received image signal Sa.
If the value of adding up is littler than 4096, and carry does not take place, as corresponding to this row read address RADr, use and in front the identical value of row just, and this row from rate conversion unit 215Y, 215C reads and in front the identical pixel data of row just.Thereby, rate conversion unit 215Y, 215C obtain brightness signal Y c and the colour difference signal Uc/Vc after the rate conversion, wherein pixel quantity phase time brightness signal Y a and colour difference signal Ua/Va before rate conversion on the vertical direction are corresponding to the extensive ratio of vertical direction and increase (seeing Fig. 9,10).
From rate conversion unit 215Y, SRAM by above-mentioned 10 row obtains the brightness signal Y c of 10 row and the brightness signal Y c of 8 row, the brightness signal Y c of 10 row read address RADr based on TG217 generated by output, the brightness signal Y c of 8 row are based on the little address of number of pixel per line.That is, obtain the brightness signal Y c (seeing Figure 14 A, 15A) of 18 row concurrently from rate conversion unit 215Y.When image signal processing unit 106 obtains constituting the intensity data of output image signal Sb in the target location of brightness signal Y b, use the brightness signal Y c of 18 row to go to extract prediction tapped and class tap.
From rate conversion unit 215C, the SRAM by above-mentioned 2 row obtain reading based on TG217 generated by output address RADr 2 row colour difference signal Uc, Vc and based on colour difference signal Uc, the Vc of 2 row of the address of little number of pixel per line.That is, from rate conversion unit 215C parallel colour difference signal Uc, the Vc (seeing Figure 14 B, 15B) that obtain each 4 row.When image signal processing unit 106 obtained constituting the chromatism data of output image signal Sb in the target location of colour difference signal Ub, Vb, using each was that 4 colour difference signal Uc, the Vc that go go to extract prediction tapped and class tap.
Obtain the 18 brightness signal Y c that go by rate conversion unit 215Y, 215C, and colour difference signal Uc, Vc of each 4 row stretch on vertical direction and time orientation.Though can extract the tap (class tap, prediction tapped) of vertical direction and time orientation by image signal processing unit 106 at an easy rate, the tap of horizontal direction is not stretched, thereby the tap that will extract on the horizontal direction is very difficult.
Based on the brightness signal Y c of 10 row and colour difference signal Uc, the Vc of each 2 row, the tap that circuit 221Y, 221C set up horizontal direction is set up in tap, and this luminance signal and colour difference signal obtain by rate conversion unit 215Y, 215C.Setting up circuit 221Y to tap provides 18 shift register 222-1 of brightness signal Y c corresponding to 18 row to 222-18 (seeing Figure 17).Similarly, setting up to tap that circuit 221C provides corresponding to each is 8 shift registers of colour difference signal Uc, Vc of 4 row.Thereby each register all is made up of the register that equates with number of taps that horizontal direction will be set up.
The shift register that circuit 221Y is set up in tap is formed in the input of luminance signal after the rate conversion.Trigger corresponding to a displacement of the change position of the intensity data of the intensity data string of luminance signal and to be submitted to shift register.Whenever displacement triggers when being submitted to shift register, obtain intensity data continuously corresponding to the dislocation of the intensity data string of luminance signal.This sets up circuit 221C too for tap.
According to present embodiment, will be for one corresponding to the centre tapped change of the arrangement of the intensity data string of brightness signal Y c after the rate conversion, with amended intensity data string input shift register, this serial data is that the change position by the intensity data string intensity data of revising brightness signal Y c obtains.When with to export this centre tapped register when consistent, provide " no " individual register on the output limit of shift register, and provide " ni " individual register on its input limit, regard amended intensity data string the result of as continuous (no+ni) the individual project at first that changes intensity data, and continuously the intensity data of (no+ni) individual project is inserted shift register.
According to the present invention, the brightness signal Y c that obtains by the intensity data string (suitable intensity data string) of revising brightness signal Y c ", set up unit 221Y from rate conversion unit 215Y input tap.Further, submit to corresponding to this brightness signal Y c displacement of change position of intensity data of intensity data string " trigger STR " (seeing Figure 24 A-G).This sets up circuit 221C too for rate conversion unit 215C and tap.
Correspondingly, corresponding to the arrangement of brightness signal Y c, the intensity data string of colour difference signal Uc, Vc and the chromatism data string after the rate conversion, change center tap, so that obtain 5 taps of level in the arrangement of the intensity data of brightness signal Y a that can be before rate conversion and colour difference signal Ua, Va and chromatism data.Further, the output start delay that circuit 221Y, 221C are set up in tap can be fixed on the clock time (no+ni) of exporting clock Cko, so not needing provides a variable delay circuit to image signal processing unit 106, wherein this delay circuit can change time delay according to the conversion magnification ratio of pixel quantity, so that use other Signal Regulation execution time, phase information (phy, pvy) (phc, pvc) for example.
In rate conversion circuit 105 shown in Figure 3, read request RRQ from storer TG211 generation, and based on this read the request RRQ, brightness signal Y a and colour difference signal Ua/Va are sent to rate conversion unit 215Y, 215C with behavior unit from frame memory 201 by impact damper 205Y, 205C.Thereby, at brightness signal Y a and colour difference signal Ua/Va to the transmission cycle, not having deviation, so can guarantee in each transmission cycle that the stable data travelling belt is logical as rate conversion unit 215Y, the 215C of second memory as the frame memory 201 of first memory.Correspondingly, each transmission cycle from frame memory 201 to rate conversion unit 215Y, 215C, rate conversion circuit 105 can both stably transmit 10 the row brightness signal Y a and 2 the row colour difference signal Ua/Va, promptly altogether 12 the row signals.
Next, describe sdram controller 202 further in detail with reference to Figure 25.In Figure 25,, and omitted description to it with the Reference numeral of assembly is identical accordingly among Fig. 3.
Submit a vertical synchronizing signal VDi synchronous to sdram controller 202 with received image signal Sa, the quantity, zone, center of also submitting the valid pixel quantity of the horizontal direction of received image signal Sa, the valid pixel quantity of received image signal Sa vertical direction (the effectively quantity of row), delivery channel to and initial row and to the difference of the center of each delivery channel, as external parameter.
As mentioned above, corresponding to the single request RRQ that reads, read the brightness signal Y a of 10 row and the colour difference signal Ua/Va of 2 row from frame memory 201 (SDRAM).Here, with the data of single row as the 1-channel data.
It is appointment that this regional center is positioned at how many zones, front that write frame memory 201 zones relatively.The initial row of supposing it is the first row (see figure 4) capable with respect to the av of rate conversion object unit AT.Further, suppose that the position above-mentioned centre bit of distance of each channel is equipped with some differences, in other words, distance center position ± zone, ± OK.
Read/write control module 307 generates one and writes sign WFL, follow the channel information of the request that the writes WRQ (see figure 1) of submitting to corresponding to input TG207, and further generate one and read sign RFL, follow the channel information of the request of the reading RRQ (see figure 3) of submitting to corresponding to storer TG211.
Write sign WFL corresponding to what submit to from read/write control module 307, read counter 305 generates one and will be submitted to and read address RADi as impact damper 204Y, the 204C of write buffer.This is read address RADi and is submitted to impact damper 204Y, 204C.Write sign WFL corresponding to what submit to from read/write control module 307, write address unit 303 generate one to be submitted to frame memory 201 write address WADm.To write address WADm by order maker 301 and be submitted to frame memory 201.
Read sign RFL corresponding to what submit to from read/write control module 307, read address location 304 generate one to be submitted to frame memory 201 read address RADm.By order maker 301 this is read address RADm and be submitted to frame memory 201.Read sign RFL corresponding to what submit to, write counter 306 and generate one and will be submitted to and write address WADo as impact damper 205Y, the 205C of sense buffer from read/write control module 307.This writes address WADo and is submitted to impact damper 205Y, 205C.
Read sign RFL corresponding to first of each territory, read scalar/vector 304 and generate one and read address RADm, to read corresponding to 12-channel data from the first capable line correlation of the av of the rate conversion object unit AT of the received image signal Sa of frame memory 201.Based on provide as mentioned above as the zone of the center of external parameter and the difference between the initial row, perhaps and from the difference between the center of each regional vertical blank each delivery channel in the cycle, calculate this and read address RADm.
Read scalar/vector 304 and generate one and read address RADm, with read with corresponding to 12-channel data from the capable 2-N line correlation of the av of the rate conversion object unit AT of the received image signal Sa of frame memory 201.In this case, by increase gradually as first row read address RADm, can obtain as 2-N capable read address RADm.
Energising (power ON) sequence of sdram controller 202 will be described below.Because its state is unclear during frame memory (SDRAM) 201 energising, when energising, at power standard after the time, stipulates that it locates to carry out precharge at all memory banks (banks), pattern resets and refresh.Yet if owing to import a vertical synchronizing signal VDi, sdram controller 202 resets execution pattern and refreshes, so during in importing vertical synchronizing signal VDi some, will automatically perform the powerON sequence.
Pattern is provided with/refreshes maker 302 and generates a controlled flag for the pattern setting of frame memory 201/refresh, and this sign is accompanied by the input of vertical synchronizing signal VDi.Order maker 301 is the necessary order of control generation of frame memory 201 based on controlled flag.
The refresh cycle of SDRAM will be described here.SDRAM needs a refresh operation to keep the data that write.For example, according to present embodiment, use the SDRAM of 16Mbit * 4 memory banks.As for this SDRAM, the refresh cycle of any memory product is configured to 4096 times/64ms.According to present embodiment,, when input vertical synchronizing signal VDi, use this blank cycle to carry out in a lump and refresh because be 60Hz or 50Hz the regional cycle of received image signal Sa.
Though in the superincumbent description, illustrate that for the convenience of explaining received image signal Sa is that 480i signal (60Hz) and output image signal Sb are 1080i signal (60Hz), received image signal Sa and output image signal Sb are not limited in these situations.In this case, because received image signal Sa is different with the form of output image signal Sb, be different with blank cycle regional cycle, a kind of refresh mode is provided here, it is imported vertical synchronizing signal VDi by twice or three times and divides this refresh operation, and satisfies the condition of 4096 times/64ms.
The operation of sdram controller shown in Figure 25 202 will be described below.
For the pattern setting of frame memory 201/refresh, reading or before wherein writing that the input from vertical synchronizing signal VDi begins from frame memory 201, pattern setting/refresh maker 302, write address unit 303, read that address location 304 and Writing/Reading control module 307 calculate these frame memories 201 one write address WADm, with and read address RADm.The reason that write address unit 303 is provided respectively and reads address location 304 is, writing and be independent respectively the execution from reading of frame memory 201 frame memory 201.
When having imported vertical synchronizing signal VDi, in pattern setting/refresh a controlled flag is proposed in the maker 302, be used for frame memory 201 execution pattern settings and refresh.This controlled flag is submitted to order maker 301.Based on this controlled flag, order maker 301 generates the required order of control frame storer 201.This order is submitted to frame memory 201.Correspondingly, at every turn when input vertical synchronizing signal VDi, the pattern setting of execution frame memory 201 and refreshing.
Corresponding to the valid pixel part of the horizontal direction of every row, submit to impact damper 204Y, 204C from input TG207 (see figure 3) to write address WADi, and write brightness signal Y a and the colour difference signal Ua/Va that constitutes received image signal Sa one by one.
After the valid pixel of the horizontal direction of every row partly finishes, write request WRQ to 307 submissions of read/write control module from input TG207.Meanwhile, write request WRQ owing to sent, impact damper 204Y, 204C need store next line brightness signal Y a and colour difference signal Ua, the Va of new input, up to carrying out read operation.Thereby dual-port SRAM is as these impact dampers 204Y, 204C.
Writing or reading in the read/write control module 307 judgment frame storeies 201.When it determined that frame memory will be in write operation, it submitted to one to follow writing of channel information to indicate WFL to read counter 305 and write address unit 303.Correspondingly, generate one from read counter 305 and read address RADi, and it is submitted to impact damper 204Y, 204C, meanwhile, 303 one of generation write address WADm from the write address unit, and by order maker 301, it are submitted to frame memory 201.
To be stored in the brightness signal Y a of every row of impact damper 204Y, 204C and the valid pixel of colour difference signal Ua/Va partly reads from impact damper 204Y, 204C temporarily, by SDRAM bus 203, send it to frame memory 201, and it is write the presumptive address of frame memory 201.In this case, with speed and the input clock Cki of 8bit, with input luminance signal Ya and colour difference signal Ua/Va input buffer 204Y, 204C.From impact damper 204Y, 204C to frame memory 201, input luminance signal Ya and colour difference signal Ua/Va are converted into 32 bit data, and are transmitted by the speed with memory clock CKm (108MHz).In this case, by SDRAM bus 203, the mode of dividing with the time is with the 2-channel data, and promptly input luminance signal Ya and colour difference signal Ua/Va are sent to frame memory 201, and write wherein.
Further, submit to one to read request RRQ from storer TG211 to read/write control module 307.307 judgements of read/write control module write or read in frame memory 201.When if it determines that frame memory will carry out read operation, it is to writing counter 306 and reading address location 304 and submit to one to follow reading of channel information to indicate RFL.Correspondingly, read address RADm from reading address location 304 one of generation,, and, it is submitted to frame memory 201 by order maker 301.Generate a write address WADo from writing counter 306, and it is submitted to impact damper 205Y, 205C.
Thereby, read request RRQ corresponding to one, whenever generating one from read/write control module 307 when reading sign, synchronously read a 12-channel data with memory clock CKm (108MHz) from frame memory 201, and by SDRAM bus 203, be sent to impact damper 205Y and impact damper 205C, and write wherein.In this case, the mode of dividing with the time transmits the 12-channel data.
As mentioned above, corresponding to reading request RRQ, with the 12-channel data after frame memory 201 is sent to impact damper 205Y, 205C, to read address RADo and be submitted to impact damper 205Y, 205C, and write address WADr will be submitted to rate conversion unit 215Y, 215C (see figure 3) from storer TG211 (see figure 3).
When request RRQ was read in generation, the 12-channel data that transmits from frame memory 201 was temporarily stored in impact damper 205Y, 205C, and it is sent to rate conversion unit 215Y, 215C then, and is stored in wherein.
Figure 26 shows the configuration of read/write control module 307.This reads/and comprise a write-channel counter 311 with control module 307, read channel counter 312, the request of reading hangs up unit 313 and channel counter 314.The request of the reading WRQ (see figure 3) that generates among the input TG207 is submitted to write-channel counter 311 and reads channel counter 312.Further, the request of the reading RRQ (see figure 3) that generates among the storer TG211 is submitted to reads channel counter 312 and unit 313 is hung up in the request of reading.
When receiving the request of writing during WRQ, write-channel counter 311 is provided with the count value of the quantity of write-channel as himself, whenever to a channel write beginning the time, count value is deducted 1.When this count value reaches 0, finish write operation.When the quantity that write-channel is set as mentioned above during as himself count value, write-channel counter 311 sends a counting opening flag CSF to 314 countings that begin channel count 314 of channel counter.
When receiving the request of writing during WRQ, write-channel counter 311 is provided with 2 count values as himself.It is that brightness signal Y a and colour difference signal Ua/Va are written into frame memory 201 respectively that 2 reason is set, thereby needs the data of a 2-channel to write.
When having submitted to one to read request RRQ or request and hang up and to have hung up one in the unit 313 when reading request RRQ, if write state is not ON when checking the count value of write-channel counter 311, reads channel counter 312 count value of the quantity of read channel as himself is set.When reading of each channel begins, read the count value of channel counter 312 and successively decrease.When this count value reached 0, read operation finished.
When the quantity that read channel is set as mentioned above during, read channel counter 312 and send a counting opening flag CSF to channel counter 314, to begin the counting of channel counter 314 as himself count value.When input simultaneously as mentioned above writes request WRQ and the request of reading during RRQ, the quantity that read channel is set is as count value, yet, do not submit counting opening flag CSF to channel counter 314.
When receiving counting opening flag CSF, channel counter 314 its counting operations of beginning.In this case, channel counter 314 little by little synchronously increases count value with memory clock CKm (108MHz) from 0, and if count value reach the maximal value consistent with channel data length, this count value returns 0, so that state becomes dormant state, wait for input counting opening flag CSF.
Here, maximal value is corresponding to the clock number of memory clock CKm, wherein this memory clock CKm is corresponding to 201 1-channel data transmits the time from impact damper 204Y, 204C to frame memory, or the 1-channel data from frame memory 201 to impact damper 205Y, 205C transmits the time.As mentioned above, when received image signal Sa was the 480i signal, the valid pixel quantity of horizontal direction was 720 pixels.Because 8 data are converted into 32 bit data, and transmit with this form, maximal value is MAX=720/4=180.
Further, when count value returned 1, channel counter 314 generated an opening flag SFL, and it is submitted to write-channel counter 311 and reads channel counter 312.Further, when count value reached maximum, channel counter 314 generated an end mark EFL, and it is submitted to write-channel counter 311 and reads channel counter 312.
When the opening flag SFL that submits to from channel counter, what write-channel counter 311 generated a channel information that is accompanied by corresponding and this count value when self count value is not 0 writes sign WFL, and it is submitted to read counter 305 and write address unit 303, and further reduce this self count value.
Correspondingly, generate to be used to read from read counter 305 and read address RADi corresponding to the channel data of this channel information.303 generate the write address WADm that is used to write corresponding to the channel data of this channel information from the write address unit.To be sent to frame memory 201 corresponding to the channel data of channel information from impact damper 204Y, 204C, and write wherein.
When channel counter 314 is submitted end mark EFL to, when self count value was not 0, write-channel counter 311 generated the counting opening flag CSF that is used to write next channel,, and it is submitted to channel counter 314.
When from channel counter 314 submission opening flag SFL, when the count value of write-channel counter 311 is 0 and this self count value when being not 0, reading channel counter 312 generates one and is accompanied by and reads sign RFL corresponding to the channel information of this count value, and it is submitted to reads address location 304 and write counter 306, reduce self count value then.
Correspondingly, read address location 304 generations and read address RADm, be used to read channel data corresponding to channel information.Write counter 306 and generate write address WADo, be used to write channel data corresponding to channel information.Corresponding to the channel data of channel information, be sent to impact damper 205Y, 205C from frame memory 201, and be written into wherein.
When the end mark EFL that submits to from channel counter 314, when the count value of write-channel counter 311 is 0 and self count value is not 0,312 in read channel counter generates counting opening flag CSF, is used for the read next channel, and it is submitted to channel counter 314.
Further, when receiving the request of reading during RRQ, unit 313 is hung up in the request of reading increases the quantity of being hung up.Further, the request of reading is hung up unit 313 based on reading request RRQ, and the quantity that read channel is set in reading channel counter 312 when this count value becomes 0, reduces the quantity of being hung up as count value.
Write operation one end does not write request and hangs up.Reason is to write the right of priority of request WRQ greater than the right of priority of reading, and in ablation process, does not ask WRQ with writing of timing form submission.
With regard to said structure, will illustrate below, read request RRQ and write the dormant state of asking WRQ.At an initial state, wherein not carry out and read or write, this state appears.Write-channel counter 311, read channel counter 312, unit 313 is hung up in the request of reading and channel counter 314 has 0 original state at one.Write-channel counter 311 waits for that input writes request WRQ, reads request RRQ and read channel counter 312 wait inputs.The request of reading is hung up unit 313 waits and is read request RRQ.
Next, will use shown in Figure 27 A-J " (1) writes independently/reads ", and describe one and under original state, submitted an operation that writes under the situation of asking WRQ independently to.
When synchronously importing one, the horizontal-drive signal HDi with relevant with received image signal Sa (Figure 27 A, B) writes request during WRQ, write-channel counter 311 is provided with 2 as himself count value, and submit counting opening flag CSF to channel counter 314, wherein 2 is the quantity (Figure 27 E) of write-channel.Channel counter 314 synchronously increases count value with memory clock CKm, and when count value reaches 1, generates opening flag SEL.Figure 27 I shows the count value of channel counter 314, and one does not have 0 unit representing that state has little by little changed to maximal value from 1.
Thereby write-channel counter 311 generates has followed writing of channel information to indicate WFL (Figure 27 D).Correspondingly, begin first channel is write.At this moment, write-channel counter 311 is reduced to 1 (Figure 27 E) with the count value of self.Figure 27 J shows the data transfer state of SDRAM bus 203.
When the count value of channel counter 314 reaches corresponding to the maximal value of the end that writes of first channel time, this channel counter 314 generates end mark EFL.Write-channel counter 311 is submitted counting opening flag CSF to channel counter 314 once more, because himself count value is not 0 but 1 (Figure 27 E).Channel counter 314 synchronously increases count value with memory clock CKm, when its count value becomes 1, generates opening flag SFL.
Thereby write-channel counter 311 generates follows writing of channel information to indicate WFL (Figure 27 D).As a result of, begin second channel is write.At this moment, write-channel counter 311 is counted self to pass and is reduced to 0 (Figure 27 E).
Corresponding to the end that writes to second channel, that is, when the count value of channel counter 314 reached maximal value, channel counter 314 generated end mark EFL.Because self count value is 0, write-channel counter 311 is prevented and is generated counting opening flag CSF or other signs.Correspondingly, write request WRQ, the writing of equal number of finishing 2 channels by input.
Next, will use shown in Figure 27 A-J " (1) writes independently/reads ", and describe one and under initial state, submitted an operation of reading under the situation of asking RRQ independently to.
When having imported the request of reading during RRQ (Figure 27 C), read quantity that channel counter 312 is provided with read channel as himself count value (Figure 27 G), because the count value of write-channel counter 311 is 0 (Figure 27 E).Though the quantity of read channel is actually 12, for convenience, what be provided with in the example of Figure 27 A-J is 4.Read request RRQ (Figure 27 C) if imported one, the request of reading is hung up unit 313 quantity of hanging up is increased to 1 (Figure 27 H).
After reading the quantity that channel counter 312 is provided with read channel, it submits counting opening flag CSF to channel counter 314.Channel counter 314 synchronously increases count value with memory clock CKm, and when count value reaches 1, generates an opening flag SFL.Thereby, read channel counter 312 one of generation and follow reading of channel information to indicate RFL (Figure 27 F).Correspondingly, begin reading of first channel.At this moment, read channel counter 312 and reduce himself count value (Figure 27 G).
Corresponding to the end of reading from first channel, promptly when the count value of channel counter 314 reached maximal value, channel counter 314 generated end mark EFL.Read channel counter 312 and submit counting opening flag CSF to channel counter 314 once more, because the count value of write-channel counter 311 is 0 and himself count value is not 0.Channel counter 314 synchronously increases count value with memory clock CKm, when count value reaches 1, generates an opening flag SFL.
Thereby read channel counter 312 one of generation and follow reading of channel information to indicate RFL (Figure 27 F).As a result, the beginning second channel reads.At this moment, read channel counter 312 and further reduce himself count value (Figure 27 G).
In kind, carry out up to reading last channel.Corresponding to the end of reading of last channel, that is, when the count value of channel counter 314 reached its maximal value, channel counter 314 generated end mark EFL.Read channel counter 312 and prevent the generation of counting opening flag CSF or the generation of other sign, because himself count value is 0.Correspondingly, be through with by read identical of input of reading request RRQ with read channel quantity.Simultaneously, when the count value of reading channel counter 312 becomes 0, read and ask hang-up unit 313 to reduce the quantity of being hung up.
Next, describe one and under initial state, write request WRQ and the operation of reading under the situation of asking RRQ in identical time input.
Though read channel counter 312 count value of the quantity of read channel as himself is set, because the request of the reading RRQ that it receives asks WRQ with writing, its is prevented to channel counter 314 and submits counting opening flag CSF to.
In this case, write-channel counter 311 is provided with 2 as himself count value, and submits counting opening flag CSF to channel counter 314, wherein, the 2nd, the quantity of write-channel.Mode when therefore, carrying out the method for write operation and submission writes request WRQ separately is identical.
When channel counter 314 generates corresponding to the end mark EFL that writes that finishes second channel, as mentioned above, write-channel counter 311 is prevented the generation of counting opening flag CSF or the generation of other sign, because himself count value is 0, then, write operation finishes.
Because in this case, the count value of write-channel counter 311 is 0, and the count value of himself is not 0, reads channel counter 312 and submits counting opening flag CSF to channel counter 314.Correspondingly, after write operation finishes, the beginning read operation.Method when carrying out the method for this read operation and request RRQ is read in submission separately is identical.
Next, will use shown in Figure 27 A-J " read in the process that writes (2) ", and describe one and in the process of write operation, submitted an operation of reading under the situation of asking RRQ to.
When having submitted to one to read request in the process at write operation (Figure 27 C), the value of reading channel counter 312 prevention read channels is set to the count value of self and submits counting opening flag CSF to channel counter 314, because the count value of write-channel counter 311 is not 0.
In this case, the request of reading is hung up unit 313 quantity of the request of the reading RRQ that hung up is increased to 1 (Figure 27 H).Read the count value of channel counter 312, determine whether carrying out a write operation based on write-channel counter 311.That is to say that when count value was not 0, it determined carrying out write operation, and when count value was 0, it determined do not carrying out write operation.
When channel counter 314 as above-mentioned, corresponding to end, when generating end mark EFL to the write operation of second channel, write-channel counter 311 is prevented and is generated counting opening flag CSF or other sign, because self count value is 0, then, finish write operation.
In this case, read channel counter 312 and prevent the quantity of read channels to be set to self count value, and submit counting opening flag CSF to, because the count value of write-channel counter 311 is 0 and the count value of himself also is 0 to channel counter 314.
Yet, when reading request RRQ and hang up the request of reading and hang up in the unit 313, read channel counter 312 quantity of read channel is arranged to self count value (Figure 27 G), then, submit counting opening flag CSF to channel counter 314.Correspondingly, after write operation finishes, the beginning read operation.Method when the method for carrying out this read operation is read request RRQ with above-mentioned independent submission is identical.When read operation has finished and the count value of reading channel counter 312 when becoming 0, the request of reading is hung up unit 313 quantity of hanging up is reduced to 0 (Figure 27 H).
Read channel counter 312 based on the hang-up number of reading request hang-up unit 313, determine whether the request of the reading RRQ of hang-up.In other words, when the hang-up number was not 0, its determined carrying out pending operation, and when the value of hanging up was 0, it was determined not at the execution pending operation.
Next, will use, and describe one and in the process of read operation, submitted under the situation that writes request (93) WRQ and operate as " (3) write in the process of reading " among Figure 27.
When input writes request WRQ (Figure 27 B), write-channel counter 311 is provided with 2 count values as himself (Figure 27 E), and the 2nd, the quantity of write-channel, and to channel counter 314 submission counting opening flag CSF.In this case, owing to carry out read operation, channel counter 314 based on from the counting opening flag CSF that reads channel counter 312, has begun its counting operation (Figure 27 I).
When the count value of channel counter 314 reached a maximal value corresponding to the end of read channel, channel counter 314 generated end mark EFL.Because the count value of write-channel counter 311 is not 0, reads channel counter 312 and prevent to channel counter 314 submission counting opening flag CSF.
At this moment, because the count value of self is not 0, write-channel counter 311 generates counting opening flag CSF, and it is submitted to channel counter 314.Correspondingly, stop read operation temporarily, and the beginning write operation.
If as mentioned above, corresponding to the end of the write operation of second channel, in channel counter 314, generate end mark EFL, write-channel counter 311 is prevented and is generated counting opening flag CSF, because the count value of himself is 0, then, write operation finishes.
In this case, read channel counter 312 and submit counting opening flag CSF to channel counter 314, though because the count value of write-channel counter 311 is 0, the count value of himself is not 0 (in the example shown in Figure 27 A-J, count value is 2).Correspondingly, after write operation finished, read operation restarted.When read operation finishes and the count value of reading channel counter 312 when reaching 0, the quantity of hang-up is reduced to 0 (Figure 27 H).
Figure 28,29 process flow diagram show a processing procedure, are used to use software to finish the operation of above-mentioned Writing/Reading control module 307.
At first, begin a processing, and, W=0, R=0, RH=0 and CH=0 are set at step ST12 at step ST11.Here, W is corresponding to the count value of write-channel counter 311, and R is corresponding to the count value of reading channel counter 312, and RH hangs up unit 313 number of hanging up corresponding to the request of reading, and CH is corresponding to the count value of channel counter 314.
Next, at step ST13, determined whether the request input.Write request WRQ and read request RRQ if exist simultaneously, increase the hang-up of reading request RRQ at step ST14 and count RH.Then, at step ST15, for example, the quantity of read channel is 12, is arranged to count value R with 12.At step ST16, the quantity 2 of write-channel is arranged to count value W.
If step ST13 only imported write the request WRQ, process advances to step ST16 at once, then the quantity 2 of write-channel is arranged to count value W.After the processing of step ST16, process advances to step ST17.In step ST17, output counting opening flag CSF.Then, at step ST18, begin upwards to count down to count value CH.Upwards counting is synchronously carried out with memory clock CKm.
Next, at step ST19, determine whether to be provided with CH=1.If CH=1, output is followed corresponding to writing of the channel information of count value W and is indicated WFL, and WFL is submitted to read counter 305 and write address unit 303 (seeing Figure 26).In step ST20, reduce count value W.After the processing of step ST20, process advances to step ST21.
At step ST21, determine whether to be provided with CH=MAX.If be provided with CH=MAX,, stop upwards counting with CH=0 at step ST22.Then, at step ST23, determine whether count value W is 0.Unless W=0, process turns back to the step ST17 that writes processing that carries out next channel.
Unless in step ST21, be provided with CH=MAX,, determine whether to have imported to read and ask RRQ at step ST24.Read request RRQ if imported, in step ST25, increase the hang-up of reading request RRQ and count RH.If do not import in step ST24 or after the processing of step ST25 and read request RRQ, process turns back to step ST21.Correspondingly, read request RRQ, then hang up this and read request RRQ when in the write operation process, having imported.
When be provided with W=0 in step ST23, write operation finishes.Then, determine at step ST26 whether count value R is 0.If be provided with R=0, whether RH is counted in the hang-up of determining to read request RRQ in step ST27 is 0.If be provided with RH=0, the hang-up that the interruption of read operation does not take place or read request RRQ, thereby process turns back to the step ST12 that dormant state has wherein taken place.
If only imported at above-mentioned step ST13 and to have read request RRQ, in step ST28, increase to hang up number RH, then, process advances to step ST29.At step ST29, the quantity of read channel, for example, and 12, be configured to count value R.Then, at step ST30, export a counting opening flag CSF.Unless be provided with R=0 in step ST26, process advances to step ST30.Then, at step ST31, begin to increase the value of count value CH.Upwards counting is synchronous with memory clock CKm.
Next, at step ST32, determine whether to be provided with CH=1.If be provided with CH=1, read sign RFL what channel information was followed in step ST33 output, this channel information is corresponding to count value R, and to reading address location 304 and writing counter 306 and submit RFL (seeing Figure 26) to.Further, determine count value R at step ST33.After the processing of step ST33, process advances to step ST34.
At step ST34, determine whether to be provided with CH=MAX.If be provided with CH=MAX, in step ST35, stop upwards counting with CH=0.Then, at step ST36, determine whether count value W is 0.Unless be provided with W=0, it means to have imported to write in the read operation process asks WRQ, and this will be described later, and process turns back to the step ST17 that processing is write in execution therein.On the other hand, when in step ST36, being provided with W=0, handle turning back to step ST37.
In step ST37, determine whether count value R is 0.Unless be provided with R=0, process turns back to step ST30, and wherein process proceeds to the processing of reading that is used for next channel.On the other hand, when being provided with R=0, in step ST38, reducing to read and ask the hang-up of RRQ to count CH, because the read operation identical with read channel quantity is through with.
Next, determine in step ST39 whether hang-up value RH is 0.Unless be provided with RH=0, process turns back to step ST29, proceeds to the processing of reading of reading request RRQ corresponding to the next one of being hung up therein.On the other hand, when being provided with RH=0, process turns back to step ST=12, and dormant state has wherein taken place, because do not hang up any request RRQ that reads.
Unless in step ST34, be provided with CH=MAX, in step ST40, determine whether to have imported any request RRQ that reads.If imported any request RRQ that reads, in step ST41, increase the hang-up of reading request RRQ and count RH, and then, process proceeded to step ST42.Unless imported any request RRQ that reads in step ST40, process proceeds to step ST42 at once.Correspondingly, if in read operation, imported any request RRQ that reads, then hang up this request.
At step ST42, determine whether to have imported any request WRQ that writes.If imported any request WRQ that writes, the quantity 2 of write-channel is configured to count value W in step ST43.Unless in step ST42 or after the processing of step ST43, imported any request WRQ that writes, process turns back to step ST34.Correspondingly, if imported any request WRQ that writes in the read operation process, stop to read processing in step ST36, then, process proceeds to and writes processing.
Unless be provided with R=0 in step ST26, process proceeds to step ST30, and processing has taken place to read therein.Read request RRQ if when request WRQ has taken place to write, imported, if or in the read operation process, imported and write request WRQ, stop to read processing so, after write operation finished, process changes to again read processing.
As mentioned above, in the sdram controller 202 as shown in figure 25, read/write control module 307 is controlled about the write operation that writes request WRQ with about reading the read operation of request RRQ.In this case, greater than about reading the read operation of request RRQ, and regulate the execution that writes with read operation about the right of priority of the write operation that writes request WRQ by identical SDRAM bus 203.Correspondingly, as mentioned above, can read request RRQ, not consider to write the time of writing of request WRQ then, carry out read operation in each official hour input.
The right of priority that replaces writing request WRQ is greater than the right of priority of reading request RRQ, and reading request RRQ can have than writing the big right of priority of request WRQ.In that event,, might read RRQ, not consider to write the time of writing of request WRQ then, carry out read operation in each schedule time input owing to carry out the adjusting that write and read goes out operation by identical SDRAM bus 203.
As mentioned above, the quantity of write-channel be 2 and also the quantity of read channel be, for example, 12.Thereby, if the right of priority that writes request WRQ greater than the right of priority of reading request RRQ, with the stand-by period of reading of reading request RRQ be two channels at the most.Yet, if read the request RRQ right of priority greater than write the request WRQ right of priority, write the request WRQ write latency with the quantity with read channel is identical at the most, for example, 12 channels.
Synchronously generate with the horizontal-drive signal HDi of received image signal Sa and to write request WRQ.If this received image signal Sa is that for example, the reproducing signals of video recorder (VTR) at horizontal cycle deviation can take place.Yet as mentioned above, sdram controller 202 shown in Figure 25 can be read request RRQ in each official hour input, and it is read, and no matter write the time of writing of request WRQ.Thereby by using sdram controller 202 shown in Figure 25, the deviation that can subdue the horizontal cycle of received image signal Sa, and can omit time base corrector (TBC) circuit etc. and be used to subdue the device of this deviation.
Figure 30 A, B show the timing of received image signal Sa of SDRAM bus 203 and the example that data transmit condition.Figure 30 A shows received image signal Sa, emphatically the deviation of its horizontal cycle.Figure 30 B shows the data transfer state of SDRAM bus 203.In this example, the quantity of write-channel is 2, and the quantity of read channel is 8.Further, WD represents the data identical with the quantity of the channel that is used to write, and RD represents and be used to read the data of wanting channel quantity identical.
Next, return Fig. 1, will describe image signal processing unit 106 in more detail.
As mentioned above, rate conversion circuit 105 is exported a picture signal Sc, has wherein changed the quantity of the pixel on horizontal direction and the vertical direction.This picture signal Sc comprises brightness signal Y c and colour difference signal Uc, Vc.In this case, output is in 5 taps of 18 row signal * levels of the parallel stretching, extension of time orientation, vertical direction and horizontal direction, as brightness signal Y c.Similarly, as each colour difference signal Uc, Vc, export 5 taps of the 4 row signal * levels that stretch in time orientation, vertical direction and horizontal direction concurrently.
Image signal processing unit 106 is carried out the processing of brightness signal Y c and colour difference signal Uc, Vc independently.Yet these processing are similar.Thereby here, the processing of brightness signal Y c and colour difference signal Uc, Vc will be described as the processing of picture signal Sc.
Based on picture signal Sc from 105 outputs of rate conversion circuit, image signal processing unit 106 comprises a class tap extraction circuit 121, as the second data extract device, near the some projects of pixel data that are used to extract the target location that is positioned at picture signal Sb are as the class tap.According to this embodiment, the target location of mobile picture signal Sb is with raster.Then, rate conversion circuit 105 is corresponding to each target location, and output is positioned near some projects of the pixel data of target location.
In this case, in processing to brightness signal Y c, corresponding to each target location of picture signal Sb, predetermined some projects of extracting intensity data from the intensity data of 18 * 5=90 are as the class tap, and wherein this intensity data is to export from rate conversion circuit 105 concurrently.Similarly, in processing to each colour difference signal Uc, Vc, corresponding to each target location of picture signal Sb, predetermined some projects of extracting chromatism data from the chromatism data of 4 * 5=20 are as the class tap, and wherein this chromatism data is to export from rate conversion circuit 105 concurrently.
Image signal processing unit 106 comprises a class sorting circuit, is used to obtain a category code CL, such coded representation based on the class tap of being extracted, the class that the pixel data of the target location of picture signal Sb belongs to by class tap extraction circuit 121.By using any compression to handle, for example self-adaptation dynamic arrangement coding (ADRC), predictive coding (DPCM), vector quantization (VQ) etc. are carried out the class classification.
The situation of the ADRC that carries out the K position will be described below.In the ADRC of K position, detect dynamic range DR=MAX-MIN, and based on this dynamic range DR, quantize to be included in each pixel data in the class tap again, wherein this dynamic range DR is included in the maximal value of the pixel data in the class tap and the difference between the minimum value.
In other words, each pixel data as for being included in the class tap deducts minimum value MIN from pixel data, and this subtraction value is carried out subtraction (quantification) by DR/2K.Correspondingly, each pixel data that is included in the class tap is quantized to the K position again, and exports with predetermined tactic bit string as category code CL.
Thereby, in 1 ADRC, deduct minimum value MIN in each pixel data from be included in this class tap, and this subtraction value is carried out subtraction (quantification) by DR/2K.Correspondingly, each pixel data that is included in the class tap is quantized to 1 again, and exports with predetermined tactic bit string as category code CL.
Image signal processing unit 106 has ROM (read-only memory) (ROM) 123.The coefficient seed data of ROM 123 each class of storage.The prediction and calculation circuit 126 of an estimation, according to following estimate equation (1), from the pixel data y that pixel data xi and coefficient data Wi as prediction tapped obtain target location the picture signal Sb, wherein this prediction and calculation circuit 126 will be described later.
Wherein, " n " is the quantity as the pixel data xi of prediction tapped.
The coefficient seed data that is stored among the ROM 123 is the coefficient data of growth equation, and this growth equation is regulated information " f, g " as parameter with phase information " h, v " and picture quality, is used to generate the coefficient data w of above-mentioned estimate equation
i(i=1 is to n).An example of following equation (2) expression growth equation.Here, phase information " h " refers to the phase information of horizontal direction and phase information " v " refers to the phase information on the vertical direction.Further, picture quality is regulated information " f " and is referred to the picture quality adjusting information that is used to regulate resolution, and picture quality adjusting information " g " refers to the picture quality adjusting information that is used to regulate the squelch degree.ROM 123 is each class storage coefficient seed data W
I0-W
I30(i=1 is to n), as, for example, the coefficient data in the growth equation (2).The generation method of coefficient seed data will be described below.
W
i＝w
io+w
i1f+w
i2g+w
i3f
2+w
i4fg+w
i5g
2+w
i6f
3+w
i7f
2g
+w
i8fg
2+w
i9g
3+w
i10v+w
i11vf+w
i12vg
+w
i13vf
2+w
i14vfg+w
i15vg
2+w
i16h+w
i17hf
+w
i18hg+w
i19hf
2+w
i20hfg+w
i21hg
2+w
i22v
2
+w
i23v
2f+w
i24v
2g+w
i25vh+w
i26vhf
+w
i27vhg+w
i28h
2+w
i29h
2f+w
i30h
2g
(2)
Image signal processing unit 106 comprises a coefficient generating circuit 124, is used to generate coefficient data wi and obtains pixel data with the target location at picture signal Sb.This coefficient generating circuit 124 is read the coefficient seed data wi0-wi30 of the class that is shown by category code CL, described category code CL is obtained by class sorting circuit 122, coefficient generating circuit 124 also uses phase information " h, v " and picture quality to regulate information " f, g " and generates coefficient data Wi, phase information " h, v " is the phase information from the target location of the picture signal Sb of rate conversion circuit 105 outputs, and picture quality is regulated information " f, g " and submitted to from system controller 101 according to growth equation (2).
Here, phase information " h, v " is in the processing to brightness signal Y c, the phase information " phy, pvy " that obtains by the output TG217 (see figure 3) of rate conversion circuit 105, on the other hand, in the processing to colour difference signal Uc, Vc, phase information " h, v " is the phase information " phc, pvc " that the output TG217 (see figure 3) by rate conversion circuit 105 obtains.Owing to, exist the tap in the picture signal Sc system to set up circuit 221Y, 221C, thereby time deviation taken place in phase information " h, v " with between the picture signal Sc of rate conversion circuit 105 outputs.
Owing to this reason, though not shown, for example, in the system of phase information " h, v ", arranged the delay circuit that is used for the time adjusting.Because according to this embodiment, the output start delay that tap is set up among circuit 221Y, the 221C is fixed, and no matter the conversion magnification ratio of pixel quantity can use a fixing delay circuit.
Image signal processing unit 106 comprises that the prediction tapped as the first data extract device extracts circuit 125, be used for based on picture signal Sc from 105 outputs of rate conversion circuit, extraction is positioned near some projects of the pixel data the target location of received image signal Sb, as prediction tapped.
In this case, in processing,, extract predetermined some projects of intensity data in the intensity data of the 18 * 5=90 that from rate conversion circuit 105, exports concurrently, as prediction tapped corresponding to each target location of picture signal Sb to brightness signal Y c.Similarly, the time each colour difference signal Uc, Vc processing in, corresponding to each target location of picture signal Sb, extract predetermined some projects of chromatism data in the chromatism data of the 4 * 5=20 that from rate conversion circuit 105, exports concurrently, as prediction tapped.
Image signal processing unit 106 comprises that is estimated a prediction and calculation circuit 126.Estimate that prediction and calculation circuit 126 uses pixel data xi (i=1 is to n) and coefficient data Wi (i=1 is to n), the pixel data of the target location of computed image signal Sb, wherein, this pixel data xi extracts circuit 125 as prediction tapped by prediction tapped and extracts, and this coefficient data Wi generates in coefficient generating circuit 124 according to estimate equation (1).Estimate the prediction and calculation circuit 126 pixel data y of each target location of computed image signal Sb one by one, and it is outputed to outlet terminal 107.
Next, will the operation of image signal processing unit 106 be described.
Be submitted to class tap extraction circuit 121 from the picture signal Sc of rate conversion circuit 105 outputs.Some projects that such tap extraction circuit 121 extracts pixel data based on picture signal Sc are as the class tap, wherein this pixel data be arranged in picture signal Sb target location near.
The class tap that class tap extraction circuit 121 is extracted is submitted to class sorting circuit 122.122 pairs of such sorting circuits as some project implementations of the pixel data of class tap for example the compression of ADRC handle, with the category code CL of the class under the pixel data of the target location that obtains presentation video signal Sb.CL is submitted to coefficient generating circuit 124 with this category code.
To be submitted to prediction tapped from the picture signal Sc of rate conversion circuit 105 outputs and extract circuit 125.This prediction tapped extracts some projects that circuit 125 extracts pixel data based on picture signal Sc as prediction tapped, and wherein this pixel data is positioned near the target location of picture signal Sb.Pixel data xi as prediction tapped is submitted to estimation prediction and calculation circuit 126.Also estimate the coefficient data Wi that prediction and calculation circuit 126 is submitted to by coefficient generating circuit 124 generations to this.
Estimate prediction and calculation circuit 126 each target location corresponding to picture signal Sb, use by prediction tapped extract that circuit 125 extracted as the pixel data xi (i=1 is to n) of prediction tapped with according to this estimate equation, by the coefficient data Wi (i=1 is to n) that coefficient generation unit 124 generates, the pixel data y of the target location of computed image signal Sb.Estimate the prediction and calculation circuit 126 pixel data y of each target location of computed image signal Sb one by one by this, and it is outputed to outlet terminal 107.
The target of this image signal processing unit 106 is based on picture signal Sc, obtain pixel data y in each target location of picture signal Sb, and do not follow the processing of rate conversion, wherein this pixel data y exports from rate conversion circuit 105, and is converted into the ratio identical with picture signal Sb.Thereby, can construct this unit at an easy rate.
This image signal processing unit 106 uses some projects of pixel data, this pixel data be positioned at from rate conversion circuit 105 export concurrently corresponding near the specified target position of each target location of picture signal Sb, and can only use a door lock circuit, structure class tap extraction circuit 121 and prediction tapped extract circuit 125.Thereby, without any need for the equipment such as delay circuit that are used in time orientation, vertical direction and horizontal direction expansion.
As mentioned above, set up 5 taps of the level that circuit 221Y, 221C obtain by tap, it is corresponding to each location of pixels of the valid pixel part of brightness signal Y c and colour difference signal Uc, Vc, obtain in the arrangement of the brightness signal Y a that 5 taps of this level can be before rate conversion and the intensity data of colour difference signal Ua, Va and chromatism data, and do not rely on the magnification ratio of pixel count.Thereby, even changed the magnification ratio of pixel data, can not damage 5 taps of level and the relation between the phase information " h, v " yet, wherein this relation is based on the location of pixels of brightness signal Y a and colour difference signal Ua, Va, thereby image signal processing unit 106 can generate the pixel data on the target location among the picture signal Sb well.
As mentioned above, set up among circuit 221Y, the 221C in tap, the pixel data string of picture signal is transfused to the shift register of every row after the rate conversion, export the output start delay of 5 taps of level up to shift register, be fixed on clock time (no+ni), and do not rely on the magnification ratio of pixel quantity.Thereby, in image signal processing unit 106, can carry out in 5 taps of level and the time between the phase information " h, v " with a fixing delay circuit and regulate, thereby the magnification ratio that does not need to depend on pixel quantity changes the variable delay circuit of time delay.
Further, image signal processing unit 106 uses the phase information " h, v " of phase information " h, v " as the target location among the picture signal Sb, thereby without any need for the circuit that can generate this phase information " h, v ", wherein this phase information " h, v " is to obtain among the output TG217 in rate conversion circuit 105.
As mentioned above, the coefficient seed data wi0-wi30 (i=1 is to n) about each class is stored among the ROM 123.Generate the result of this coefficient seed data as primary learning.
At first, will the example of a generation method be described.Show an example below, be used for obtaining the coefficient seed data wi0-wi30 of the coefficient data of growth equation (2).
Here, for the explanation of back, definition tj (j=1 to 30) in equation (3).
T0＝1，t1＝f，t2＝g，t3＝f2，t4＝fg，t5＝g2，t6＝f3，t7＝f2g，t8＝fg2，t9＝g3，
t10＝v，t11＝vf，t12＝vg，t13＝vf2，t14＝vfg，t15＝vg2，t16＝h，t17＝hf，
t18＝hg，t19＝hf2，t20＝hfg，t21＝hg2，t22＝v2，t23＝v2f，t24＝v2g，
t25＝vh，t26＝vhf，t27＝vhg，t28＝h2，t29＝h2f，t30＝h2g
(3)
By using equation (3), equation (2) can be rewritten as equation (4).
At last, obtain unspecific coefficient wij by study.In other words, by using
Be used for the pixel data of student signal of each class and the pixel data of teacher signal, determined to minimize the coefficient of square error.This is based on a method for solving according to least squares approach.The quantity of supposing study is m, and (residue of the learning data of 1＜k＜m) is ek to k, and the sum of square error is E, uses equation (1) and equation (2) the formal representation E with equation (5).
Wherein, the i that xik has expressed at student's image estimates the k pixel data of tap position, and yk has expressed the k pixel data of corresponding teacher's image.
Method for solving according to least squares approach obtains wij, and wherein the part differential according to the equation (5) of wij is 0.This is expressed in the equation (6)
If as equation (7), (8), define Xipjq, Yip, can use matrix that equation (6) is rewritten as equation (9).
…(9)
Equation (9) is commonly called normal equations.According to this normal equations, (Gauss-Jordon's elimination method) comes wij is found the solution based on sweep-out method, with the design factor seed data.
Figure 31 shows the principle about the generation method of above-mentioned coefficient seed data, generates a SD signal (525i signal) as student signal from the HD signal (1050i signal) as teacher signal.The 525i signal means the interlacing type image signal with 525 row.The 1050i signal means the interlacing type image signal with 1050 row.
Figure 32 shows the relation between the location of pixels of 525i signal and 1050i signal.Here, represent the pixel of 525i signal a little louder, point is represented the pixel of 1050i signal.Further, represent location of pixels in the odd number zone, and dot the location of pixels in the even number zone with solid line.
By on vertical direction and horizontal direction 8 grades of the phase-shifts of SD signal, generate the SD signal of 8 * 8=64, SD1-SD64.Figure 33 shows on the vertical direction 8 grades phase-shifts state V1-V8.Here, the pixel pitch of SD signal vertical direction is 4096." o " represents the odd number zone and " e " expression even number zone.
The V1 state means that the shift amount of SD signal is 0, and in this case, the pixel of HD signal has the phase place 0,1024,2048,3072 with respect to the pixel of SD signal.The V2 state means that the shift amount of SD signal is 1, and in this case, the pixel of HD signal has the phase place 768,1792,2816,3840 with respect to the pixel of SD signal.The V3 state means that the shift amount of SD signal is 2, and in this case, the pixel of HD signal has the phase place 512,1536,2560,3584 with respect to the pixel of SD signal.The V4 state means that the shift amount of SD signal is 3, and in this case, the pixel of HD signal has the phase place 256,1280,2304,3328 with respect to the pixel of SD signal.
The V5 state means that the shift amount of SD signal is 4, and in this case, the pixel of HD signal has the phase place 0,1024,2048,3072 with respect to the pixel of SD signal.The V6 state means that the shift amount of SD signal is 5, and in this case, the pixel of HD signal has the phase place 768,1792,2816,3840 with respect to the pixel of SD signal.The V7 state means that the shift amount of SD signal is 6, and in this case, the pixel of HD signal has the phase place 512,1536,2560,3584 with respect to the pixel of SD signal.The V8 state means that the carry digit of SD signal is 7, and in this case, the pixel of HD signal has the phase place 256,1280,2304,3328 with respect to the pixel of SD signal.
Figure 34 shows on the horizontal direction 8 grades phase-shifts state H1-H8.Here, the pixel separation of SD signal level direction is 4096.
The H1 state means that the shift amount of SD signal is 0, and in this case, the pixel of HD signal has the phase place 0,2048 with respect to the pixel of SD signal.The H2 state means that the shift amount of SD signal is 1, and in this case, the pixel of HD signal has the phase place 1792,3840 with respect to the pixel of SD signal.The H3 state means that the shift amount of SD signal is 2, and in this case, the pixel of HD signal has the phase place 1536,3584 with respect to the pixel of SD signal.The H4 state means that the shift amount of SD signal is 3, and in this case, the pixel of HD signal has the phase place 1280,3328 with respect to the pixel of SD signal.
The H5 state means that the shift amount of SD signal is 4, and in this case, the pixel of HD signal has the phase place 1024,3072 with respect to the pixel of SD signal.The H6 state means that the shift amount of SD signal is 5, and in this case, the pixel of HD signal has the phase place 768,2816 with respect to the pixel of SD signal.The H7 state means that the shift amount of SD signal is 6, and in this case, the pixel of HD signal has the phase place 512,2560 with respect to the pixel of SD signal.The H8 state means that the shift amount of SD signal is 7, and in this case, the pixel of HD signal has the phase place 256,2304 with respect to the pixel of SD signal.
Figure 35 shows when the pixel of SD signal is placed on the center, by respectively being shifted 8 grades in vertical direction and horizontal direction, obtains the SD signal of 64 types, with the phase place of indication HD signal.In other words, with regard to the pixel of SD signal, the pixel of HD signal has the phase place that shows with the circle that has shade at same figure.
Here, as an example of phase-shifts, will explain the method for from an over-sampling wave filter, only extracting the phase place of wanting below.If regulate as above-mentioned picture quality, adopt resolution adjustment and squelch to regulate as an example, by changing the frequecy characteristic of over-sampling wave filter, can create student's image with different resolution.Student's image with different resolution has been arranged, can create coefficient, the effect that being used to of different coefficients improved resolution is also different.For example, if student's image of a high gloss and student's image of a low-luster are arranged, the student's image that has high gloss by study, can generate coefficient and have student's image of low-luster, can generate coefficient with the low effect that is used to improve ratio by study with the high effect that is used to improve resolution.
Further, by noise being applied to each student's image, can create the student's image that has been employed noise with different resolution.By changing the noisiness of using, can generate student's image, and the result is, has generated the coefficient with different noise suppression effects with different noisinesses.For example, if much noise has been arranged student's image applications to another student's image applications small amount of noise, can be employed student's image of much noise by study, establishment has the coefficient that strong noise suppresses effect, and can be employed student's image of small amount of noise by study, create and have the coefficient that low noise suppresses effect.
As for the noisiness of using, if shown in equation (10), the pixel value x using noise n by to student's image creates the pixel value x ' that this has used student's image of noise, regulates applied noisiness by changing G.
x′＝x+G·n (10)
Figure 36 shows the principle of final results of learning.Here, as an example, suppose that the frequecy characteristic with different over-sampling wave filters is categorized into 8 grades, and the noise application quantity also is categorized into 8 grades.Based on student's image of independent frequecy characteristic, create coefficient data by study, and further, be employed student's image of noise, create the coefficient data of regulating corresponding to squelch by study corresponding to resolution adjustment.Further, by study student image, create the coefficient seed data, this coefficient seed data is used for generating pixel corresponding to different phase places, and this student's image has independent frequecy characteristic and noise application quantity, has different phase places.
Figure 37 shows the configuration of coefficient seed data generating apparatus 150, and this device is used for generating the coefficient seed data according to above-mentioned principle.
Coefficient seed data generating apparatus 150 comprises an entry terminal 151, is used to receive HD signal (1050i) as teacher signal; A phase-shifts circuit 152A is used for extracting the phase place of wanting, to obtain SD signal (525i) by using the over-sampling wave filter with vertical direction in the horizontal direction; A noise adding circuit 152B is used for this SD signal is added noise.
Parameter " f " is used to specify the frequecy characteristic of over-sampling wave filter, and parameter " h, v " is used in the horizontal direction and vertical direction designated phase amount of displacement, with above-mentioned parameter input phase shift circuit 152A.Parameter " g " is used to specify noise increases ratio, and parameter " g " input noise is added circuit 152B.Here, parameter " f " is corresponding to the resolution adjustment information " f " in the image signal processing unit among Fig. 1 106.Parameter " h, v " is corresponding to the phase information in the image signal processing unit among Fig. 1 106 " h, v ".Parameter " g " correspondence is that the squelch degree in the image signal processing unit 106 is regulated information " g " among Fig. 1.
Coefficient seed data generating apparatus 150 comprises a class tap extraction circuit 154, is used for the SD signal exported based on noise adding circuit 152B, and some projects of extracting pixel data are as the class tap, and this pixel data is positioned near the target location of HD signal; And a class sorting circuit, be used for the category code CL that obtains expressing a class based on such tap, wherein, the pixel data of the target location in the HD signal belongs to such.
Further, coefficient seed data generating apparatus 150 comprises that also a prediction tapped extracts circuit 153, be used for the SD signal exported based on from noise adding circuit 152B, some projects of extracting pixel data are as prediction tapped, this pixel data be positioned at the HD signal the target location near.
Coefficient seed data generating apparatus 150 further comprises a normal equations generative circuit 160, is used to generate normal equations (square journey (9)), and this normal equations is used to obtain the coefficient seed data wi0-wi30 (i=1 is to n) of each class.Based on pixel data y from each target location of the HD signal of the HD signal extraction that will be transfused to entry terminal 151, extract the pixel data xi that circuit 153 is extracted corresponding to the pixel data y of each target location by prediction tapped as prediction tapped, the category code CL that obtains corresponding to the pixel data y of each target location and by class sorting circuit 157, be used to specify the parameter " f " of the frequecy characteristic of over-sampling wave filter, be used to specify the parameter " h; v of the phase-shifts amount of vertical direction " and based on the parameter that is used to specify the noise adding rate " g ", normal equations generative circuit 160 generates the coefficient seed data wi0-wi30 (i=1 is to n) that this normal equations is used to obtain each class.
In this case, by single and the n item of pixel data xi of packed-pixel data y, create the single project of learning data, as its prediction tapped of correspondence.Change the parameter " f, h, v " of phase-shifts counting circuit 152A one by one, and the parameter of noise adding circuit 152B " g ", so that generate the SD signal corresponding to the there.Correspondingly, normal equations generation unit 160 generates a normal equations, wherein writes down the project of many learning datas.By creating the SD signal one by one and writing down this learning data, pixel data, the squelch degree that can obtain being used to obtain to regulate about arbitrary resolution are regulated and the horizontal/vertical phase place.
Coefficient seed data generating apparatus 150 comprises a coefficient seed data determining unit 161, is used to receive the noise equation data by 160 generations of normal equations generation unit about each class; And, obtain being used for the coefficient seed data wi0-wi30 of each class by separating the normal equations of each class; And coefficient kind quantum memory 162, be used to store resulting coefficient seed data wi0-wi30.
To explain coefficient seed data generating apparatus 150 shown in Figure 37 below.
Import HD signals (1050i signal) as teacher signal to entry terminal 151.Corresponding to this HD signal, phase-shifts circuit 152A extracts the phase place of wanting by using the over-sampling wave filter with vertical direction in the horizontal direction, obtains the SD signal.In this case, be created in the SD signal that horizontal direction and vertical direction be displaced to 8 grades each one by one.
SD signal corresponding to each phase place, change parameter " f " and parameter " g " one by one, wherein, so that generate corresponding SD signal one by one, this parameter " f " will be imported into phase-shifts circuit 152A, and this parameter " g " will be imported into noise adding circuit 152B.
Class tap extraction circuit 154 extracts pixel data from each SD signal some projects are as the class tap, and wherein, this pixel data is positioned near the target location of HD signal, and this SD signal is exported from noise adding circuit 152B.The class tap is submitted to class sorting circuit 157.Class sorting circuit 157 is carried out squeeze operations, and for example as the ADRC on some projects of the pixel data of class tap, so that obtain category code CL, wherein this category code CL has expressed the class that pixel data was subordinate to of the target location of picture signal Sb.Submit this other sign indicating number CL of class to normal equations generation unit 160.
Further, prediction tapped extracts circuit 153, and extraction is as some projects of the pixel data of prediction tapped from each SD signal of noise adding circuit 152B output, and wherein this pixel data is arranged near the picture signal HD target location.To be submitted to normal equations generation unit 160 as the pixel data xi of this prediction tapped.
The HD signal wave that is input to entry terminal 151 is submitted to normal equations generation unit 160.The category code CL that obtains by class sorting circuit 157 based on some projects of extracting by prediction tapped that circuit 153 extracted from the pixel data y of each target location of the HD signal of HD signal extraction, corresponding to the pixel data y of each target location, corresponding to the pixel data y of each target location and based on parameter " f, h, v, g " as the pixel data xi of prediction tapped, normal equations generation unit 160 generates a normal equations, is used to obtain the coefficient seed data wi0-wi30 (i=1 is to n) about each class.
Find the solution normal equations by coefficient seed data determining unit 161, so that obtain the coefficient seed data wi0-wi30 of each class.Coefficient seed data wi0-wi30 is stored in the coefficient kind quantum memory 162 of dividing the address into each class.
Coefficient seed data generating apparatus 150 as shown in figure 37 can generate the coefficient seed data wi0-wi30 of each class among the ROM 123 that will store image signal processing unit shown in Figure 1 106 into.
The processing of image signal processing apparatus 100 shown in Figure 1 can use software to carry out by image signal processing apparatus shown in Figure 38 (computing machine) 500.When using software to carry out a series of processing, a program forming this software can be installed from the built-in computing machine of specialized hardware, also can this program be installed from a general purpose personal computer, by different types of program is installed, this general purpose personal computer can be carried out different types of function.
At first, will image signal processing apparatus 500 shown in Figure 38 be described.Image signal processing apparatus 500 comprises a CPU 501, is used to control the operation of whole device; A ROM (read-only memory) (ROM) 502 is used to store control program, coefficient seed data of CPU 501 etc.; A random access storage device (RAM) that has constituted the perform region of CPU 501.CPU 501, ROM 502, RAM 503 are connected respectively to bus 504.
Image signal processing apparatus 500 comprises a hard disk drive (HDD) 505, as external memory unit; With a driver 506, it operates movable storage medium 519, for example removable hard disk, read-only optical disc (CD-ROM), magnetooptics (MO) dish, Digital video disc (DVD), disk, semiconductor memory etc.Driver 505,506 is connected to bus 504 respectively.
Image signal processing apparatus 500 has a communication unit 508 that will be connected to communication network 507, and this communication network can be wired or wireless network.Communication unit 508 is connected to bus 504 by an interface 509.
Image signal processing apparatus 500 has a user interface section.This user interface section comprises a remote control signal receiving circuit 511, is used for from a remote control signal transmitter 510 receiving remote control signal RM; And the display 513 formed such as display 513 of forming by cathode ray tube (CRT), LCDs (LCD).Receiving circuit 511 is connected to bus 504 by interface 512, and display 513 is connected to bus 504 by interface 514.
Image signal processing apparatus 500 comprises an entry terminal 515, is used for received image signal Sa, and an outlet terminal 517, is used for output image signal Sb.Entry terminal 515 is connected to bus 504 by interface 516, and outlet terminal 517 is connected to bus 504 by interface 518.
For example, can pass through communication unit 508, from for example being communication network 507 download control programs of internet, and it is stored in hard disk drive 505 or RAM303 is medium to be used, rather than as above-described in ROM 502 storage control program etc.Further, can provide control program with the form of movable storage medium.
Can be with the form of movable storage medium, or by the communication network 507 download images signal Sas of communication unit 508 from for example internet, rather than the picture signal Sa that will handle by entry terminal 515 inputs.Further, can submit picture signal Sb after handling concurrently to display 513, and be stored in the hard disk drive 505, or by communication unit 508, sending it to for example is the communication network 507 of internet, rather than picture signal Sb is sent to outlet terminal 517.
Below with reference to the flow chart description among Figure 39, as the process that in image signal processing apparatus 500, is used for obtaining picture signal Sb shown in Figure 38 shows, this process from picture signal Sa.
At first,, begin this processing, and at step ST52, according to the quantity of predetermined frame or according to the quantity received image signal Sa of presumptive area at step ST51.After passing through entry terminal 515 received image signal Sa, picture signal Sa is stored among the RAM 503 temporarily.Further, if picture signal Sa is recorded in the hard disk drive 505, read picture signal Sa, and it is stored in RAM 503 temporarily from hard disk drive 505.Subsequently, at step ST53, determine whether that the processing of the picture signal Sa on entire frame or the whole zone is through with.When processing finished, this process finished in step ST54.On the other hand, be through with if not handle, process proceeds to step ST55.
At step ST55, the picture signal Sa that imports in step ST52 is carried out rate conversion handle, to generate picture signal Sc.In step ST52,, obtain phase information " h, v " corresponding to each pixel data of picture signal Sc.Then, at step ST56,, obtain picture quality equally and regulate information " f, g " based on user's operation.
Next, at step ST57, based on the picture signal Sc that generates among the step ST55, obtain the pixel data of class tap and prediction tapped, this pixel data is corresponding to the target location of picture signal Sb.Then, at step ST58, based on the class tap of extracting among the step ST57, generate the category code CL that expresses a class, wherein, the pixel data of picture signal Sb target location belongs to such.
Then, in step ST59, the coefficient seed data of the class of expressing by category code CL that use generates in step ST58, in step ST55, obtain regulate information " f, g " corresponding to the phase information " h, v " of the target location of picture signal Sb and according to the picture quality that above-mentioned equation (2) obtains in step ST56, generate the coefficient data Wi of an estimate equation, wherein, this equation is the pixel data that is used to obtain the target location of picture signal Sb.
Next,,, use the pixel data xi of coefficient data Wi that in step ST59, generates and a prediction tapped of conduct that in step ST57, extracts, generate the pixel data y of the target location of picture signal Sb according to estimate equation (1) at step ST60.
Next, at step ST61, determine whether the processing in each zone of the picture signal Sa that imports finishes in step ST52.If this processing finishes, process turns back to step ST52, wherein carries out the input of the picture signal Sa in predetermined frame or the presumptive area and handles.On the other hand, unless this processing is through with, process turns back to step ST57, wherein carries out a processing and is used to obtain pixel data y in the next target location of picture signal Sb.
According to processing, handle the picture signal Sa of input, so that obtain picture signal Sb along process flow diagram shown in Figure 39.
Though omitted the reproduction for the treatment of apparatus, the processing among Figure 37 in the coefficient seed data generating apparatus 150 can use software to realize.
With reference to the process flow diagram among Figure 40, the processing procedure that is used to generate the coefficient seed data is described below.
At first, in step ST71, begin processing, and in step ST72, phase shift place value of the SD signal that selection is used to learn (for example, stipulating) and picture quality regulated value (for example, stipulating) with parameter " f, g " with parameter " h, v ".Then, in step ST73, determine whether to finish study for all combinations of phase shift place value and picture quality regulated value.If there is not the study of end for all combinations, process proceeds to step ST74.
In step ST74,, import a known HD signal with the quantity in single frame or single zone.In step ST75, determine whether to finish for all frames or regional HD Signal Processing.If it is through with, process turns back to step ST72, selects next phase shift place value and picture quality regulated value therein, and repeats above-mentioned same processing.On the other hand, unless it is through with, process proceeds to step ST76.
In step ST76, the HD signal of importing from step ST74 generates a SD signal, wherein only this SD signal is carried out phase-shifts, and regulate the picture quality (with the form of resolution or noise) of this SD signal according to the picture quality regulated value according to the phase shift place value of in step ST72, selecting.Subsequently, at step ST77,, obtain the pixel data of class tap and prediction tapped in the SD signal that from step ST76, generates corresponding to the target location of HD signal.
Next, at step ST78, based on the class tap that obtains among the step ST77, generate the category code CL that has expressed a class, wherein, the pixel data of the target location of HD signal belongs to such.Use is at the pixel data of the target location of HD signal, and the pixel data of a prediction tapped of the conduct that obtains in step ST77 that is assumed that a project of learning data, carries out the addition that is used to obtain normal equations (square journey (9)).Carry out this addition based on the category code CL that is used for each class.
Next, at step ST80, the study that determines whether to finish in the entire domain of HD signal is handled, and this HD signal is imported in step ST74.Study is handled if be through with, and process turns back to step ST74, wherein according to the quantity or the single zone of next frame, imports the HD signal, and repeats above-mentioned same processing.On the other hand, be through with unless study is handled, process turns back to step ST77, wherein carries out the processing about next target location in the HD signal.
In step ST73, end is used for the study of the combination of all phase shift place values and picture quality regulated value, handles proceeding to step ST81.In step ST81, by finding the solution normal equations, calculate the coefficient seed data of each class, and in step ST82, the coefficient seed data is stored in the storer based on sweep-out method etc., then, and in step ST83, end process.
Processing by along as shown in figure 40 process flow diagram can obtain the coefficient seed data according to each class of a method, and wherein, the method among this method and Figure 37 in the coefficient seed data generating apparatus 150 is identical.
According to the foregoing description, in rate conversion circuit 105,, from frame memory 201, read the brightness signal Y a of 10 row corresponding to the single request RRQ that reads, and final, rate conversion unit 215Y exports the brightness signal Y c of 18 row concurrently.Further, from frame memory 201, read the colour difference signal Ua/Va of 2 row, and final, the blue difference signal Uc of rate conversion unit 215C output 4 row and the red color difference signal Vc of 4 row.
Yet corresponding to the single request RRQ that reads, the quantity of brightness signal Y a that should read from frame memory 201 and the row of colour difference signal Ua/Va is not limited to present embodiment.
For example, can consider to read the brightness signal Y a of 5 row and the colour difference signal Ua/Va of single file from frame memory 201 corresponding to the single request of reading RRQ.In this case, the still processing that postpones by row among rate conversion unit 215Y, the 215C, final, can obtain the brightness signal Y c of 18 row, the blue difference signal Uc of 4 row and the red color difference signal Vc of 4 row.
Figure 41 A shows the tap region of luminance signal, and represents 5 row 0-4 of not row delay with white circle, and represents to have row to postpone 13 row 5-17 with the band shaded circles.In this case, with row 10 as the center.Figure 41 B shows the example of the tap region of colour difference signal, and represents not have the delegation 0 that postpones with white circle, and the 3 capable 1-3 that delay is arranged that represent with the circle of band shade.In this case, with row 1 as the center.
For example, can consider to read request RRQ, read the brightness signal Y a that is used for 4 row and be used for the 2 colour difference signal Ua/Va that go from frame memory 201 corresponding to one.In this case, by being used for the processing that row postpones among rate conversion unit 215Y, the 215C, finally, can obtain to obtain being used for the brightness signal Y c of 14 row and being used for the blue difference signal Uc of 8 row and being used for the 8 red color difference signal Vc that go.
Figure 42 A shows an example of the tap region of luminance signal, and the 4 row 0-3 that represented by white circle represent not go the row that postpones, and represent to have the row of row delay with the 10 row 4-13 that the circle of band shade is represented.In this case, regard row 8 as center.Figure 42 B shows an example of the tap region of colour difference signal, represents not go the row that postpones with 2 row 0,1 that white circle is represented, and represents to have the row of row delay with the 6 row 2-7 that the circle of band shade is represented.In this case, regard row 3 as center.
Though according to the foregoing description, show a situation, the tap in the rate conversion circuit 105 is therein set up circuit 221Y, 221C and has been set up 5 taps in the horizontal direction, and the quantity of tap is not limited to present embodiment.Further, can provide luminance signal and colour difference signal with varying number tap.
In the above-described embodiments, explained a situation, the coefficient seed data is stored in ROM123 therein, and coefficient generating circuit 124 uses the coefficient seed data in the class that category code CL represent, according to the growth equation of having explained (2), regulate information " f, g " corresponding to phase information " h, v " and picture quality, generate coefficient data Wi.Yet, the coefficient data Wi of each class can be stored in ROM 123, this coefficient data Wi is the combination of regulating information " f, g " about all phase informations " h, v " and picture quality, and can read coefficient data Wi corresponding to phase information " h, v " and picture quality adjusting information " f, g " in the expressed class of the category code CL that will use.
In this case, the coefficient data Wi that phase information " h, v " and picture quality are regulated each combination of information " f, g " is stored in the storage medium 135, and can obtain this data by study SD signal, wherein, this SD signal is to obtain according to the combination by each parameter " f, g, h, v ".
In the above-described embodiment, show a situation, ought obtain picture signal Sc from picture signal Sa in this case, and, in the time of reading out the quality that increases pixel by twice, increase the quantity of pixel at rate conversion unit 215Y, 215C.Yet according to the form of picture signal Sa and picture signal Sc, in rate conversion, the quantity of pixel can reduce.In this case, in rate conversion unit 215Y, 215C, reduce the quantity of pixel by refinement.
In the above-described embodiment, show a situation, use image signal processing unit 106 in this case, from the picture signal Sc that stretches in time orientation, vertical direction and horizontal direction, extract class tap and prediction tapped and use, wherein, this picture signal Sc is from 105 outputs of rate conversion circuit.Yet, set up circuit 221Y, 221C for the tap of rate conversion circuit 105, allow to provide a tap that is used to obtain the class tap to set up circuit, and a tap that is used to obtain prediction tapped sets up circuit, so that rate conversion circuit 105 can directly be exported the class tap and the prediction tapped that will use in image signal processing unit 106.In this case, provide class tap extraction circuit 121 or prediction tapped to extract circuit 125 need for image signal processing unit 106.
Though in the above-described embodiment, narrated the use of conduct about the linear equation of the estimate equation of the pixel data of generation picture signal Sb,, the present invention is not limited to this embodiment, for example, allows to use a senior equation as estimate equation.
Though in the above-described embodiments, show a situation, detection type code CL in this case, and in estimate equation, use coefficient data Wi corresponding to this category code CL, can consider to omit the detecting unit of category code CL.In this case, unique space of coefficient seed data is stored among the ROM 123.
According to an aspect of the present invention, a received image signal is stored in first memory temporarily, and one by one with behavior unit, be sent to second memory from first memory, and write wherein, pixel period after conversion and line period are read picture signal from second memory then, to obtain output image signal.In this case, the transmission of control chart image signal from the first memory to the second memory is so that can carry out this transmission at each official hour.Correspondingly, can guarantee stable data travelling belt between first memory and the second memory, thereby improve its service efficiency.
According to a further aspect in the invention, first control writes request based on one, pass through data bus, be stored in this storer from write buffer transmitted image signal to a storer and with picture signal, second control is based on the request of reading, by this data bus, this picture signal is sent to sense buffer and picture signal is stored in the sense buffer from this storer, the right of priority of one of them control is greater than another, carries out writing or the adjusting of read operation by identical data bus so that can be in a good state.Correspondingly, can carry out read operation based on the request of reading of each official hour input, and not rely on the time of writing of the request of writing.
According to another aspect of the present invention, greater than the control of reading, and can read request, generate a stand-by period that is used for read operation based on this based on the request of reading based on the right of priority of writing control that writes request.Yet if write request corresponding to one, the n picture signal of single horizontal cycle is written into storer corresponding to the single request of reading, and (m＞n) read from storer, maximum latency is n to the m picture signal of single horizontal cycle.Correspondingly, this based on the right of priority of reading control of the request of reading greater than under based on the situation of writing control that writes request, shorter than being used for based on a maximum latency (for m) that writes the write operation of request.
According to another aspect of the present invention, by using the converting objects pixel data string of first picture signal, so that magnification ratio corresponding to pixel count, constantly by the pixel data that rate process is identical, generate the suitable pixel data string of the valid pixel part of the second image signal level direction, and will be submitted to shift register by revising the amended pixel data string that this pixel data string that is fit to obtains, and use displacement to trigger, the pixel data that will revise the change position of back pixel data string one by one is sent to shift register.Correspondingly, valid pixel part corresponding to the second image signal level direction, set up the tap of specific quantity in the horizontal direction, and pass through the change position of the pixel data of the suitable pixel data string of modification, obtain amended pixel data string, so that make centre tapped change meet the arrangement of suitable pixel data string.
Correspondingly, according to the present invention, can before rate conversion, obtain the tap of the predetermined quantity of the horizontal direction that the pixel data of picture signal (first picture signal) arranges, and not depend on the magnification ratio of pixel quantity.If thereby according to phase information based on the location of pixels of the picture signal before the rate conversion, the tap of predetermined quantity on the usage level direction, generate the pixel data of the target location of output image signal, even the magnification ratio of pixel has changed, the tap of predetermined quantity and the corresponding relation between the phase information can be not destroyed on the horizontal direction, so that can produce the pixel data of the target location of output image signal under a good state.
According to a further aspect of the present invention, when output terminal and the input end of shift register at the register of an output center tap, when the individual register of " no " individual register and " ni " is arranged respectively, (no+ni) the individual pixel data at first that can see the after image prime number certificate that makes an amendment changes constantly, so that constantly (no+hi) individual pixel data is at first put into shift register at every row.
Correspondingly, according to the present invention, import this shift register at each row from the pixel data string of a picture signal that will be after rate conversion, start delay up to the tap of predetermined quantity on this register output horizontal direction can be fixed on the individual clock time of every row (no+hi), and does not rely on the enlargement factor of pixel quantity.If thereby based on the phase information of the target location of output image signal, the tap of the predetermined quantity of usage level direction, generate the pixel of the target location of output image signal, there is no need to provide any variable delay circuit, the tap and the time between the phase information that are used for predetermined quantity on the horizontal direction are regulated, wherein, this variable delay circuit can change time delay according to the magnification ratio of pixel quantity.
According to the present invention, the transmission of the picture signal of control from the first memory to the second memory makes it carry out at each official hour, thereby has guaranteed that the stable data travelling belt is logical between first memory and the second memory, to improve service efficiency.Application purpose of the present invention can be by interim storage received image signal in first memory, picture signal is sent to second memory with behavior unit one by one and writes wherein from first memory, and the pixel period after conversion and line period read picture signal from second memory, obtains output image signal.
According to the present invention, can waltz through same data bus and carry out and to write and read operation, read so that carry out, and do not rely on time of writing of the request of writing based on the input of the request of reading of each official hour.Application target of the present invention can be by interim storage received image signal in first memory, picture signal is sent to second memory with behavior unit one by one and writes wherein from first memory, and the pixel period after conversion and line period read picture signal from second memory, obtains output image signal.
According to the present invention, can be before rate conversion in the arrangement of the pixel data of picture signal, obtain the tap of predetermined quantity on the horizontal direction, and do not rely on the magnification ratio of pixel data.Thereby, application purpose of the present invention can be the tap by the predetermined quantity of horizontal direction before the usage rate conversion, obtain the tap of predetermined quantity in the horizontal direction, to create new pixel data, it is corresponding to each location of pixels of the valid pixel part of the horizontal direction of output image signal.
The present invention includes the relevant flesh and blood of submitting in Jap.P. office with on August 19th, 2003 of the Japanese patent application that is numbered JP2003-295511, JP2003-295512, JP2003-295513, quote its full content as a reference at this.
Though aforesaid instructions has been described the preferred embodiments of the present invention, those skilled in the art can make many changes to preferred embodiment not deviating under the situation of the present invention aspect main.Thereby additional claim is intended to cover all such changes that drop on true scope of the present invention and spirit.
Claims (11)
1. a memory controller is used to control the storer that writes and read view data by identical data bus therein, and described memory controller comprises:
Write buffer is used for storing received image signal temporarily, so that this picture signal is write described storer;
Sense buffer is used for the output image signal that interim storage is read from described storer;
Write scalar/vector, be used to generate the address that writes of described storer;
Read scalar/vector, be used to generate the address of reading of described storer; And
Write/read-out control unit, be used for based on the request of when the received image signal of predetermined quantity is stored in the said write impact damper, submitting to of reading that writes request and submit at every turn at each official hour, control said write impact damper, described sense buffer, said write scalar/vector and the described scalar/vector of reading, and
Wherein, first control is based on the said write request, control is sent to received image signal described storer and stores this received image signal therein from the said write impact damper by data bus, second control is read request based on described, control is sent to this output image signal described sense buffer and stores this output image signal therein from described storer by described data bus, and described control module is given in these two controls any with a right of priority greater than another one.
2. memory controller as claimed in claim 1, wherein said control module are given the right of priority of described first control greater than described second control.
3. memory controller as claimed in claim 2, when submitting said write request and described when reading request simultaneously to, described control module writes the execution of request control to the write operation of described storer based on this, hang up this request of reading and behind the said write EO, from described storer, read this picture signal based on the request of reading of this hang-up.
4. memory controller as claimed in claim 2, the request of wherein ought describedly reading is what to submit in the process that writes to described storer, described control module is hung up this request of reading and behind the said write EO, is read picture signal based on the request of being hung up of reading from described storer.
5. memory controller as claimed in claim 1, wherein working as the said write request is to submit to the process of reading from described storer, described control module stops described read operation temporarily, write request based on this, the operation that described storer is write is carried out in control, and after write operation finishes, read the remainder of the read operation that stops.
6. memory controller as claimed in claim 1, wherein said storer are burst transmissions type frame memories.
7. memory controller as claimed in claim 1, wherein said storer are that SDRAM and described memory controller refresh at the vertical blank periodic unit.
8. memory controller as claimed in claim 1, wherein corresponding to the said write request, the n of a horizontal cycle picture signal (n is an integer) is stored in the described storer, and corresponding to described read the request horizontal cycle m picture signal (m is an integer, m＞n) read from described storer.
9. memory controller is used to control one and writes and read the storer of view data therein by identical data bus, and described memory controller comprises:
Write buffer is used for storing received image signal temporarily, so that this picture signal is write described storer;
Sense buffer is used for the output image signal that interim storage is read from described reservoir;
Write address generating device, be used to generate the address that writes of described storer;
Read address generating device, be used to generate the address of reading of described storer; And
Control device, be used for based on the request of when the received image signal of predetermined quantity is stored in this write buffer, submitting to of reading that writes request and submit at every turn at each official hour, control said write impact damper, described sense buffer, said write scalar/vector and the described scalar/vector of reading, and
Wherein, first control is based on the said write request, control is sent to received image signal described storer and stores this received image signal therein from the said write impact damper by data bus, second control is read request based on described, control is sent to this output image signal described sense buffer and stores this output image signal therein from described storer by described data bus, and described control module is given in these two controls any with a right of priority greater than another one.
10. memory control methods comprises:
First controlled step when the picture signal of predetermined quantity is stored in this write buffer, based on the request that writes of each submission, by data bus, is sent to storer with this picture signal from this write buffer, and writes this picture signal therein; And
Second controlled step, the request of reading based on each official hour is submitted to is sent to this sense buffer with this picture signal from described storer by described data bus, and writes this picture signal therein,
Wherein, be performed with a right of priority based on described first controlled step of said write request with based in described described second controlled step of reading request any greater than another one.
11. memory control methods as claimed in claim 10, wherein said first controlled step is performed with a right of priority greater than described second controlled step.
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| JP295511/2003 | 2003-08-19 | ||
| JP295512/2003 | 2003-08-19 | ||
| JP2003295511A JP4661036B2 (en) | 2003-08-19 | 2003-08-19 | Memory controller, memory control method, and program for executing the method |
| JP295513/2003 | 2003-08-19 |
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| CNB2004100822271A Division CN100435579C (en) | 2003-08-19 | 2004-08-19 | Memory controller, memory control method, rate conversion apparatus, rate conversion method, image-signal-processing apparatus, image-signal-processing method |
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| CN101079230A true CN101079230A (en) | 2007-11-28 |
| CN100587771C CN100587771C (en) | 2010-02-03 |
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2004
- 2004-08-19 CN CN200710126243A patent/CN100587771C/en not_active Expired - Fee Related
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104603867A (en) * | 2012-09-07 | 2015-05-06 | 夏普株式会社 | Memory control device, mobile terminal, memory control program, and computer-readable recording medium |
| CN104603867B (en) * | 2012-09-07 | 2016-08-17 | 夏普株式会社 | Storage control device and portable terminal device |
| CN103716555B (en) * | 2012-10-02 | 2017-04-12 | 株式会社索思未来 | Device and method for processing image, and imaging device |
| US9762776B2 (en) | 2012-10-02 | 2017-09-12 | Socionext, Inc. | Device and method for resizing image, and imaging device |
| CN106201363A (en) * | 2016-07-26 | 2016-12-07 | 四川大学 | The memorizer of the random real time access of video flowing Pixel-level data and storage method |
Also Published As
| Publication number | Publication date |
|---|---|
| JP4661036B2 (en) | 2011-03-30 |
| CN100587771C (en) | 2010-02-03 |
| JP2005062693A (en) | 2005-03-10 |
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