CN101075481A - Shift register and its signal generator - Google Patents
Shift register and its signal generator Download PDFInfo
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- CN101075481A CN101075481A CN 200610084614 CN200610084614A CN101075481A CN 101075481 A CN101075481 A CN 101075481A CN 200610084614 CN200610084614 CN 200610084614 CN 200610084614 A CN200610084614 A CN 200610084614A CN 101075481 A CN101075481 A CN 101075481A
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Abstract
A shift register consists of the first switch formed by the first output end, the first control end and the first output end; transistor formed by grid, the first source electrode/drain electrode and the second source electrode/drain electrode; controlled switch formed by the first controlled input end, the second controlled input end, switch control end and the second switch; the second switch formed by the second input end, the second control end and the second output end.
Description
Technical field
The invention relates to a kind of shift register and signal generator thereof, and particularly relevant for a kind of shift register and signal generator thereof of avoiding signal output part suspension joint (Floating).
Background technology
Figure 1A is the shift-register circuit structural drawing of the scanner driver of known United States Patent (USP) notification number 20040174189.Please refer to Figure 1A, shift register 100 comprises three N type metal oxide semiconductors (N-type Meta Oxide Semiconductor, NMOS) 101,102 and 103 and electric capacity 104 of field-effect transistor.The drain electrode of first transistor 101 is to be coupled to input signal IN, and the grid of transistor 101 is accepted the control of clock signal C KA, and the source electrode of transistor 101 is in order to output control signal C1.The drain electrode of second transistor 102 is to be coupled to clock signal C KB, and the grid of transistor 102 is accepted the control of control signal C1, and the source electrode of transistor 102 is in order to export an output signal OUT.In addition, the drain electrode of the 3rd transistor 103 is the source electrodes that are coupled to transistor 102, the source electrode of transistor 103 is to be coupled to voltage VSS, and the grid of transistor 103 controlled by clock signal C KA, and wherein clock signal C KB is the inversion signal of clock signal C KA.Electric capacity 104 is coupled between the source electrode and grid of transistor 102.
Please be simultaneously with reference to Figure 1B, it illustrates the coherent signal sequential chart of Figure 1A shift register 100.Shown in Figure 1B, in the first clock period T1, input signal IN has VSS level (for example being 0V), and clock signal C KA and CKB have VDD (for example being 9V) and VSS level respectively.This moment, transistor 101 conductings made control signal C1 have (VDD-Vt) level, and wherein Vt is starting potential (Threshold Voltage) value of transistor 101.Simultaneously, clock signal C KA is turn-on transistor 103 also, makes output signal OUT have the VSS level, and also conducting of transistor 102.At this moment, electric capacity 104 is chargings and store the cross-pressure of (VDD-Vt-VSS).Then, in second clock period T 2, input signal IN has the VDD level, and clock signal C KA and CKB have VSS and VDD level respectively.At this moment, transistor 101 not conductings.Clock signal C KB to the VDD level, improves the source voltage (P point voltage) of transistor 102 by the VSS electrical level rising simultaneously.So by the cross-pressure of electric capacity 104, the grid voltage of transistor 102 also rises, and makes transistor 102 be higher than the source voltage conducting because of grid voltage thereupon.Yet, because clock signal C KA has the VSS level, cause transistor 103 not conductings, make the drain electrode of transistor 103, that is the signal output part P floating of can having an opportunity to occur.
Next, in the 3rd clock period, input signal IN has the VSS level, and clock signal C KA and CKB have VSS and VDD level.As above-mentioned, transistor 101 and 103 neither conductings make signal output part P floating can occur equally.When signal output part P is in floating, the scanning-line signal of scanner driver just is controlled the interference of voltage Vcom and data line signal easily, and cause sweep trace output signal shakiness, influence follow-up pixel voltage, and then the phenomenon that causes display image to glimmer, reduce picture quality.
Summary of the invention
In view of this, purpose of the present invention is exactly at shift register that a kind of novelty is provided and signal generator thereof.Between above-mentioned the 3rd transistorized grid and second transistorized grid, add the controlled switch element, make when the 3rd not conducting of transistor, this controlled switch element conductive, caused the image flicker phenomenon to avoid signal output part to be in floating, and then improved the picture quality of display.
According to purpose of the present invention, a kind of shift register is proposed, in order to receiving inputted signal, and export an output signal according to this.Shift register comprises first switch, transistor, controlled switch element and second switch.First switch comprises first input end, first control end and first output terminal.First input end is coupled to input signal, and first control end is coupled to first clock signal.Transistor has grid, first source/drain and second source/drain.Grid is coupled to first output terminal, and first source/drain is coupled to the second clock signal.The controlled switch element comprises first controlled input end, second controlled input end, switch control end and second switch.First controlled input end is coupled to the 3rd clock signal.Second controlled input end is coupled to first voltage, and the switch control end is coupled to first output terminal.Second switch comprises second input end, second control end and second output terminal.Second input end is coupled to first voltage, and second control end is coupled to controlled output terminal, and second output terminal is coupled to transistorized second source/drain, in order to export this output signal.
Wherein first clock signal is controlled first switch conduction, and the output input signal, makes controlled switch element conductive, the 3rd clock signal make controlled output terminal export second voltage, and the conducting of control second switch, and output signal level is first voltage;
Wherein first clock signal is controlled the first not conducting of switch, the level of second clock signal buck first output terminal, make transistor turns, output signal is the second clock signal, the level of first output terminal changes simultaneously, make controlled switch element conductive, the 3rd clock signal make controlled output terminal export first voltage, and the not conducting of control second switch.
According to purpose of the present invention, a kind of signal generator is proposed, comprise multi-stage shift register.Shift registers at different levels are in order to receiving the input signal from the upper level shift register, and export an output signal according to this.Shift registers at different levels comprise first switch, transistor, controlled switch element and second switch.First switch comprises first input end, first control end and first output terminal.First input end is coupled to input signal, and first control end is coupled to first clock signal.Transistor has grid, first source/drain and second source/drain.Grid is coupled to first output terminal, and first source/drain is coupled to the second clock signal.The controlled switch element comprises first controlled input end, second controlled input end, switch control end and second switch.First controlled input end is coupled to the 3rd clock signal.Second controlled input end is coupled to first voltage, and the switch control end is coupled to first output terminal.Second switch comprises second input end, second control end and second output terminal.Second input end is coupled to first voltage, and second control end is coupled to controlled output terminal, and second output terminal is coupled to transistorized second source/drain, in order to export this output signal.
Wherein first clock signal is controlled first switch conduction, and the output input signal, makes controlled switch element conductive, the 3rd clock signal make controlled output terminal export second voltage, and the conducting of control second switch, and output signal level is first voltage;
Wherein first clock signal is controlled the first not conducting of switch, the level of second clock signal buck first output terminal, make transistor turns, output signal is the second clock signal, the level of first output terminal changes simultaneously, make controlled switch element conductive, the 3rd clock signal make controlled output terminal export first voltage, and the not conducting of control second switch.
According to purpose of the present invention, a kind of shift register is proposed, comprise the first transistor, transistor seconds, the 3rd transistor, the 4th transistor and the 5th transistor.The source electrode receiving inputted signal of the first transistor, and the grid of the first transistor receives first clock signal.The grid of transistor seconds couples the drain electrode of the first transistor, and the source electrode of transistor seconds receives the second clock signal, and an output signal is exported in the drain electrode of transistor seconds.The 3rd transistor drain couples the source electrode of transistor seconds, and the 3rd transistorized source electrode receives reference voltage.The 4th transistorized grid and drain electrode couple first clock signal, and the 4th transistorized source electrode couples the 3rd transistorized grid.The 5th transistor drain couples the 4th transistorized source electrode, and the 5th transistorized source electrode receives reference voltage, and the 5th transistorized grid couples the grid of transistor seconds.
For above-mentioned purpose of the present invention, feature and advantage can be become apparent, a preferred embodiment cited below particularly, and cooperate appended graphicly, be described in detail below:
Description of drawings
Figure 1A is the shift-register circuit structural drawing of the scanner driver of known United States Patent (USP) notification number 20040174189.
Figure 1B illustrates the coherent signal sequential chart of Figure 1A shift register.
Fig. 2 illustrates a kind of signal generator circuit block diagram according to a preferred embodiment of the present invention.
Fig. 3 illustrates the circuit structure diagram of shift register among Fig. 2.
Fig. 4 illustrates shift register coherent signal sequential chart among Fig. 2.
Fig. 5 A～5C illustrates shift register each transistorized on off state synoptic diagram in period 1～period 3 among Fig. 2 respectively.
[main element label declaration]
1: grid
2: source electrode
3: drain electrode
100,210: shift register
101,102,103: transistor
104: electric capacity
200: signal generator
201,202,203,204,205: transistor
Embodiment
Please refer to Fig. 2, it illustrates a kind of signal generator circuit block diagram according to a preferred embodiment of the present invention.Signal generator 200 for example is the scanner driver of display, and it comprises multi-stage shift register 210.Shift registers 210 at different levels in order to receive input signal IN from upper level shift register 210 (STV, OUT1 ...), and export according to this an output signal OUT (OUT1, OUT2 ...), wherein first order shift register 210 receives start signal STV.
Please be simultaneously with reference to Fig. 3, it illustrates the circuit structure diagram of shift register 210 among Fig. 2.Shift registers 210 at different levels comprise nmos pass transistor 201,202,203,204 and 205.The drain electrode of transistor 201 (3) is coupled to input signal IN, and the grid of transistor 201 (1) is coupled to the first clock signal C KA.The grid of transistor 202 (1) is coupled to the source electrode (2) (or node A0) of transistor 201, and the drain electrode of transistor 202 (3) is coupled to second clock signal CKB.Transistor 204 is for diode couples transistor, and its grid (1) and drain electrode (3) couple end and be anode (+), and its source electrode (2) is a negative terminal (-).The anode (+) of transistor 204 is coupled to the first clock signal C KA.The source electrode of transistor 205 (2) is coupled to the first voltage VSS, for example be-6～-7V, the grid of transistor 205 (1) is coupled to the source electrode (2) of transistor 201, and the drain electrode of transistor 205 (3) is coupled to the negative terminal (-) (or node A1) of transistor 204.In addition, the source electrode of transistor 203 (2) is coupled to the first voltage VSS, and the grid of transistor 203 (1) is coupled to the drain electrode (3) of transistor 205, and the drain electrode of transistor 203 (3) is coupled to the source electrode (2) of transistor 202, in order to output signal output OUT.
It should be noted that as shown in Figure 2 second clock signal CKB (CK3 or CK4) is the inversion signal of the first clock signal C KA (CK1 or CK2).And the first clock signal C KA of arbitrary grade of shift register 210 (=CK1) or second clock signal CKB (=CK3) phase place be with the first clock signal C KA of next stage shift register 210 (=CK2) or second clock signal CKB (=CK4) 1/4 clock period of phasic difference (T/4) mutually.
Fig. 4 illustrates shift register 210 coherent signal sequential charts among Fig. 2, and Fig. 5 A～5C be illustrate respectively shift register 210 among Fig. 2 in the period 1～period 3 T1～T3 in the on off state synoptic diagram of transistor 201～205.Please be simultaneously with reference to Fig. 4 and Fig. 5 A, in period 1 T1 (T1=T/4), the input signal IN and the first clock signal C KA have VDD level (for example being 20V), make the source electrode (A0 voltage) of transistor 201 conductings and transistor 201 have (VDD-Vt) level, wherein Vt is the starting potential value of transistor 201.Simultaneously the grid voltage (=A0 voltage) of transistor 205 for (VDD-Vt) (being about 20V-2.5V=17.5V) be the source voltage VSS that is higher than transistor 205 (be about-6～-7V), so transistor 205 conductings.Because the drain voltage (A1 voltage) of transistor 205, that is the negative terminal voltage of transistor 204 is determined by the bias voltage of transistor 204, so the drain voltage of transistor 205 can be higher than its source voltage VSS and be lower than the positive terminal voltage VDD of transistor 204.At this moment, the grid voltage of transistor 203 (=A1 voltage) is the source voltage VSS that is higher than transistor 203, so transistor 203 conductings, and output signal OUT exports the first voltage VSS.
Please be simultaneously with reference to Fig. 4 and Fig. 5 B, the person of connecing is in T2 second round (T2=T/4), and input signal IN and second clock signal CKB have the VDD level, and the first clock signal C KA has the VSS level, make transistor 201 not conductings.At this moment, because the grid source electrode stray capacitance Cgs of transistor 202 had stored the cross-pressure of (VDD-Vt-VSS) in last one-period, when second clock signal CKB changes into the VDD level by the VSS level, the source voltage of transistor 202 can be drawn high thereupon, and improve the grid voltage (A0 voltage) of transistor 202 via capacitor C gs, make transistor 202 complete conductings, and output signal OUT has the VDD level.Last A0 voltage is to draw high to (2*VDD-Vt-VSS).Simultaneously, the grid voltage of transistor 205 (=A0 voltage) be (2*VDD-Vt-VSS) (～2*20V-2.5V-(and 6V)=43.5V) be the source voltage VSS that is higher than transistor 205 (be about-6～-7V), therefore transistor 204 conductings, A1 voltage is VSS, and transistor 203 not conductings.Thus, the drain electrode of transistor 203 (being signal output part) just can be coupled to the first voltage VSS via stray capacitance Cgs, the node A0 of transistor 202 and form current path, the floating of the signal output part that produced when avoiding transistor 103 not conductings in the prior art.
Please be simultaneously with reference to Fig. 4 and Fig. 5 C, then in period 3 T3 (T3=T/4), the input signal IN and the first clock signal C KA have the VSS level, and second clock signal CKB has the VDD level, make transistor 201 still not conductings.A0 voltage still remains on the level of (2*VDD-Vt-VSS), and transistor 202 conductings, makes output signal OUT have the VDD level of this second clock signal CKB.Similarly, transistor 205 conductings, and A1 voltage at this moment are the VSS level, and then make transistor 203 not conductings.The drain electrode of transistor 203 (being signal output part) can be coupled to the first voltage VSS via stray capacitance Cgs, the node A0 of transistor 202 equally and form current path, the floating of the signal output part that produced when avoiding transistor 103 not conductings in the prior art.Therefore, according to shift register 210 of the present invention, the phase place of input signal IN can be delayed 1/4 clock period (T/4).
It should be noted that, when the output signal OUT of arbitrary grade of shift register 210 inputs to next stage shift register 210, because output signal OUT is to delay the T/4 time compared to input signal IN, simultaneously the first clock signal C KA of next stage shift register 210 (=CK2) and second clock signal CKB (=CK4) also respectively than the first clock signal C KA of this grade shift register 210 (=CK1) and second clock signal CKB (CK3) delay the T/4 time.Therefore, it is the sequential level variation unanimity of level shift register 210 fully therewith that the sequential level of input signal IN, the clock signal C KA of next stage shift register 210 and CKB and output signal OUT changes, and similarly the phase place of input signal IN can be delayed T/4.
As mentioned above, be that example explains though the present invention has nmos pass transistor 201～205 with shift register 210, right shift register 210 of the present invention also can be to use the PMOS transistor to reach.Perhaps transistor 201,203 and 205 also can be to use other on-off element to reach, and for example is to be respectively first switch, second switch and the 3rd switch.Perhaps in addition transistor 204 and 205 also can be the controlled switch element of other circuit structure, comprise first controlled input end that couples the 3rd clock signal, second controlled input end that couples the first voltage VSS, the controlled output terminal that couples the switch control end of first output switching terminal and be coupled to the second switch control end.So long as in first switch conduction, this input signal control controlled switch element conductive, the 3rd clock signal makes controlled output terminal export the second voltage turn-on second switch; And when the first not conducting of switch, the second clock signal makes transistor 202 conductings, and the grid of buck transistor 202, make the controlled switch element conductive, the 3rd clock signal makes controlled output terminal export first voltage and closes second switch, can avoid signal output part (second switch output terminal) to be in floating, reach the purpose that improves the display image quality, therefore neither disengaging technical scope of the present invention.
The advantage of disclosed shift register of the above embodiment of the present invention and signal generator thereof is to use three transistors and a simple controlled switch element, when the not conducting of transistor that couples signal output part, the controlled switch element conductive is to form the current path of signal output part and operating voltage, the problem of avoiding signal output part floating to occur and causing display image to glimmer, and then the image quality of raising display.
In sum; though the present invention discloses as above with a preferred embodiment; right its is not in order to limit the present invention; any those skilled in the art; without departing from the spirit and scope of the present invention; when can being used for a variety of modifications and variations, so protection scope of the present invention is as the criterion when looking appended the claim scope person of defining.
Claims (19)
1. a shift register in order to receiving inputted signal, and is exported an output signal according to this, and this shift register comprises:
First switch comprises:
First input end is coupled to this input signal;
First control end is coupled to first clock signal; And
First output terminal;
Transistor has grid, first source/drain and second source/drain, and this grid is coupled to this first output terminal, and this first source/drain is coupled to the second clock signal; And
The controlled switch element comprises:
First controlled input end is coupled to the 3rd clock signal;
Second controlled input end is coupled to first voltage;
The switch control end is coupled to this first output terminal; And
Controlled output terminal; And
Second switch comprises:
Second input end is coupled to this first voltage;
Second control end is coupled to this controlled output terminal;
Second output terminal is coupled to this transistorized this second source/drain, in order to exporting this output signal,
Wherein, this first clock signal is controlled this first switch conduction, and exports this input signal, make this controlled switch element conductive, the 3rd clock signal makes this controlled output terminal export second voltage, and controls this second switch conducting, and this output signal level is this first voltage;
Wherein, this first clock signal is controlled this not conducting of first switch, the level of this this first output terminal of second clock signal buck, make this transistor turns, this output signal is this second clock signal, and the level of this first output terminal changes simultaneously, makes this controlled switch element conductive, the 3rd clock signal makes this controlled output terminal export this first voltage, and controls this not conducting of second switch.
2. shift register according to claim 1, wherein this controlled switch element also comprises:
Diode couples transistor, has anode and negative terminal, and this anode is coupled to the 3rd clock signal; And
The 3rd switch comprises:
The 3rd input end is coupled to this first voltage;
The 3rd control end is coupled to this first output terminal; And
The 3rd output terminal is coupled to this diode and couples transistorized this negative terminal and this second control end.
3. shift register according to claim 2, wherein this first switch, this second switch, the 3rd switch, this diode couple transistor and this transistor is all reached by nmos pass transistor.
4. shift register according to claim 3, wherein this first voltage has low level, and this second voltage is higher than this first voltage.
5. shift register according to claim 4, wherein the 3rd clock signal is this first clock signal.
6. shift register according to claim 5, wherein this second clock signal inversion signal that is this first clock signal.
7. signal generator comprises:
Multi-stage shift register, shift registers at different levels be in order to receiving the input signal from the upper level shift register, and export an output signal according to this, and shift registers at different levels comprise:
First switch comprises:
First input end is coupled to this input signal;
First control end is coupled to first clock signal; And
First output terminal;
Transistor has grid, first source/drain and second source/drain, and this grid is coupled to this first output terminal, and this first source/drain is coupled to the second clock signal; And
The controlled switch element comprises:
First controlled input end is coupled to the 3rd clock signal;
Second controlled input end is coupled to first voltage;
The switch control end is coupled to this first output terminal; And
Controlled output terminal; And
Second switch comprises:
Second input end is coupled to this first voltage;
Second control end is coupled to this controlled output terminal;
Second output terminal is coupled to this transistorized this second source/drain, in order to exporting this output signal,
Wherein, this first clock signal is controlled this first switch conduction, and exports this input signal, make this controlled switch element conductive, the 3rd clock signal makes this controlled output terminal export second voltage, and controls this second switch conducting, and this output signal level is this first voltage;
Wherein, this first clock signal is controlled this not conducting of first switch, the level of this this first output terminal of second clock signal buck, make this transistor turns, this output signal is this second clock signal, and the level of this first output terminal changes simultaneously, makes this controlled switch element conductive, the 3rd clock signal makes this controlled output terminal export this first voltage, and controls this not conducting of second switch.
8. signal generator according to claim 7, wherein this controlled switch element also comprises:
Diode couples transistor, has anode and negative terminal, and this anode is coupled to this first clock signal; And
The 3rd switch comprises:
The 3rd input end is coupled to this first voltage;
The 3rd control end is coupled to this first output terminal; And
The 3rd output terminal is coupled to this diode and couples transistorized this negative terminal and this second control end.
9. signal generator according to claim 8, wherein this first switch, this second switch, the 3rd switch, this diode couple transistor and this transistor is all reached by nmos pass transistor.
10. signal generator according to claim 9, wherein this first voltage has low level, and this second voltage is higher than this first voltage.
11. signal generator according to claim 10, wherein the 3rd clock signal is this first clock signal.
12. signal generator according to claim 11, wherein this second clock signal inversion signal that is this first clock signal.
13. signal generator according to claim 12, wherein this of shift register at the corresponding levels first clock signal phase is that this first clock signal phase with the next stage shift register differed for 1/4 clock period.
14. signal generator according to claim 7 is a scanner driver.
15. a shift register comprises:
The first transistor by the source electrode receiving inputted signal of this first transistor, and receives first clock signal by the grid of this first transistor;
Transistor seconds, the grid of this transistor seconds couples the drain electrode of this first transistor, and the source electrode of this transistor seconds receives the second clock signal, and an output signal is exported in the drain electrode of this transistor seconds;
The 3rd transistor, the 3rd transistor drain couples the source electrode of this transistor seconds, and the 3rd transistorized source electrode receives reference voltage;
The 4th transistor, the 4th transistorized grid and the 4th transistor drain couple this first clock signal, and the 4th transistorized source electrode couples the 3rd transistorized grid; And
The 5th transistor, the 5th transistor drain couple the 4th transistorized source electrode, and the 5th transistorized source electrode receives this reference voltage, and the 5th transistorized grid couples the grid of this transistor seconds.
16. shift register according to claim 15, wherein this first clock signal is controlled this first transistor conducting, and export this input signal, make the 5th transistor turns, this first clock signal makes the 4th transistorized source electrode export second voltage, and control the 3rd transistor turns, and this output signal level is this reference voltage;
Wherein, this first clock signal is controlled this not conducting of the first transistor, the level of the drain electrode of this this first transistor of second clock signal buck, make this transistor seconds conducting, this output signal is this second clock signal, and the level of the drain electrode of this first transistor changes simultaneously, makes the 5th transistor turns, this first clock signal makes the 4th transistorized source electrode export this reference voltage, and controls the 3rd not conducting of transistor.
17. shift register according to claim 16, wherein this first transistor, this transistor seconds, the 3rd transistor, the 4th transistor and the 5th transistor are all reached by nmos pass transistor.
18. shift register according to claim 17, wherein this reference voltage has low level, and this second voltage is higher than this reference voltage.
19. shift register according to claim 18, wherein this second clock signal inversion signal that is this first clock signal.
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| Application Number | Priority Date | Filing Date | Title |
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| CN2006100846148A CN101075481B (en) | 2006-05-19 | 2006-05-19 | Shift register and its signal generator |
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| CN2006100846148A CN101075481B (en) | 2006-05-19 | 2006-05-19 | Shift register and its signal generator |
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| CN101075481A true CN101075481A (en) | 2007-11-21 |
| CN101075481B CN101075481B (en) | 2010-06-16 |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102460587A (en) * | 2009-06-25 | 2012-05-16 | 夏普株式会社 | Shift register circuit, display device provided with same, and shift register circuit driving method |
| CN104900179A (en) * | 2015-06-29 | 2015-09-09 | 杨秀莲 | Array scanning control circuit of flat panel display |
| CN108665854A (en) * | 2017-03-27 | 2018-10-16 | 昆山工研院新型平板显示技术中心有限公司 | Control signal drive circuit and driving method and pixel circuit drive method |
| WO2020052343A1 (en) * | 2018-09-11 | 2020-03-19 | 京东方科技集团股份有限公司 | Shift register unit and drive method therefor, gate driver circuit, and display device |
-
2006
- 2006-05-19 CN CN2006100846148A patent/CN101075481B/en not_active Expired - Fee Related
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102460587A (en) * | 2009-06-25 | 2012-05-16 | 夏普株式会社 | Shift register circuit, display device provided with same, and shift register circuit driving method |
| CN102460587B (en) * | 2009-06-25 | 2014-12-17 | 夏普株式会社 | Shift register, display device provided with same, and shift register driving method |
| CN104900179A (en) * | 2015-06-29 | 2015-09-09 | 杨秀莲 | Array scanning control circuit of flat panel display |
| CN104900179B (en) * | 2015-06-29 | 2017-08-18 | 重庆市中光电显示技术有限公司 | A kind of array scanning control circuit of flat-panel monitor |
| CN108665854A (en) * | 2017-03-27 | 2018-10-16 | 昆山工研院新型平板显示技术中心有限公司 | Control signal drive circuit and driving method and pixel circuit drive method |
| WO2020052343A1 (en) * | 2018-09-11 | 2020-03-19 | 京东方科技集团股份有限公司 | Shift register unit and drive method therefor, gate driver circuit, and display device |
| US11468820B2 (en) | 2018-09-11 | 2022-10-11 | Fuzhou Boe Optoelectronics Technology Co., Ltd. | Control circuit configuration for shift register unit, gate driving circuit and display device, and method for driving the shift register unit |
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| Publication number | Publication date |
|---|---|
| CN101075481B (en) | 2010-06-16 |
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