CN1010732B - Digital radio frequency receiver - Google Patents
Digital radio frequency receiverInfo
- Publication number
- CN1010732B CN1010732B CN 86105333 CN86105333A CN1010732B CN 1010732 B CN1010732 B CN 1010732B CN 86105333 CN86105333 CN 86105333 CN 86105333 A CN86105333 A CN 86105333A CN 1010732 B CN1010732 B CN 1010732B
- Authority
- CN
- China
- Prior art keywords
- digital
- signal
- sampling
- narrow
- band
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Images
Landscapes
- Analogue/Digital Conversion (AREA)
- Digital Transmission Methods That Use Modulated Carrier Waves (AREA)
Abstract
A digital FM demodulator is described. According to the principles of the present invention, a digital FM signal is demodulated by processing sampled input vectors of a quadrature FM digital signal centered approximately zero frequency. The sampled quadrature input vectors are quantized to lie within a predetermined magnitude range. The quantized vectors are coupled to a phase accumulator which generates a current coarse phase value related to input vectors of the quadrature FM signal. The output of the phase accumulator is also coupled to a vector rotation means which rotates the input vector to a predetermined quadrant to determine a fine phase value based on said rotated input signal vector. The fine and coarse values are then summed and output as a composite phase value, and digitally filtered by subtracting the value of the previous composite phase angle sample from the value of the current composite phase angle sample to produce a demodulated message sample.
Description
The present invention relates to telecommunications context, is exactly the radio-frequency transmitter of being realized by digital circuit basically particularly.
Traditional telecommunication equipment is that pattern is intended the circuit realization basically.The inherent characteristic of simulated assembly has limited the number of signals that can handle.For example, the noise of analogue amplifier and gain characteristic have limited the dynamic range of processed analog signal.In addition, analog information can not be stored easily, so that carry out complicated signal processing.
The operation of using Digital Signal Processing to use simulation process to carry out before replacing, eliminated in the operation may since not wishing of being caused of external action (as temperature, humidity and analogue device are aging) change.In addition, in the character and the characteristic aspect of processing able to programme, Digital Signal Processing provides flexibility.For example, the channel frequence of digital intermediate frequency (IF) integrating circuit, sampling rate, and its filter response all is programmable to a certain extent.When carrying out the program of alternately storage, digital signal processor (DSP) can carry out different filtering and demodulation, to realize the diverse wireless device of type.DSP also can be used to introduce advanced treatment technology, as free should be balanced.
Another advantage of digital receiver structure is, DSP and IF circuit can design to such an extent that make it can " conversely " carry out the corresponding operating of Digital Implementation transmitter.For half-duplex operation, circuit can utilize switch transition, so that make its " oppositely " simply, and to full bidirectional operation, then needs two IF filters.
The basic technical contribution that makes the real figure receiver have feasibility is a high speed (20-100 megahertz), the A/D converter of high-resolution (10-12 bit).The resulting high integration of realization that second factor that causes digital receiver structure technology possibility is VLSIIC and high-speed, for example, it finally makes 4 utmost points with 40 kilo hertzs of sampling rates/4 zero points (4-pole/4-zero) double precision filter can realize in the digital signal processor of today.The present invention combines these new technologies and improved front end simulation process and digital IF filtering, to finish the feasible design of real figure receiver.
Receiver structure of the present invention makes the manufacturing technology and the operating characteristic of mobile wireless electricity equipment that revolutionary variation arranged.And this method can be set up receiver with the assembly of minimal amount, and this has just reduced assembly and manufacturing expense, has also improved the reliability in radio station and the convenience of maintenance simultaneously at once.
Generally speaking, the present invention will finish a kind of full-digital radio receiver, and it handles the radiofrequency signal that receives, and described signal changes digital form into after the antenna output end preliminary election.Receiver of the present invention comprises preselector, high speed mould-number (A/D) transducer, intermediate frequency (IF) selectivity part with Digital Implementation of the output signal on the practical base-band frequency, and select at last or balance, demodulation is transferred nextport universal digital signal processor NextPort (DSP) integrated circuit of reprocessing.
According to the radio receiver that an object of the present invention is to provide a kind of Digital Implementation.
Another object of the present invention provides a kind of radio receiver structure that receives multiple radiation pattern that is easy to adapt to.
A further object of the present invention provides the radio receiver structure that a kind of in fact available integrated circuit technique realizes.
A further object of the invention provides a kind of digital receiver IF filter meter and establishes, and it is with fast relatively speed work, so that reduction is to the requirement of the resolution and the step-length of A/D converter.
Fig. 1 is the block diagram that shows the effect of digital receiver of the present invention.
Fig. 2 is the schematic diagram of digital receiver front end circuit of the present invention.
Fig. 3 is the block diagram that digital zero IF of the present invention selects part.
Fig. 4 a is the theory diagram of the digital oscillator mentioned among Fig. 1.
Fig. 4 b be with Fig. 3 in digital zero IF select the schematic diagram of the compatible pseudorandom dither generator of part.
Fig. 5 a is needed " fast ", the block diagram of narrowband low-pass filter.
Fig. 5 b is the approximate block diagram of the decomposition of the quick low pass filter of Fig. 5 a.
Fig. 6 a is the frequency diagram that the quick low-pass filter characteristic of Fig. 5 is described in detail in detail to Fig. 6 d.
Fig. 7 is the schematic diagram that is used for second order narrow-band low pass infinite impulse response (IIR) filter of the quick low pass filter that Fig. 5 b decomposes.
Fig. 8 is used for quick low pass filter that Fig. 5 b decomposes, has to be half the schematic diagram of second order finite impulse response (FIR) (FIR) filter of depression sign of sampling rate.
Fig. 9 a is to be used for the time that time described in Fig. 3 cuts apart multiple " at a slow speed " low pass filter to cut apart multiple step low-pass iir filter schematic diagram to Fig. 9 c.
Figure 10 be for further with sampling rate from 80 kilo hertzs of block diagrams that are reduced to 40 kilo hertzs of 5 rank low-pass FIR filters that adopted.
Figure 11 is the block diagram of the quadravalence low pass iir filter that adopted for last selectivity and passband balance before demodulation.
Figure 12 is a block diagram by the FM demodulator of general dsp realization.
Figure 13 a is the figure that the principle of the phasor in the literary composition of the present invention is described in detail in detail to Figure 13 c.
Figure 14 a and Figure 14 b are the flow charts that the operation of FM demodulator of the present invention backstage backward program is described in detail in detail.
Figure 15 a is the flow chart of the operation of the described scale routine of Figure 15 a to Figure 15 b.
Figure 16 a is the flow chart that the operation of digital demodulator remainder of the present invention is described in detail in detail to Figure 16 c.
Fig. 1 illustrates the effect of digital receiver, and it comprises three main operations.Although do not provide the example of different receivers in the drawings, for the people who is good at this technology clearly, in receiver of the present invention, can use various method.Especially, " front end " part 104(will be in Fig. 2 more detailed description), the antenna 102 that receives analog radio frequency (RF) signal is connected to the IF selectivity part 110 of Digital Implementation.Preselector 106 provides the wideband filtered to input signal, obscures in follow-up A/D transfer process preventing.A/D functional block 108 comprises for the necessary gain of the digital processing of this receiver structure and sampling-maintenance operation.
Next major part, IF selectivity part 110(will be described in further detail among Fig. 3 below), the quadrature local oscillator (LO) 116 of generation complex exponential signal (sine of quadrature and cosine signal) is provided.The frequency of this signal is selected by system channel frequency input " A ".Orthogonal mixer 112 utilizes the digital multiplier shift frequency, and required narrow channel is dropped to approaching zero hertz IF frequency.High speed selectivity part 114 comprises the narrowband low-pass filter part of several cascades, and they will be removed near the desired signal of undesirable signal concentrating on zero-frequency of high frequency.This low-pass filtering make sampling rate gradually from the two-forty at A/D converter 108 outputs ease down to can with the comparable speed of bandwidth chahnel at " rear end " part 120 inputs.
" rear end " part 120 is used for general broadcasting station structure " specialization " is become specifically to be suitable for the structure used by one of system's radio station type input " B " appointment special radio station.Its best realizes comprising a nextport universal digital signal processor NextPort (DSP).Final selectivity part 124 is provided at before the radio signal demodulation, is suitable for any required auxiliary filtering of modulation type and channel characteristic.For example, can provide the adaptive channel balance to a numerical data communication system.Also provide the adjacent channel decay than filtering part 124, and the passband balance, with the imperfection of compensated high-speed selective filter 114 characteristics, the imperfection of characteristic is owing to realizing that the needed thick coefficient quantization of multiplier-less (low pass) filter causes.But demodulation part 126 software programmings realize polytype demodulation, comprise the FM demodulation that is used for voice and frequency shift keying (FSK) data.Voice signal after the demodulation can change back to analog form, amplifies and pass through loudspeaker plays then, as providing in image 121 and 122.Perhaps, digital speech information is stored digital memory 123, play again after being provided with.(not shown) in data communication system, the data symbol after the demodulation can send to computer so that further handle, and perhaps send to terminal and show immediately.In addition, the control information of realization automatic frequency tracking 128 can produce from " rear end " part 120.At last, need clock generating part 118, control the input sample speed (this is absolutely necessary for accurate down converted) of A/D conversion and allow digital circuit move in the mode of routine, and control output sampling rate (this is perhaps for synchronous with follow-on system).Here in the embodiment as example of Miao Shuing, sampling rate fs gets and does 20 megahertzes, and the band center that receive is in about 875 megahertzes.
Fig. 2 is the front end schematic circuit of digital receiver of the present invention.The effect of circuit is the radiofrequency signal digitlization with selected frequency band.The invention enables sampling directly at R.F. frequency is finished.But, before sampling, provide the broadband preliminary election by the R.F. analog filter.R.F. filter 202 and 206 effect provide the selectivity to signal imitation.These signal imitations are included in the reflection that traditional receiver front end exists, half IF spine, Able-Baker spine or the like.Except these spines, also must provide selectivity to frequency, cause and obscure because it may be sampled process.Maximum allows that bandwidth is limited by Nyquist bandwidth (fs/2, fs is a sampling rate) herein, but practical filter will be significantly less than this limit.
Use 2 utmost points as shown in Figure 2, about 4 megahertzes of each bandwidth and 5 utmost point filters, when sampling, can provide inhibition the frequency of obscuring greater than 90 decibels with 20 megahertz speed.Except the signal that enters antenna 224 is provided the selectivity, filter 206 has been gone back frequency band limits by R.F。The broadband noise that preamplifier 204 produces enters first sampling and keeps 208.This has improved the noise factor of front end 200 thus effectively for preventing that obscuring of noise from being necessary.R.F. preamplifier 204 is used for the R.F. signal is amplified to enough levels, to provide system sensitivity desired essential signal to noise ratio.Because different frequency band needs different filters, be R.F. amplifier 204 practical as the part of filter structure (202 and 206).Receiver of the present invention provides about 28 decibels an of gain, the R.F. amplifier 204 that noise factor is about 5 decibels.
Amplify and the frequency band of the signal selected by functional block 202,204 and 206, by first sampling with keep 208 samplings.This is similar with down converted in traditional R.F. receiver.Though quick analog-digital converter is acquired signal effectively,, thereby need before transducer, sample because the actual converted utensil has the finite bandwidth input.And all known high-resolution (＞10) so far, high-speed converters are all utilized two step transfer processes.Such transducer must use second sampling and the holding circuit 220.
Dual sampling is for overcoming acquisition time, and precision and the physical constraints that descends are necessary.First sampling and the collection that keeps must be exceedingly fast, in receiver of the present invention in 300 picosecond scopes.This just need utilize little maintenance electric capacity, so that by each sampling electric capacity is charged, up to the voltage near input signal.Owing to be charged to input signal values fully in can not be between sampling period, caused slight Filtering Processing, this is negligible for the narrow band signal that the typical case is used for the motor-driven communication in land.In first sampling with the fall off rate that uses little maintenance electric capacity to cause in keeping, to two steps release-number converter is nonconforming.Equally, may not be suitable for two step transducers the settling time of first sampling and the relative simple holding circuit that keeps to use.Because these reasons have adopted high accuracy second sampling and have kept 220.Because signal is down converted effectively, its this moment with slowly many rate variation.This just allows to use long acquisition time and bigger maintenance electric capacity.Known two step transducers require sampling and remain on the decline that is significantly less than in (typical case is less than the 1/2 sampling period) time in sampling period less than 1/2 step-length.
First sampling and maintenance (208) can realize as buffer amplifier with Schottky diode electric bridge and bigrid MOS FET according to conventional art.Second sampling and maintenance can utilize the Schottky diode electric bridge to realize, this bridge has additional reverse biased, so that restriction descends when keeping pattern.Be used as buffer amplifier by differential configuration J-FETS as input and the bipolar high speed amplifier of forming of following of high dynamic range.
209 pairs of further amplifying signals of wide-band amplifier are necessary so that overcome the quantizing noise of analog-digital converter.Amplifier 209 is used to amplify the signal that sampling obtains, thereby it must be the broadband.High dynamic range also is necessary, causes distorted signals to prevent amplifier nonlinearity.The noise factor of amplifier 209 depends on " reception " gain number of being provided by R.F. amplifier 204 and to the whole noise requirements of sensitivity.Motorola MHW591 CATV wide-band amplifier is suitable for the wide-band amplifier as 800 megahertz receivers of the present invention.With the similar A/D converter structure of type described herein, at Muto, in the article of Peetz and Reher explanation is arranged, referring to " designing one 10, the analog-to-digital conversion system of per second 20,000,000 characters (Designing a 10-bit; 20Ms-Per-Second Analog-to-Digital Converter System) ", Hewlett-Packard's magazine (HEWLETT PACKARD JOURNAL), November nineteen eighty-two, the 33rd volume, No. 11, the 9-29 page or leaf.
According to principle of the present invention, in combiner/splitter 214, dither signal 218 is added on the signal that obtains of sampling.Combiner/splitter helps to prevent to be present in non-linear in wide-band amplifier and the dither source and converts lowpass noise to other frequency.The purpose of dither 218 is evenly to expand the quantizing noise of analog-digital converter.The even expansion of noise base portion (noise floor) on the Nyquist bandwidth prevents to become intrinsic problem by the intermodulation distortion that quantizes to cause, and allow to recover at least significant bit signal below horizontal, reduced the gain requirement before A/D converter thus, and alleviated because the non-linear problem that causes in the transducer previous stages.If use two transducers, dither signal 218 adds before must and keeping 220 in second sampling, because signal must remain unchanged in the transition period.Dither source 218 can utilize the analogue noise source for example diode noise generator realize.The universal feature of dither signal and advantage are at Schuchman.L. be described in the article of being write.Referring to " dither signal and their effects (Dither Signals and Their Effect on Quantization Noise) in quantizing noise ", Institute of Electrical and Electronics Engineers mechanics of communication collected works (IEEE TRANSACTIONS ON COMMUNICA-TION TECHNOLOGY), in December, 1964, the 162-165 page or leaf.
The noise that is added on the signal should be isolated with information on frequency spectrum.The sampling of being carried out in 800 megahertz receivers of the present invention is placed on information between about 3 to 7 megahertzes.Low pass filter 216 prevents that noise is added on the information signal.Receiver of the present invention is that low pass filter 216 is equipped with 5 utmost point elliptic filters that a cut-off frequency is 1.5 megahertzes.The average level of dither signal on the noise equivalent bandwidth of low pass filter 216, should 5 step-lengths greater than analog-digital converter about.Must be noted that and prevent that dither signal from causing slicing on A/D converter 222.
Analog to digital converter 222 is a digital signal with analog-signal transitions.Transducer must be from the dynamic environment that needed receiver is used acknowledge(ment) signal.For the motor-driven communication applications in land, minimum must the 10A/D position, and theoretical research shows, can be comparable with all existing motor-driven receivers in traditional land by the dynamic range that 12 bit pads provide.Two factors that analog-digital converter 222 has basic importance are sample rate and step-length.Essential gain number before the step-length decision conversion is so that receive the noise basis portion that quantizes.Step-length is big more, and gain requires big more.Big gain causes the nonlinear effect before the transducer.Conversion speed is also extremely important, because its determines the bandwidth of allowing of front end filter, and by the quantizing noise expansion is reduced the requirement to gain on bigger bandwidth.
The analog-digital converter 222 that satisfies the use of the present invention's 800 megahertz digital receivers is about 3 millivolts two steps, 10 bit pads of step-length, and it can be with the rate transition greater than 50 megahertzes.According to principle of the present invention, about 54 decibels front-end gain is for realizing that about 10 decibels post-detection signal to noise ratio is essential in the receiver that has 30 kilo hertzs of bandwidth when receiving 3 microvolt signals that obtain with the sampling of 20 megahertz speed.Before transducer 222 necessary a large amount of gain-limitation the non-linear behavior of system.Modulation rate (IMR) is limited to about 65 decibels mutually, and this is lower than the index that traditional receiver can reach a little.For the people who generally is familiar with this technology, clearly,, IMR＞80 decibel will be allowed to reach if step-length is reduced to about 200 microvolts.This numerical value can be compared with most of existing tradition 800 megahertz receivers.
Referring now to Fig. 3, the digital zero IF selectivity part (DZISS) that is suitable for the present invention practice is described with the form of block diagram.Digital zero IF selectivity part, be arranged between the rear end DSP120 of the front end circuit 200 of Fig. 2 and Fig. 1, and its operation makes the modulated RF signal by front end 200 outputs convert the baseband signal of being handled by rear end 120 to, DZISS is by an inphase mixer 304, a quadrature phase frequency mixer 306, a digital quadrature local oscillator (LO) 302(provides homophase LO signal 309 and quadrature phase LO signal 311), two " soon " wave digital lowpass filters 308 and 310, two " slowly " wave digital lowpass filters 312 and 313, and a clock source (not shown) is formed.
In actual practice of the present invention, at input port 303 and 307 identical digital information is added to inphase mixer 304 and quadrature phase frequency mixer 306 respectively.In general, port 303 and 307 is not a line, in fact is many lines representing multidigit (as 10 or 12) numeral.The physical length of the numeral of using in any given application depends on many factors, comprising: the resolution of requirement, the frequency of the RF signal that the dynamic range of requirement and sampling receive.12 word length is considered to have qualified performance when reception 20 megahertzes are sampled the typical radio signal that obtains.
Can improved noise characteristic, this knows for people in this technology.Above-mentioned quadrature optical mixing process with in simulation " zero IF ", or the process of directly changing in the receiver to be carried out is similar.But, use really linear digital multiplier, got rid of the unwanted signal of generation in the direct conversion of simulation and the second order mixing of D.C., and other undesirable effect.
To near zero hertz centre frequency, wherein the frequency inverted amount can be controlled 305 decisions by channel frequence with needed signal frequency converting in the quadrature mixing of being undertaken by multiplier 304 and 306.The quadrature mixed frequency signal of gained then can be through low-pass filtering, to remove out-of-band noise and unwanted signal.In the practice of the best of the present invention, this selectivity provides in two-stage.The first order is made of quick recursive digital filter part 308 and 310. Digital filter 308 and 310 structures are identical, and can make according to the recursion filter topology, and this technology will be described in greater detail below.Remaining selectivity is by " slower " recursion filter 312, and 313 provide respectively.This selection of structure will discuss in more detail below.And then after the filtering, digital signal outputs to rear end DSP120 so that further handle.
Fig. 4 a is the principle and the block diagram of the digital oscillator described among Fig. 3.We remember that the effect of quadrature oscillator provides and is used for the digitized of quadrature optical mixing process, the sine and the cosine waveform of sampling type.The realization of digital zero IF selectivity part depends on the ability of the accurate and stable numeral that produces these wave modes.Being particularly suitable for the formation of a class digital oscillator of requirement of the present invention, is to be based upon the ROM(read-only memory) table look-up notional.Consider to comprise the generation of the sinusoidal wave digital signal of sampling of plural number:
W（t）＝e
j2πfct
Wherein fc is the frequency of needed oscillator.
According to traditional Communication Theory,
e
j2πfct＝cos2πfct+jsin2πfct
Like this, can be considered to be respectively plural sine-shaped real part and imaginary part for needed sine and cosine waveform.The e of sampling type
J2 π fc
tCan be by replacing continuous time variable t obtain with discrete time variable nT, here n be the counting integer (1,2,3 ...), and T is the sampling period, it equals the 1/fs=1/ sample frequency.Thereby this discrete time signal is equivalent to:
W（n）＝e
j2πfc（nT）
Producing the ROM look-up method of this signal, is by making frequency variable f
cAnd time variable is discrete draws.If we allow
fC=Kfs/2
N(K and N are integers here), so:
W（n）＝e
j2πkfs（n/fs）/2
N＝e
j2πnk/2
N
As can be seen, have only 2
NThe cosine of individual out of phase and sine value need to produce.Produce a kind of method of these numerical value, make direct ROM table look-up, it consists essentially of to use and comprises 2
NThe ROM table of logarithm value (cosine and sine), these are 2 years old
NLogarithm value comprises Integer n K(by one and is proportional to phase place) register addressing.Phase register increases numerical value K(corresponding to needed frequency f c in each sampling time (corresponding to n)).Resulting frequency resolution is △ f=fs/2
N, can produce 2 thus
NIndividual different frequency.
According to the needs of using, directly the ROM look up table technique may comprise a large amount of ROM.But can utilize the advantage of cosine and sine-shaped symmetric property, reduce the scale of ROM.This character can make the entry number of table from 2
NTo reducing to 2
N/ 8 pairs.Even now, the scale of ROM are still greatly.In this case, can utilize a kind of factor that is called to decompose the scale that technology that ROM tables look-up further reduces ROM.
Digital local oscillator 400 of the present invention adopts the factor to decompose the ROM look up table technique, and what it utilized is such fact, and promptly the unit amplitude phasor can be decomposed into the multiplication of complex numbers of " slightly " and " carefully " phasor.Like this, unit amplitude phasor e
jφ can be with being e with signal decomposition
J φCe
J φ fRepresent.Therefore, the unit amplitude phasor can realize like this, and thick value phasor of separating and thin value phasor are stored among the ROM, and both are taken advantage of together to obtain the discrete time sine and the cosine value of orthogonal mixer requirement.The advantage that this factor is decomposed is, the thick value of storage and carefully the necessary ROM number of value phasor than direct ROM lookup table mode is desired great minimizing arranged.The cost that this ROM scale reduces to be paid is to introduce the circuit that carries out thick and thin phasor complex multiplication.Usually, complex multiplication can be finished with four multipliers and two adders.By suitably selecting thin value phasor, and consider that low-angle cosine value can be similar to 1, being used for the ROM that cosine carefully is worth phasor can save.And, by the low-angle cosine value is approximately 1, can from produce the desired multiplication structure of the multiplication of complex numbers, save two multipliers.This causes decomposing in the factor saving of expense and scale in the ROM method.
Still, utilize the factor to decompose of the formal description of the digital quadrature local oscillator of ROM method realization with block diagram referring to Fig. 4 a.In A/D converter sampling frequency band, the frequency information with the N bit form that is proportional to required frequency, input channel frequency latch 402.Channel frequence latch 402 can constitute by multiple different form.For example, suppose N=20, the 74LS175(four end d type flip flops by motorola inc's manufacturing of 5 cascades) and other assembly, the realization that meets the requirements can be provided.Those people that are good at this technology can know, channel frequence latch 402 input that can in all sorts of ways.For example, in the unifrequency radio station, the channel frequence latch will be imported single binary number all the time.And for the multi-frequency radio station, channel frequence latch 402 perhaps latchs by the microprocessor computing and from it in addition from EPROM or the ROM form input of tabling look-up.
Channel frequence latch 402 is connected to binary adder 404.Those people that are good at this technology can understand that in the discussion to digital quadrature local oscillator 400, all connecting lines between each functional block in fact all are multidigit binary system word lines, rather than single line below.Phase accumulator 406 is received in the output of adder 404.Phase accumulator 406 can constitute a N position binary latch, in order to store the address of the ROM position that the next one will addressing.Like this, the output of phase accumulator 406 can directly be received cosine and slightly is worth ROM418, and we do not need to remember sine thick value ROM416 and sinusoidal thin value ROM414(carefully to be worth cosine ROM, are similar to 1 at this moment because carefully be worth cosine).And the output of phase accumulator 406 is fed back to adder 404, so that be in the binary number addition (mould 2 of channel frequence latch 402 internal channel frequency informations with representative
N).The output of phase accumulator 406, each clock cycle upgrades once, and the clock cycle is sample frequency normally.The result of this binary addition is that phase accumulator 406 is storing last address with the binary system that is included in a binary vector addition in the channel frequence latch and (being proportional to phase place).This numeral produces quadrature local oscillator signal Cos2 π fcnT and the desired next address of Sin2 π fcnT.
In optimum implementation, the output by digital dither signal being added to phase accumulator 406 and before addressing ROM form with truncation as a result, can reduce the scale of ROM, or ground of equal value, can improve frequency resolution and not increase the scale of ROM.The frequency resolution of local oscillator is by the wide data path (N) of phase accumulator and the sampling rate fs definition that requires.The most direct method that increases frequency resolution is the scale that phase accumulator is added more figure place and increase the ROM form.But this will be the way of a costliness, because one of the every increase of phase accumulator, the scale of ROM will double.Another selection is the figure place that increases phase accumulator, but casts out additional figure place before tabling look-up carrying out ROM.This will introduce, and serious phase place rounds off and cause spine in local oscillator output.For fear of these spines, before truncation, low-level dither signal is added to accumulator and exports.
According to principle of the present invention,, can improve the frequency resolution of digital oscillator and do not increase the scale of ROM and do not introduce spine in output by before truncation, the binary system dither signal being added to the output of phase accumulator 406.In order to achieve this end, digital oscillator 400 has the dither source 408 of a L position, and it produces the L bit wide, even probability density, pseudorandom " white noise " signal.The clock frequency in dither source 408 is decided to be sample frequency, so that to each the phase place word from phase accumulator 406 outputs, provides the dither word of a new L position.By with M=N-L the zero front that is added to the L position dither words of 408 outputs, constitute a N position dither word from the dither source.By N position binary adder 410, with mould 2
NForm, the N position dither word that this sample is closed and the output addition of the N position of phase accumulator 406.Then adder 410 cast out M position (truncation does not draw) with output.In practice, this truncation process can be finished by omitting the some least significant bits that produce in digital adder 410 outputs simply.The truncation operation itself makes the ROM scale reduce.
Distortion or noise take place in the quantification of binary phase word or truncation when producing sinusoidal and cosine waveform.Because phase place is one-period function (sawtooth waveforms), also will be periodic by the noise that quantizes to produce, unless it is randomized with certain side.Periodic noise will cause discrete " spine " in the output spectral line of oscillator, if they surpass certain threshold value, be undesirable in great majority are used.Added that before phase quantization dither signal can make the phase noise randomization, and have the white noise spectrum that more closes requirement in output.The binary phase word is represented by a N position binary word.Dither signal comprises the pseudo-random binary word of a L position, the phase place word addition of it and N position.This process has produced the binary word of a N=L+M position.This binary word becomes the binary phase word of a M position then through truncation, it is not subjected to the influence of above-mentioned glitch comparatively speaking.
The phase quantization effect of oscillator output noise can be illustrated by following analysis.Desirable oscillator output is described by following equation:
W（n）＝e
j2πfc
nT＝e
jφ（n）
If the phase angle has error when quantizing
(n), time output is described by following formula so:
W（n）＝e
j〔φ（n）+ 
（n）〕
The error of being introduced is:
E（n）＝W（n）-W（n）＝e
j〔φ（n）+ 
（n）〕-e
jφ（n）
＝e
jφ（n）〔ej
（n）-1〕
For significant situation,
(n) very little (＜＜1), ej
(n) available 1+j
(n) approximate, can get thus:
E（n）＝e
jφ（n）·j
（n）
E(n) it only is the frequency translation (and by the inessential scale of j) of phase quantization noise spectral line that spectral line can be regarded as.Therefore, if
(n) be at random or " in vain ", E(n so) too.And, power E(n) with
(n) identical, make the level of the output noise that causes by phase noise to estimate at an easy rate.
Select the power level of dither signal between noise whitening effect and output noise power level, to do the folding table.Along with the increase (by increasing the figure place L in the dither signal) of dither power, it is whiter that noise will become, but total phase noise power also increases simultaneously.As can be seen,, select L=N-M will make dither power have optimum level, because its representative will be with the necessary minimum dither signal of the complete albefaction of phase quantization noise if dither signal shows uniform probability density.Therefore in the best realizes, the figure place L of dither signal equals the figure place that abandons in the truncation process.It should be noted that, can utilize the dither signal that presents non-homogeneous probability density.But uniform density preferably is because it is easy to generate most.Because L=N-M, the variation of phase noise (power) equals two times of phase change of dither signal of equal value.A given desirable resolution by N and fs decision, L and M so, thereby desired ROM scale are by the permissible level decision at the white noise of oscillator output.
As example, when the fs=20 megahertz, during the N=20 position, frequency resolution is 19.07 hertz.There not being to be truncated under the situation of dither M=17 position (so that the ROM scale reduces a factor 8), produce spine in oscillator output, it is lower than 98 decibels of the levels of needed signal for a characteristic frequency.Before truncation, add 3 dither signal, error signal is bleached, remove spine.According to principle of the present invention, for a given output noise level, as long as simply with frequency and phase latch, and dither signal adds more position, just can unrestrictedly increase the frequency resolution of digital oscillator.ROM scale by the M decision remains unchanged.The M position binary word that retains behind the truncation is delivered to ROM address latch 4/2, and latch 412 outputs are connected to ROM418,416 and 414.When receiving an address, ROM418,416 and 414 at they output ports separately, and output is positioned at the digital binary word at the place, address that receives.Produced digital quadrature signal from three binary number computings then.
As previously mentioned, ROM416 and 418 output signal are cosine and the sinusoidal binary numbers that is proportional to thick phase place.The output signal of ROM414 is the binary number that is proportional to the sine of thin phase place.Error drops to minimum in thin cosine is approximate in order to make, and used thin phase value is to concentrate near the value of positive axis.The output of ROM address latch 412 is numbers of a M position, and it is divided into the thin address in thick address, Mc position and Mf position, M=Mc+Mf here.Thick phase place is 2 π (Pc+1/2)/2
Mc, wherein Pc is the integer corresponding to thick address, Mc position.Thin phase place is 2 π (Pf-2
Mf-1)/2
M, wherein Pf is the integer corresponding to thin address, Mf position.For example, if M
c=10 and Mf=7, the table 1 shown in below the clauses and subclauses of ROM form can have and the structure of table 2.
Table 1
Address (Pc) is slightly " Pc " thick in the address of " Pc " in the address
The content of the content SIN ROM of COS ROM
0 COS2π·（1）/2 SIN2π·（1）/2
1 COS2π·（3）/2 SIN2π·（3）/2
2 COS2π·（5）/2 SIN2π·（5）/2
3 COS2π·（7）/2 SIN2π·（7）/2
4 COS2π·（9）/2 SIN2π·（9）/2
·
·
·
1022 COS2π（2045）/2 SIN2π（2045）/2
1023 COS2π（2047）/2 SIN2π（2047）/2
Table 2
Address (Pf) is thin address Pf's
SIN ROM content
0 SIN2π（-64）/2
1 SIN2π（-63）/2
2 SIN2π（-62）/2
3 SIN2π（-61）/2
126 SIN2π（62）/2
127 SIN2π（63）/2
For producing cosine waveform (being the real part of complex waveform), the output of sinusoidal approximation ROM418 and sinusoidal exact value ROM414 is at first multiplied each other in multiplier 426.The output of multiplier 426 is added on the summing circuit 440, and it is deducted (form of the complement code with 2) from the output of cosine approximation ROM416 at this place.This calculating process produces cosine value, and it is being exported on the passage 441 and is being coupled on the orthogonal mixer of Fig. 3.For producing the sine value of digital quadrature value LO, cosine approximation ROM416 and sinusoidal exact value ROM414 multiply each other in multiplier 428.The output of multiplier 428 is added on the summing circuit 442, locates its output addition with sinusoidal approximation ROM418 at this.Summing circuit 442 is by connecting the discrete time sine value digital code of 443 outputs, and it is coupled on the orthogonal mixer 306 of Fig. 3.Like this, because the discrete time value of sinusoidal and cosine signal is calculated on mathematics, control mutually so reach 90 desirable degree positions with minimum ROM space.Register 420,422,424,434 and 438 provide streamline, and it helps the high running speed of digital oscillator.Delay circuit 430 and 436 is used for the delay of balanced unlike signal path.
The ROMLO(read-only memory local oscillator that decomposes) reduces the zone of ROM, keep acceptable frequency resolution simultaneously.For example, be operated in 20MH for providing
2Digital quadrature LO, each approximation ROM416,418 can realize in 1024 * 16ROM, and the sinusoidal ROM414 of exact value can realize in 128 * 8ROM.This causes using the ROM of about 34,000 bits to reach about 20H
2Frequency resolution.Because except the phase accumulator of position, there is not the circuit of feedback form, so the ROM structure of decomposing is more suitable for the operation of high sampling rate.This allows the remainder (particularly multiplier 426 and 428, they are main speed bottle-necks) of LO circuit to constitute streamline to realize the very high speed of service.Streamline can be included in some key points and introduce latch, as know in the prior art in multiplier inside.So just described the ROMLO that decomposes, its output has the discrete time figure orthogonal signalling of selected frequency.
The digital adder that is applicable to device of the present invention can be the form that some 7,4LS,181 4 bit arithmetic logical block devices compose in parallel.These devices show within the databook that is entitled as " Motorla Schottky TTL databook " that motorola inc (Box2092 Phoehix, Arizona, 85036) provides and describe.ROM418,416 and 414 can be made of the multiple ROM device of knowing, as (the 811E of Signetics company that describes in " the bipolar storage databook of Signetics " (1984), Argues Aveue, P.O.Box3409, Sunnyvale, Calif, 94088) 82LSI81 that provides.For example, multiplier 426 and 428 all can be by TRW Ltd. (US) One Space Park, Redondo Beach CA 90278 U.S.A. of group of TRW electronics corporation (P.O.Box2472, Lajolla, the MPYO16K that Ca.92038) produces realization.
The quantity of required approximation ROM can further reduce by the symmetric advantage of utilizing sinusoidal and cosine waveform, like this, only needs the value of the unit amplitude phasor in eight/one-period (promptly 45 spend) of storage phasor unit circle.The people who knows prior art knows sine or the cosine value that revolves three-sixth turn with the unit amplitude phasor representation.According to sinusoidal waveform symmetric property still, except may reversion changing (promptly with mutual, sine becomes cosine and opposite process) outside, cosine and the sinusoidal waveform value on an eight/one-period of unit circle equates with the value of these waveforms on other eight/one-period.Like this, only the approximation phasor that needs is in eight/one-period, add that phasor is in the indicating device of which eight/one-period, also with good grounds current eight/one-period negates (being reindexing) and/or changes the circuit of the output of approximate cosine ROM416 and near sinusoidal ROM418.Eight/one-period, indicating device realized at an easy rate with three binary digit ROM addresses.For example, three highest orders (MSB) can be used to represent eight/one-period, and remaining position is used for pairing approximation value phasor ROM addressing.
Fig. 4 b is the schematic diagram with the example of a kind of digital high frequency oscillation generator of digital oscillator compatibility of the present invention.The numeral high-frequency oscillation signal can be produced by any pseudo random sequence generation technique of knowing.A kind of higher-order of oscillation of form, or randomizer is at article " the high speed randomizer " (A High-Speed Random-Number Generator) of G.I.Donov, " radio electronics and communication system " the 25th volume, the 4th phase, show in the 88-90 page or leaf (nineteen eighty-two) and description.
With reference now to Fig. 4 b,, show 3 feedback shift register pseudo-random sequence generators with the form of scheming, it is convenient to be used in the realization of the present invention.The sequencer of Fig. 4 b is used to provide the binary adder 410 of L bit digital high-frequency oscillation signal to Fig. 4 a.High frequency oscillation generator 408 comprises R Bit Shift register 460, and it can be made of to 499 a plurality of triggers of connecting with cascade system 464.In practice preferably of the present invention, 3 parallel high-frequency oscillation signals are tap on the shift register from the output that is positioned at trigger 478,491 and 499 respectively.Be coupled on trigger 464,493,498 and 499 for the input of exclusive-OR gate 462.The output of exclusive-OR gate 462 is coupled in the input of trigger 464.Shift register produces 3 pseudorandom high-frequency oscillation signals, and it is added in the output of phase accumulator 406 of Fig. 4 a.The same with other device that uses in the practice of the present invention, trigger 464 to 499 and exclusive-OR gate 462 can be any logical devices of knowing; Yet high speed TTL device is specially adapted to realize the present invention.The realization that utilizes other logic families also is tangible for the people of the common skill with prior art.The high frequency oscillation generator of Fig. 4 b is stated as the example of one type the digital high frequency oscillation generator of realizing digital oscillator of the present invention satisfactorily.It is apparent that for the person skilled in the art many other digital high frequency oscillation generators also can utilize satisfactorily, " to bleach " in order making, to provide the cycle of providing to be at least the digital high frequency oscillation generator of the pseudo random sequence of the long uniform L figure place of probability density of 2 sampling points by the position phase noise of cutting the top generation.
As shown in Figure 3, intermediate frequency (IF) filtering part is with the speed reception of the 20M sampling point/second data from analog to digital converter, the same direct current of the signal that receives (zero intermediate frequency frequency) is mixed, carry out low-pass filtering to the received signal with the acquisition desired signal, and signal is delivered to the tail end 120 of Fig. 1 with the sample rate that (sharply) reduces.In example preferably, the reduction of low-pass filtering and sample rate is not a separate operation; On the contrary, when unwanted signal (if do not remove it can cause obscure) was filtered, sample rate reduced gradually between each filter segment.Unique sample rate work with input (enforcement of example described here is f among giving birth to case
s=20MH
2) filtering partly is first part.Only other circuit with that sample rate work is quadrature local oscillator (LO) and frequency mixer.Like this, this high speed circuit selects the operating rate of part that 3 upper limits are set for all digital zero IF.The mutual modulation problems that takes place for sample-and-hold circuit and analog to digital converter with front end reduces to signal minimum and the enough bandwidth of permission acceptance, and high-speed cruising is very important for digit receiver of the present invention.
Fig. 5 a is Fig. 3 " fast ", narrowband low- pass filter 308 and 310 block diagram.Quadrature local oscillator 302 and frequency mixer 304 and 306 are no feedback circuit (being mainly ROM and multiplier), and they are suitable for the parallel mode of streamline or other form to improve its speed.Yet, make circulation (infinite impulse response) filter because of lining low pass filter part 308,310, they can not constitute streamline and go raising speed.Their speed is by determining along the maximum delay in sealing (feedback) path.For the used low pass filter of the present invention, this highway section comprises two digital adders and a latch.Be exactly the modulus sampling rate has been limited in this highway section, thereby total limited digital receiver performance.Because realize very high-speed problem, Design of Filter becomes two staggered 10MH
2The TTL filter.The problem of obscuring common and that use low sampling rate to accompany alleviates by increasing near undesirable filtering limit zero point.
Shown in Fig. 5 b, " fast " low pass part 546 of Fig. 5 a resolves into two Half Speeds and partly adds compound filter.This improve to allow the digital IF part can be with the twice operation of the speed of other method, and the performance of digital receiver of the present invention is improved." decomposition " of the present invention filter shows in conjunction with Fig. 3 and 5.Other filter decomposition technique has obtained discussing, as at M.Bellanger, G.Bonnerott and M.Coudreuse are at IEEE TRANSACTIONS ON ACOUSTICS, SPEEH, AND SIGNAL PRO CESSING, VOL.ASSP-24, NO.2, deliver among the April1976 " by the polyphase network digital filtering: sampling rate change and bank of filters in application (Digital Filtering by Polyphase Netivork:Application to Sample-Rate Alteration and Filter Banks) " article in.
Note, because two Half Speed circuit need approximately equal power (secondary power of ignoring compound filter) with single full speed circuit, so though decomposition needs to increase hardware, it just increases the consumption (with cmos device) of power on paper.
Fig. 6 describes decomposable process in detail with some map of magnitudes.Particularly, Fig. 6 a has shown that first the two poles of the earth part of original pattern is for input sampling rate f
sBe 20MH
2Response.Fig. 6 b has shown " after the decomposition " characteristic, and it is two 10MH
2The result of part, Fig. 6 C has shown the response of " compound " filter of back simultaneously.At last, Fig. 6 d has shown the combination (being cascade) of Fig. 6 b and Fig. 6 c, except to 10MH
2" trap " (it is at f
s/ 2 eliminate near the result at the zero point of two limits) outside, it in fact can not be differentiated with Fig. 6 a.
Decomposing filtering can be expressed as follows:
Wherein x and y are respectively the multiple input and output (being that they all have real part and imaginary part) of filter.And, h
dBe the multinomial coefficient that decomposes filtering, and N
DThe=2nd, the rank of former full speed filter.Because the 20MH that decomposes
2Filtering can be expressed as z
-2(as showing in next part), it can be by 10MH
2The circuit realization of form, wherein
h
d(i)=h
d(i/2) i is an even number
0 i is an odd number
H wherein
hIt is former high-speed coefficient.
Like this, the filtering of decomposition can be expressed as again:
Variable i is become 2j is simplified to summation:
From this formula, the input x of filtering and output y can be divided into two-way along separate routes, shown in Fig. 5 a:
x
（Y）（m）＝x（2m+Y）
y
（Y）（m）＝y（2m+Y）
Y=mod(n wherein, 2) 0,/00 0,1
Get with the n among the decomposition filtering summation above the 2m+1 replacement:
At last, two decomposition filtering that separate (Y=0,1) can be expressed as:
Suppose that desirable filtering has limit z=z
pThen corresponding filtering characteristic can be expressed as:
H＝（1-z
pz
-1）
-1
If this limit is outside one's consideration 180 " repetition ", then can get following characteristic:
H′＝〔（1-z
pz
-1）（1-z
pe
jπz
-1）〕
-1
＝〔（1-z
pz
-1）（1+z
pz
-1）〕
1
＝（1-z
2 pz
-2）
-1
Because the gained characteristic has Z
-2Form, so it can (resemble with forward part show) resolve into two Half Speed filtering, each has limit z
2=z
2 p
Low-pass filtering in the digital zero IF selectivity instrument of the present invention partly realizes that with following form this form can be write as the form of coefficient a and b, wherein b=ca.For limit to z
p, z
* p, wherein:
z
p＝（1-d）e
jq（d，q＜＜1）
Coefficient is:
a @ 2d
And
b＝d
2+q
2
For Half Speed filtering, limit is to being z
2 p(z
2 p)
*Because
z
2 p＝〔（1-d）e
jq〕
2
@（1-2d）e
j2q
Like this, the form of the coefficient of situation and obtaining at full speed in the time of can analyzing situation at full speed for the coefficient of Half Speed filtering:
a′＝2（2d）
＝2a
And
b′＝（2d）
2+（2q）
2
＝4（d
2+q
2）
＝4b
This design is described in Fig. 5 b.Second order IIR(infinite impulse response) filter is at IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS, VOL CAS-27, NO.12, Agarial among the Dec 1975, the article of A.C.Burrus C.S. " has low-down selectivity and the new circulation numeral filter structure " description in (New Recursive Digital Filter Strucurs Hauing Very Low Sensitivity ang Roundoff Noise) of the noise that rounds off.Filter structure by Agarwal and Burrus suggestion is improved for the delay that will prolong whole feedback loop reduces to minimum for purposes of the present invention.Filter structure of the present invention is described in Fig. 7.
All digital filtering structures mainly are made up of same three parts: adder, multiplier, and delay circuit (being generally latch or RAM).The factor that influences the digital filtering performance is all relevant with the following fact, and the different parameters of filtering is digitized, that is, they have limited accuracy, rather than the unlimited precision in analog filtering.The limited precision of digital filtering mainly provides three main performance influences, all must be controlled in any digital filtering instrument.
It is one of influence that coefficient rounds off.The constant coefficient of finding in digital filter is determined its frequency response.The result who makes these coefficient roundings them be expressed as binary limited integer has caused in the filter response permanent, the variation that can indicate.This same RLC(resistance inductance capacitance that changes analog filtering) value is similar, yet, not resembling in analog filtering, digital filtering is subjected to the infringement of variations in temperature.Usually, the Q value of filter high more (being that bandwidth is narrow compared with sampling rate), frequency response is subjected to the influence that coefficient rounds off and changes just greatly more, unless used special structure.Because IF filtering usually is very narrow band, or high Q value filtering, to select be critical so filter structure careful filled out.
The noise that rounds off is another performance characteristics that must control in the digital filtering.The data that are input in the digital filter have been rounded to limited binary number, and filter rounding off of almost adding always of fixed point place really.Above-mentioned rounding off operates in generation error or noise in the digital filter.For example, if the digital word length of using in the filter is 16 and coefficient table is shown within 10, then each multiply operation need produce 25 and multiply each other, and it must be rounded to 16 before the result is failed back memory.
The last main influence that will control in digital filtering is the overflow level.Data sampling be illustrated in the fact within spacing mean exist with filter in each node maximumly allow absolute value accordingly, if surpassed it just cause overflow phenomena (if used 2 complementary binary computing would be generally around).This maximum allowable number is determined the dynamic range of filter according to the described noise level coupling of rounding off in front.
Some common structures are used to realize digital filtering.Directly method for designing is that direct-type filter segment single order and second order is cascaded up, up to reaching required filtering progression.The advantage of this method is simple, regular, and is easy to actual Design of Filter.Yet usual way also suffers mainly from realizing that narrow-band filtering needs high accuracy (as 16) filter factor to represent the infringement of this fact.This need carry out very complicated multiplying (for example 16 in the feedback loop of filtering part.20).These multiplyings have added serious speed and time restriction to the running of filter.In addition, pile line operation (improving the common technology of logical circuit speed) can not be used in the feedback control loop.At last, high accuracy, high-speed gear consume sizable power.
Refer now to Fig. 7, describe digital low-pass filtering part 700 with the form of block diagram.The filter that is used for DZISS is that recursive filter is (in the key point feedback of Filter Structures, calibration, and summation output signal), it has narrow bandwidth, and be optimized at a high speed and be muting sensitivity to parameters numberization noted earlier to the adverse effect of digital filtering.Second order narrow-band low pass infinite impulse response (IIR) filter of Fig. 7 is used in " fast " low pass filter that decomposes among Fig. 5 b, and it is with the speed operation of analog to digital converter.Decomposition is useful in realizing this high speed of service, but needs to increase hardware: two second order IIR partly replace one and unwanted second-order F IR part of past.
Wave digital lowpass filter 700 provides by the square frame 550 of Fig. 5 b and 552 functions of describing.Wave digital lowpass filter comprises that 704,708,712 and 716, two of four digital adders (2 complement codes) postpone or latch 710 and 718 and two binary shift devices 706 and 714.Described during digital quadrature local oscillator 400 as discussed earlier, the low pass filter 308,310 and 312 and 313 that resembles the independent connection of describing among Fig. 3 is long number character code rather than monofilament cords.
Be added to the in-phase input end 702 of digital adder 704 to the input signal of digital filter 700.Take from digital delay 718 for second anti-phase input of digital adder 704, it is from output 720 feedbacks of filter circuit.Poor (2 the complement codes) that digital adder 704 obtains then are added to the input of gain unit 706, and it provides first and signal after the displacement as an input of digital adder 708.
706 time delays of following.
Fig. 8 is the compound finite impulse response (FIR) of second order (FIR) filter of band trap, and its sample rate is half of the used sample rate of the quick low pass filter of the decomposition among Fig. 5 b.Draw as Fig. 5 b, be coupled on the output 720 of filter 700 for the input 802 of filter 800.According to Fig. 8, digital filter 800 comprise be coupled to respectively digital delay 810 and 814 and digital adder 812 and 816 on numerical shift device 804,806 and 808.Numerical shift device 804,806 and 808 is used 1/4,1/2 and 1/4 gain respectively, to realize the filter that arranged two zero points of half sample frequency on unit circle.These numerical shift devices make input 802 move right 2,1 and 2 respectively.Because above-mentioned " displacement " can realize by arrange the path of line with suitable manner, so these gain operations do not consume actual time and do not need actual hardware.First part and use the calibration output of the gain unit 806 that obtains by delay cell 810 to import as second in adder 812, to form as previous (or last) calibration output of first input and gain unit 804.Similarly, obtain exporting 818 as second part and, to be the calibration output of using the gain unit 808 that is obtained by delay cell 814 import and form as previous (or last) first part of first input and adder 812 with as first for it.The transfer function of this filter can be written as
H（Z）＝Y（Z）/X（Z）＝（1/4）〔1+Z
-1（2+Z
-1）〕
Be to calculate output, relatively two summations in the IIR part and one latch, and the FIR filter only need once be sued for peace and a latch operation, so the FIR composite filter is easy to full input sampling rate (20MH
2) operation.Another design allows adder with lower sample rate operation by adopting additional control circuit.By introducing filtering operation along separate routes, promptly only calculate the required output of filtering part with the sample rate operation of lowering of back, just allow the FIR filter to move slowlyer.In cmos device, power consumption also reduces when the speed of service reduces usually.Like this, the power consumption of FIR composite filter can some control circuits be that cost reduces just.
" fast " filter 308 of Fig. 3 and 310 and " at a slow speed " low pass filter 312 and 313 between, wish to realize the reduction of sample rate, or along separate routes.Such as is well known in the art, the attenuation that is provided by " fast " low pass filter is provided the possible degree that sample rate reduces.For example, if use 20MH
2Input sampling rate, and " fast " filter realizes by having as the resolution filter of the listed coefficient of table 3, then 2MH
2Output sampling rate may be utilized, the protection of obscuring that played 100Db that provides by " fast " filter is provided.
" at a slow speed " low pass filter 312 and 313 can be real by what two limit filtering part
Filtering part a c speed (MHz)
(decomposition) 2 fast
-82
-920
At a slow speed 12
-62
-22
At a slow speed 22
-62
-32
At a slow speed 32
-62
-42
Table 3
Existing.For example, if use three grades, every grade has Fig. 9 a, listed coefficient in the structure of 9b and 9c and the table 3, and then sample rate can reduce to 80KH by 2MHz
2, wherein at a slow speed 1, at a slow speed 2 and at a slow speed 3 respectively corresponding to Fig. 9 a, 9b and 9c.
Another design of saving hardware relates to staggered homophase and quadrature sampling stream and with three grades of time-division multiplex filtering.This needs filter doubling the operating rate operation of non-multichannel design, but because sample rate has reduced by 10 times than fast electric-wave filter, so 1/5th operations that multi-channel filter still can first order filtering speed.
Fig. 9 a is a block diagram of cutting apart time of being used in realization " low speed " low pass filter first time-division multiplex secondary low pass IIR filtering stage in the multichannel filtering.Fig. 9 a to 9c representation class is similar to the time-division multiplex scheme of filter construction shown in Figure 7.The main distinction between the multichannel scheme of the structure of Fig. 7 and Fig. 9 is that delay cell has been doubled on length.Like this, do not use Z
-1Unit (being implemented in single latching in the hardware) and use Z
-2The unit, they are formed by two series of latches.The effect of this structure is each homophase of filter alternate treatment and quadrature sampling.In the discussion of back, the operation of Fig. 9 will be gone through.After handling by digital filter 900a, signal be coupled to the second filtering stage 900b and to after the 3rd filtering stage of describing by Figure 90 0c.Digital filter 900a, total filter structure of 900b and 900c is identical, so only go through digital filter 900a.
Yet respectively shown in Fig. 9 a, 9b and 9c and table 3, digital filter 900a, the data path of 900b and 900c and filter response change between at different levels very little.
Wave digital lowpass filter 900a comprises four digital adders (2 complement codes) 904a, 908a, 912a and 916a, four digital phase-locking storages (per two in 910a and 918a) and two binary shift device 906a and 914a.Be added on the in-phase input end 902a of digital adder 904a for the input signal of digital filter 900a.Take from the digital phase-locking storage to 918a for second anti-phase input of digital adder 904a, it is by the output 920a feedback of filter circuit.Poor (2 the complement codes) that then digital adder 904a obtained are added on the input of shifter 906a, and it provides first and signal after the displacement as the input of digital adder 908a.
Shift unit 906a with all positions of the numeric data code of digital adder 904a output to the right (promptly to lowest order) move the Nc position, be equivalent to multiply by and equal 2
-NcCoefficient.This displacement can be by suitable selection the path of data circuit from digital adder 904a to adder 908a realize.Like this, promoted the realization of the high speed of service of digital filtering part 900a, this is not resemble the time delay of following with shifter 906a because do not exist in the coefficient multiplication of being realized by common multiplier circuit.
The output of digital adder 908a before two sampling times that digital adder 908a keeps latch to 910a is added on first and the signal of shift unit.Then, the output of the digital adder 908a of latch 910a maintenance is added on the digital adder 912a.Take from latch to 918a for second anti-phase input of digital adder 912a, it takes from the output 920a of digital filter as previously mentioned.The result of digital adder 912a is added on the shifter 914a, and it is coupled on the digital adder 912a.Shifter 914a is the Na positions that move right, all positions of the numeric data code of digital adder 912a output, is equivalent to multiply by equal 2
-NaCoefficient.Because do not cause time delay, so shifter 914a has also promoted the realization of the high speed of service.Corresponding to the frequency response of parameter N c and the Na control figure filtering part 900a of shifter 906a and 914a, can be selected to produce the response that is suitable for intended application respectively.Digital adder 916a being added in the previous output of the 916a that delayer 918a keeps after with second displacement with signal.The output of delayer 918a also is the output of digital low-pass filtering part 900a, and has been added to the restriction of the input signal 902a of the input of circuit 904a the expression of bandwidth before the representative.
Clearly, for the people who knows prior art, can between partly each of four (all) low-pass filtering, use sample rate decay more gradually.The decay of gradually sample rate provides obvious superiority, and it provides very big flexibility in to the ratio of output sampling rate setting up total input.According to the restriction to output sampling rate, its allows almost at random to set up the modulus sample rate, with the passband coupling of required preselector.In the output of the third level (with last) " at a slow speed " low-pass filtering part, enough decay have been added on the passage of higher frequency, make because obscuring of causing of the shunt from 2MHz to 80KHz do not disturb desirablely, and the center is about the frequency band of zero-frequency.
After selecting part 114 Filtering Processing and shunt through the high speed of Fig. 1, the digital signal of recovery comprises the receiving digital signals with quadrature component.The phase information that the orthogonal property of the digital signal that receives guarantees to be present in the original RF signal is being preserved through obtaining after the processing chain.The quadrature digital signal that receives is coupled on the end 120 of the digital receiver among Fig. 1, and it is convenient to as previously mentioned by programmable, general Digital Signal Processing I.C.(integrated circuit) realize.Radio end 120 carries out required additional treatments, produces the digital baseband signal that is used to provide restore data or sound signal.In addition, radio end 120 can provide final demodulation filtering and the demodulation reprocessing to restoring signal.Figure 10 and 11 has described the optionally digital filtering structure that is suitable for carrying out final pre-demodulating in the scope of Digital Signal Processing I.C. in detail.Following Figure 12 has described the technology that spirit according to the present invention is suitable for demodulation FM signal in detail.
Figure 10 has shown the acyclic filter 1000 in five rank, and it provides additional decay to make sample rate further drop to 40KHz by 80, only causes the aliasing distortion on the insignificant required frequency band simultaneously.Because this filter is gone up operation at the quite low output sampling rate (second mining sample) of 40KHz, may in general digital signal processor, realize it.Above-mentioned processor typically is suitable for multiplying 1004,1010,1016,1026,1030 and 1036 and add operation 1006,1012,1020,1024 and 1032 pipelinings very much, so select " directly type " filter structure.
Figure 11 has shown the direct type filter structure that four limits and four zero points are arranged, its be used to flatten logical strainer response of composite received machine filter.It can be by a series of multiplyings in nextport universal digital signal processor NextPort 1104,1112,1118,1120,1126,1132,1140,1146 and 1150, add operation 1106,1114, and 1116,1122,1108,1130,1136 and 1144 realize.Because single precision (general 16 bit word lengths) computing can not provide light radio application required enough dynamic ranges, be necessary in the DSP instrument, to use double-precision arithmetic.Clearly, for the people who knows prior art, the final different bandwidth of part of selecting can obtain by selecting filter factors different among the terminal DSP program controlly.The different choice bandwidth also can be by using different reduction sample rates, or by obtaining at multiplier-less low-pass filtering different wired gain unit in partly (for example by to a selector).
Figure 12 is the block diagram with the digital FM demodulator of digital radio structure compatible of the present invention.In fact, digital demodulation is a task of wherein being finished by digital signal processor I.C..According to Figure 12, amplitude limit part 1202 comprises the calibration level 1204 with homophase passage inverse operation generator 1210 and product multiplier 1212, and the inverse of the homophase of calibrating thereon and rotating (I ') component is with the multiply each other item of tangent value of the phase angle that produces the signal phasor sampling equal to calibrate and to rotate of anti-phase (Q ') component of calibration and rotation.The effect of digital multiplier 1212 is that desirable restriction is carried out in any variation of the input signal amplitude of the vector that possible exist.The tangent of the item representative rotation of passing through by digital multiplier and the signal phasor sampling of calibration.This is handled by cotangent generator level 1214; Its output equals to rotate and the phase angle of the signal phasor calibrated.When this amount is added to by digital adder 1214 from the approximate position of approximation position phase accumulator 1206 outputs mutually on the value, then it represents total phase angle that the input signal vector is sampled.The difference signal that is created in the output of the digital adder 1218 between the negative value of the phase angle of signal phasor sampling at that time and the delay output that digital delay 1220 produces represent the 1 output demodulating information of sampling.
Figure 13 a is the principle of describing the phasor in the scope of the invention in detail to 13c.With reference now to Figure 13 a,, the function of scaler 1204 be the amplitude that will change the input signal vector amplitude calibration shown in the shadow region.Shown in Figure 13 b, approximation position phase accumulator 1206 is determined the approximate phase angle of signal phasor, φ c, and the output of cosine generator level 1212 equals the precise phase of signal phasor, φ f.Signal phasor φ f is limited in by vector rotation-π/4≤φ f≤+ scope of π/4 in (shadow region of Figure 13 b).2 amounts of this that produces in the output of digital adder 1214 sum is represented total phase angle of input signal vector sampling, φ (n).The difference △ (φ (n)) (shown in Figure 13 c) between the phase sampler φ (n-1) that at that time position phase sampler φ (n) and digital delay 1220 produce that is produced by digital adder 1218 represents the demodulation output information of a sampling.Typical case after FM detects moves, and represents the sample streams of the output information of demodulation can carry out low-pass filtering to remove the noise outside inromation bandwidth.
It is apparent that for the one skilled in the art digital demodulator of describing among the last figure can be with discrete hardware digital multiplier, adder, register waits to be realized.Digital demodulator of the present invention is particularly suitable for the instrument that has one group to be known as the device of digital signal processor.With the various digital signal processors of knowing, as by (the One Natick Executive Park of U.S. NEC electronics corporation, Natick, Mass.01760) NEC D7720, or by the Texas Instruments Inc (P.O.Box 225012, Dallas, Texas 752265) TMS32010 that provides.Digital signal processor generally comprises hardware high-speed figure multiplier, and also with good grounds predetermined algorithm is handled the ability of digital data stream.
Figure 14 a and 14b are the flow charts that the background process of the present invention that realizes with digital signal processor is described in detail in detail.In the present invention of various kinds, homophase and inversion signal vector component will be expressed as component I and Q respectively hereinafter.Algorithm of the present invention starts from 1402, and it makes digital signal processor carry out judgement 1404 to determine the symbols of I component.On the result based on judgement 1404, the symbol of Q component is by judging that 1406 and 1448 determine.Then, the difference of I and Q is by item 1410,1408, and 1472 and 1450 determine that they comprise Q-I respectively, I-Q, the value of Q-I and Q+I.The symbol of accordingly result is respectively by judging that 1430,1412,1474 and 1452 determine.On these results' basis, know component (I or Q) with big absolute value, and the eight/one-period at signal phasor place (promptly multiply by π/4) also cicada.If this value is less than zero, it is respectively by item 1420,1486, and 1476 and 1462 replenish.The maximum value of passage of representing I or Q is respectively by item 1442,1432, and 1422,1414,1488,1478,1466 or 1454 advance program stacks, and the amount of being expressed as SMAX afterwards.Amount SMAX uses 1444,1434,1424,1416,1490,1480,1466 or 1456 to call the calibration subprogram and determine to affact calibration amount in the sampling of input signal vector respectively.The calibration subprogram is returned the signal phasor component I and the Q of correct calibration.Then, the approximate position of locating based on eight/one-period of signal phasor is worth mutually respectively by item 1446,1436, and 1426,1418,1492,1482,1468 or 1460 are stored on the temporary storage location.
This value is general's multiple of pi/2 radian always in the scope of-π≤φ (c)≤π.By item 1440,1428, the symmetry rotation is done in 1492,1484, the 1470 or 1460 approximate positions of the preserving negative value of value mutually to signal phasor by respectively then.Calibration that obtains and rotating signal component are expressed as I ' and Q ' signal phasor component later on.The effect of this vector rotation is the rotating signal vector, makes postrotational signal phasor component I ' and Q ' generation have the resultant vector of the phase angle within scope-π/4≤φ f≤π/4.
Figure 15 a and 15b are and the interrelate flow process of operation of the calibration subprogram described of top Figure 14 a.The value of calibration subprogram 1500 check SMAX is to determine to act on the correct calibration amount on signal phasor component I and the Q.The operation of this subprogram depends on resolution or is used for representing the figure place of signal phasor component.Explain in the scope of 32 long words that operate in expression signal phasor component of calibration subprogram.In the porch of 1502 calibration subprograms, the highest word (MSW) of amount SMAX is by judging 1504 with itself and zero balancing.If the MSW of SMAX is bigger than zero, then the small character (LSW) of SMAX is just abandoned, and by item 1506 with MSW and calibration threshold ratio.If the MSW of SMAX is predicated zero, then MSW will be abandoned, and by item 1528 with LSW and calibration threshold ratio.Use null check by judgement 1508 and 1530 respectively again by item 1506 and 1528 comparative results that produce respectively, if find that the result is greater than zero, then do not need to the calibration of signal phasor component, and subprogram is withdrawn into the some place of main program call subroutine 1500 by item 1550.If it is the word of the reservation of SMAX (being MSW or LSW) is littler than threshold value, then whether big by the order of magnitude of judging the word that 1510 and 1532 checks keep respectively than 255.This be equivalent to determine SMAX reservation word last 8 whether more than or equal to zero.If the result of this check is sure (being that the MSW of SMAX or LSW are greater than 255), then respectively with 1514 or 1536 with the word that keeps divided by 256.This has following 8 effect that last 8 of the word of the reservation of SMAX is displaced to this word.Less than 255, then need not make division if judge word that 1510 or 1532 result shows reservation.Be somebody's turn to do amount now and removed the value of selecting to be stored in the ROM tables of data as address bit, and retrieve calibration coefficient from ROM by item 1520,1540 by item 1516,1512,1538 or 1534.According to aforesaid judgement 1510 or 1532, coefficient is adjusted to the required right value of signal phasor component calibration.At last, the signal phasor component is scaled to correct zone for using to demodulator by item 1522 and 1524 or 1524 and 1546, and main program is got back to caller by item 1526 or 1548.
With reference now to Figure 16 a,, the contrary or inverse of I ' vector component is determined.This process is finished by 6 rank Chebysheo polynomial approximations are applied on function f (x)=1/x.
The multinomial that is used for approaching this function is:
f（x）＝（1/x）～
｛〔〔〔〔〔C7（x-1）+C6〕（x-1）+C5〕
（x-1）+C4〕（x-1）+C3〕（x-1）+C2〕（x-1）+C1｝
X=I ' wherein
And C1=+1.00000, C2=-1.0027
C3＝+1.00278，C4＝-0.91392
C5＝+0.91392，C6＝-1.62475
C7＝+1.62475
According to principle of the present invention, shift Q ' component onto the program stack storage area by item 1604, by item 1606 amounts of calculation (I '-1), then with its as the amount ARG.Coefficient C7 is taken out from data ROM by item 1608, by item 1610 usefulness ARG and it amount of formation TMP that multiplies each other.Coefficient C6 is taken out from data ROM by item 1612, is added to TMP by item 1614 and goes up the new value of generation to TMP.Repeat this pattern successively by item 1616 to 1644, up to from program stack storage, taking out Q ' component, and itself and the TMP generation of multiplying each other are similar to the amount of tan φ f=Q '/I ' by item 1650 by item 1648.The cotangent of the amount that is obtained by item 1650 just is determined.This process is by being applied to function Q f=arctan(x with 5 rank Chebyshev multinomials) go up and realize.
The multinomial that approaches this function is:
arctan（x）～
x｛〔〔〔〔C6（y）+C5〕y+C4〕y+C3〕y+C2〕y+C1｝
Wherein
x＝Q′/I′
y＝x
2＝（Q′/I′）
2
And, C6=-0.01343, C5=+0.05737,
C4＝-0.12109，C3＝+0.19556，
C2＝-0.33301，C1＝+0.99997
Amount x=(Q '/I ') shifts onto in the program stack storage by item 1652, and be designated as the amount y=x that gets root of ARG later on
2Value calculate by item 1654.In the chain that is similar to the similarity method that calculates previously described reciprocal value, by the cotangent value of item 1656 to 1692 amounts of calculation (Q '/I ').The result of this process is signed value, the phase angle of the signal phasor of representative rotation, or the accurate phase angle of input signal vector sampling.The approximation of the phase angle of input signal vector sampling is taken out from temporary storage location by item 1694, by item 1696 with it with the addition of cotangent result calculated.
This result represents the phase angle of input signal vector sampling.The phase angle φ n-1 of front input signal vector sampling is taken out from program stack by item 1700.Current position phase sampler is shifted onto in the program stack by item 1702.At last, calculate the poor of position, front phase samplers and present bit phase sampler, produce demodulating information m(n thus by item 1704) the output sampling.
Intelligence sample m(n) is included in demodulation tone signal in the sampled form.The demodulation tone signal can be converted back to analog form, and is amplified as previously mentioned, broadcasts by loud speaker.Perhaps, digital sound information can digital form be stored in and be provided with the back in the digital storage 123 and uses.In the data communication system (not shown), demodulating data symbols can be delivered to further process in the computer or deliver to terminal and show immediately.
In a word, digital radio receiver is described.Digital receiver of the present invention has been imagined whole digital receiver, and its handles the received signal that converts digital form after preselected in the output of antenna to.Receiver of the present invention comprises preselected device, high speed analog digital (A/D) transducer, the intermediate frequency (IF) with Digital Implementation of the signal output that is in substantially on the base band frequency is selected part and is separated nextport universal digital signal processor NextPort (DSP) integrated circuit that the filtering of mediation audio frequency is used.Other application of the present invention and distortion are clearly for the people who knows prior art under situation without departing from the spirit and scope of the present invention.
Claims (8)
1, handles the device of the broadband analog signal that comprises required narrow band analog signals basically with digital form, comprise
(a) receive and filter, it comprises and is used for receiving the broadband analog signal that comprises required narrow band analog signals and to the coupling device and the filter of its filtering;
(b) digitalizer, it is coupled with described filter, is used for periodically described broadband analog signal being sampled and converting thereof into the sampling wideband digital signal;
(c) digital device, it is coupled with described digitalizer, is used for selecting required sampling narrow-band digital signal from the sampling wideband digital signal;
It is characterized in that described digital device comprises digital quadrature oscillator arrangement, digital quadrature multiplier/mixer apparatus, digital quadrature narrowband low-pass filter device and is used for the device of the bandwidth of the described digital quadrature low-pass filter device of program control.
2, the device of claim 1, wherein said digital device comprise digital oscillation device, digital multiplication/mixer device and digital narrow-band filter means.
3, handle the method for the broadband analog signal that comprises required narrow band analog signals substantially with digital form, may further comprise the steps:
(a) reception comprises required narrow band analog signals and it is carried out filtering;
(b) periodically described broadband analog signal is sampled and convert thereof into the sampling wideband digital signal;
(c) from the sampling wideband digital signal, select required sampling narrow-band digital signal;
It is characterized in that this method also comprises:
(d) bandwidth of sampling narrow-band digital signal is carried out program control;
(e) the described sampling narrow-band digital of demodulation signal.
4, method as claimed in claim 3, wherein said selection step further comprise the digital oscillation signals according of generation, make the step of digital narrow-band filtering with the narrow-band digital signal of generation sampling with the wideband digital signal multiplier word oscillation signals according of sampling with the product signal of generation sampling with to the product signal of sampling.
5, be used to handle the basic digital device of narrow radio frequency (RF) signal that comprises required narrow band signal, comprise:
(a) receiving system, it comprises the antenna assembly that is used for receiving (RF) signal that comprises described broadband (RF) signal;
(b) filter, it and described antenna assembly are coupled, and are used for described broadband (RF) signal is carried out filtering;
(c) be coupled to the digitalizer of described filter, be used for periodically described broadband RF signal being sampled and converting thereof into the sampling wideband digital signal;
(d) digital device that is coupled with described digitalizer is used for selecting required sampling narrow-band digital signal from the sampling wideband digital signal;
It is characterized in that also comprising:
(e) be used for the digital processing unit of the described sampling narrow-band digital of demodulation signal, wherein said digital processing unit also comprises and is used for the device that additional character filtering and sampling rate reduce.
6, basic digital device as claimed in claim 5, wherein said digital device comprises digital quadrature oscillator, digital quadrature multiplication/frequency mixer and digital quadrature narrowband low-pass filter.
7, be used for handling with digital form basically the method for narrow radio frequency (RF) signal that comprises required narrow band signal, may further comprise the steps:
(a) receive (RF) signal that comprises described broadband RF signal;
(b) described broadband RF signal is carried out filtering;
(c) periodically described filtered broadband (RF) signal is sampled and convert thereof into the sampling wideband digital signal;
It is characterized in that:
(d) by producing a digital quadrature oscillation signals according, this quadrature oscillation signals according and sampling wideband digital signal be multiply by the long-pending signal of generation mutually, this long-pending signal is carried out the filtering of digital quadrature narrow-band low pass to produce sampling narrow-band digital signal, and described sampling narrow-band digital signal carried out program control, from the sampling wideband digital signal, select required sampling narrow-band digital signal;
(e) described narrow-band digital signal is carried out digital demodulation.
8, the method for claim 7, wherein said selection step further comprises the digital oscillation signals according of generation, producing the long-pending signal of sampling, and the utmost point signal of sampling carried out the step of digital narrow-band filtering with the narrow-band digital signal that produces sampling with the oscillation signals according of the wideband digital signal multiplier word of sampling.
Applications Claiming Priority (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US77173685A | 1985-09-03 | 1985-09-03 | |
| US751,913 | 1985-09-03 | ||
| US771,736 | 1985-09-03 | ||
| US06/751,913 US4675882A (en) | 1985-09-10 | 1985-09-10 | FM demodulator |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN86105333A CN86105333A (en) | 1987-05-20 |
| CN1010732B true CN1010732B (en) | 1990-12-05 |
Family
ID=27115506
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 86105333 Expired CN1010732B (en) | 1985-09-03 | 1986-09-03 | Digital radio frequency receiver |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN1010732B (en) |
| IL (1) | IL79902A0 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109729038B (en) * | 2018-12-25 | 2022-05-03 | 北京无线电计量测试研究所 | Agile broadband vector baseband signal generating device and method |
| CN112803960B (en) * | 2019-11-14 | 2022-06-21 | 瑞昱半导体股份有限公司 | Transceiver device |
-
1986
- 1986-09-01 IL IL79902A patent/IL79902A0/en not_active IP Right Cessation
- 1986-09-03 CN CN 86105333 patent/CN1010732B/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| IL79902A0 (en) | 1986-12-31 |
| CN86105333A (en) | 1987-05-20 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CA1304786C (en) | Digital radio frequency receiver | |
| US4893316A (en) | Digital radio frequency receiver | |
| US5504455A (en) | Efficient digital quadrature demodulator | |
| CN1795615A (en) | Digital transmitter and method | |
| CN1041679A (en) | The digital FM demodulator that sampling rate reduces | |
| CN87102565A (en) | Code device | |
| CN1158826C (en) | Method of clipping signal amplitudes in modulation system | |
| JPS5823100A (en) | Coding of voice signal | |
| CN1358348A (en) | Apparatus for receiving and processing radio frequency signal | |
| CN1156368A (en) | Delaydetector arrangement for detecting phase difference from phase modulation signal | |
| CN1010732B (en) | Digital radio frequency receiver | |
| CN1119802A (en) | Digital filter circuit and signal processing method for the same | |
| US6664819B2 (en) | Frequency synthesizer for improving a unique DDS characteristic | |
| CN1207846A (en) | Filtering in receiver that uses log-polar signal processing | |
| CN109787585A (en) | A kind of FIR filtering system based on nested type residue number system | |
| US5204683A (en) | Radar receiver for a radar having a digital beam forming antenna | |
| CN1611015A (en) | Receiving apparatus | |
| CN1104092C (en) | Method and device for analog signal sampling | |
| CN1698333A (en) | Timing extraction device and method, and demodulation device using the timing extraction device | |
| CN1622449A (en) | Digital frequency converter | |
| CA1318358C (en) | Digital radio frequency receiver | |
| JP3148053B2 (en) | Digital quadrature detector | |
| Dattorro | The Implementation of Digital Filters for High Fidelity Audio | |
| CN1262812A (en) | Time discrete filter | |
| US7139330B1 (en) | System for signal mixing and method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C13 | Decision | ||
| GR02 | Examined patent application | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C53 | Correction of patent for invention or patent application | ||
| COR | Change of bibliographic data |
Free format text: CORRECT: PATENTEE; FROM: MOTOROLA LTD. TO: MOTOROLA, INC. |
|
| CP01 | Change in the name or title of a patent holder |
Patentee after: Motorola Inc. Patentee before: Motorola Ltd. |
|
| C17 | Cessation of patent right | ||
| CX01 | Expiry of patent term |