CN101073082A - System and method to determine peak power demand in an integrated circuit - Google Patents
System and method to determine peak power demand in an integrated circuit Download PDFInfo
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- CN101073082A CN101073082A CN 200580042003 CN200580042003A CN101073082A CN 101073082 A CN101073082 A CN 101073082A CN 200580042003 CN200580042003 CN 200580042003 CN 200580042003 A CN200580042003 A CN 200580042003A CN 101073082 A CN101073082 A CN 101073082A
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Abstract
A method comprises receiving a description of a power distribution network of a circuit, defining at least one DC supernode in the power distribution network, receiving a logical description of the circuit, and determining at least one logic path in the circuit. The method further comprises traversing the at least one logic path in reverse and determining at least one input vector of the at least one logic path. The input vector describes a plurality of nodes in the logic path and a logic transition at an output node occurring in response to a combination of logic transitions at at least one input node in the at least one logic path. The method further comprises assigning a weighting value to each logic transition of each node in the at least one input vector, identifying at least one input vector with maximum contribution to drawing power from the power distribution network as indicated by the assigned weighting, and simulating an AC response of the identified at least one input vector with maximum contribution and identifying at least one logic path generating a peak load to the power distribution network.
Description
Present application for patent is advocated the right of priority of the 60/634th, No. 960 temporary patent application case of application on Dec 9th, 2004.
Technical field
The present invention relates to can be used for the AC electric current bottleneck in the distribute power network of recognition integrated circuit and determine the system and method for the peak power requirements in the integrated circuit.
Background technology
In integrated circuit, the distribute power network is with all component of current delivery in the circuit.The distribute power network can be crossed over a plurality of metal levels in the integrated circuit, and can arrange by the 3D grid pattern.More and more higher and switching frequency is more and more faster along with the device density of integrated circuit of today (especially microprocessor), it is extremely important that the distribute power network design is come into force.High-performance microprocessor of today (for example digital signal processor) has many more demands to power supply, and has forced stricter tolerance limit requirement.These digital signal processor designs have the low voltage requirement, so that reduce total power dissipation.Low voltage needs to transmit the distribute power network of the electric current of more increasing.Therefore, the accurate simulation of execution integrated circuit (IC) design is important to detect AC electric current bottleneck (AC current bottleneck).Too high so that can not realize that sufficient electric current satisfies local device electric current demand the time when the impedance of distribute power network, AC electric current bottleneck takes place.Because AC electric current bottleneck, the performance of integrated circuit and speed may sharply be demoted.
Summary of the invention
In an embodiment of this disclosure, a kind of method comprises: the description of the distribute power network of receiving circuit; In described distribute power network, define at least one DC supernode; Receive the logical description of described circuit; With at least one logical path of determining in the described circuit.Described method further comprises described at least one logical path of reverse traversal and determines at least one input vector of described at least one logical path.The a plurality of nodes in the described input vector description logic path and the logical transition at output node place, described logical transition takes place in response to the combination of the logical transition at least one the input node place in described at least one logical path.Described method further comprises: each logical transition that weighted value is assigned to each node in described at least one input vector; Identification as by the weighting that is distributed indicated to draw at least one input vector that power has maximum contribution from the distribute power network: and the AC response of at least one input vector of being discerned of simulation, and identification produces at least one logical path of peak load to the distribute power network with maximum contribution.
In another embodiment of this disclosure, the method for one group of vector that a kind of generation is used for the simulation of circuit comprises: the logical description that receives described circuit; Determine at least one logical path in the circuit; At least one input vector with described at least one logical path of reverse traversal and definite described at least one logical path.The node in the described input vector description logic path and the logical transition at output node place, described logical transition takes place in response to the combination of the logical transition at least one input node place.Described method further comprises: weighted value is assigned to each conversion of each node in described at least one input vector, wherein considers at least in part in dynamic load, conversion timing sequence and the impedance of described node place distribute power network and distribute described weighted value; With identification as by the weighting that is distributed indicated to draw at least one input vector that power has maximum contribution from the distribute power network.
In the another embodiment of this disclosure, a kind of upward face code has a kind of computer-readable media of method, and wherein said method comprises: the description of the distribute power network of receiving circuit; In described distribute power network, define at least one DC supernode; Receive the logical description of described circuit; With at least one logical path of determining in the described circuit.Described method further comprises described at least one logical path of reverse traversal and determines a plurality of input vectors of described at least one logical path, the a plurality of nodes in each equal description logic path of wherein said input vector and the logical transition at output node place, described logical transition takes place in response to the combination of the logical transition at least one the input node place in described at least one logical path.Described method further comprises: weighted value is assigned to each logical transition of each node in each input vector, wherein considers at least in part in dynamic load, conversion timing sequence and the impedance of described node place distribute power network and distribute described weighted value; With identification to draw a plurality of input vectors that power has maximum contribution from the distribute power network.Described method further comprises: make up described a plurality of input vectors through discerning to be used for simulation; With the described a plurality of AC responses with input vector of maximum contribution through identification of simulation, and identification produces at least one logical path of peak load to the distribute power network.
A kind of system comprises: the device that is used for the logical description of the description of received power distributed network and circuit; Be used for defining the device of at least one DC supernode at described distribute power network; Device with at least one logical path that is used for definite described circuit.Described system further comprises the device that is used for oppositely traveling through described at least one logical path and determines at least one input vector of described at least one logical path, wherein said input vector is described a plurality of nodes in the described logical path and the logical transition at output node place, and described logical transition takes place in response to the combination of the logical transition at least one the input node place in described at least one logical path.Described system further comprises: be used for weighted value be assigned to described at least one input vector each node each logical transition and identification as by the weighting that is distributed indicated to drawing the device that power has at least one input vector of maximum contribution from the distribute power network; Have the AC response of input vector of maximum contribution and identification produces device from least one logical path of peak load to the distribute power network with being used to simulate through at least one of identification.
Description of drawings
When reading, from following detailed description, can understand the various aspects of this disclosure best with accompanying drawing.What emphasize is that according to the standard convention in the industry, each parts are not to draw in proportion.In fact, for the clearness purpose of discussing, the size of each parts can increase arbitrarily or reduce.
Fig. 1 is the simplified block diagram of embodiment of system and method that is used for determining the peak power requirements of integrated circuit;
Fig. 2 is the process flow diagram of embodiment of method that is used for determining the peak power requirements of integrated circuit;
Fig. 3 is the synoptic diagram with the logical circuit of the example of the method that explains the peak power requirements that is used for definite integrated circuit;
Fig. 4-the 6th is with the synoptic diagram of the simple logic circuit of the example of the method that is described further the peak power requirements that is used for determining integrated circuit; With
Fig. 7-the 9th, the diagrammatic representation of definition of DC supernode and overlapping AC analogue window.
Embodiment
System and method as herein described can be used for the AC electric current bottleneck in the distribute power network of recognition integrated circuit.In case detect, design just changes, and for example can reduce the impedance of distribute power network and the effective capacitance of increase distribute power network, to improve the design of overall power distributed network.Make the worst case of effective capacitance, effective resistance and the load of the peak power requirements of circuit or distribute power network and estimate, so that identification AC electric current bottleneck.
Fig. 1 is the simplified block diagram of embodiment of system 10 that is used for determining the peak power requirements of integrated circuit.System 10 can operate with reception and contain relevant for the having the given data form or treat one or more files 12 of the description of development format of circuit design, and described circuit design for example is logical design, physical layout, static timing analysis, encapsulation and decoupling capacitor data etc.The performance analysis with execution distribute power network can be operated by system 10, and produces output 14, for example discerns the report and the curve map that the distribute power network are had the circuit of greatest requirements.
Fig. 2 is the simplified flow chart of embodiment of method 20 that is used for determining the peak power requirements of integrated circuit.Method 20 comprises first step 21, wherein the description of design of received power distributed network and/or integrated circuit layout.The distribute power network description can have any suitable format nowadays known or leaved for development.In step 22, in the distribute power network, define or discern one or more DC supernodes (super node).Power supply via the distribute power network with the current loading of DC current delivery in the integrated circuit.Yet when checking indivedual load, the electric current that is drawn by these loads is owing to load on V
SSVoltage level and V
CCChange between the voltage level and be similar to AC.Yet the load that adds together is many more, and the load current of accumulation just shows as and is similar to DC more.Show as the point that is similar to DC by the summation that the DC supernode is defined as the wherein electric current in the distribute power network, with problem be divided into from the DC supernode get back to the DC problem of power supply and from the DC supernode to the distribute power network on the AC problem of load.V
CCAnd V
SSNetwork passes through its shared capacitive coupling together, and can be the place separation of DC effectively for response in required load only.Therefore, can be with V
CCAnd V
SSNetwork is considered as two separate networks from power supply to the DC supernode.Because it is that wherein the local problem with very little influence falls in load and the electric capacity in a distance to local AC that AC descends, so can define one or more DC supernodes at each regional area, wherein (for example) regional area can comprise 100 to 1000 logic gates or loads.In general, can set predetermined threshold (for example 90%), make that 90% of wherein current distributing figure (current profile) in (for example) distribute power network is designated as the DC supernode for the node of DC waveform.
In order to determine the DC supernode in the distribute power network, should consider the type of load transfer to be studied.The figure of merit is a power ratio, and it compares AC for the DC at DC supernode place.Described ratio is high more, and the result is accurate more, and the size of common AC problem is big more.Thereby though can regulate described ratio by the definition that changes the DC supernode is that cost increases treatment capacity with the accuracy, is typically the DC supernode is defined as conversion from a distribute power network layer to another distribute power network layer.For instance, the DC supernode can be defined in integrated circuit and the encapsulation between interface.The DC supernode also can be in integrated circuit the point place between the metal layer.For instance, will use C4 or controlled collapse chip to connect under the situation of (Controlled Collapse Chip Connection) (being also referred to as flip-chip), the tie point between integrated circuit (IC) chip and the encapsulation pad can be appointed as the DC supernode.In the integrated circuit that will use leadframe package, can (for example) interface between two metal levels in the top be appointed as the DC supernode.
In step 23, receive the set of circuits logical network and describe 12.Circuit logic network description 12 can comprise the data about circuit design, and described circuit design for example is logical design, physical layout, static timing analysis, encapsulation and decoupling capacitor data etc.In step 24, in integrated circuit, discern the zone of being concerned about.The zone of being concerned about is will simulated in the integrated circuit (IC) logic to determine that peak point current draws the localized areas of (peak current draw).In order to increase the accuracy of simulation, also analyze and simulate adjoin be concerned about the predetermined portions of circuit in the zone in zone.Circuit in the adjoins region can be shared one or more DC supernodes with circuit in care zone, and therefore may influence or promote be concerned about the power demand of the circuit in the zone.
In step 26, the logical path in zone and the adjoins region is concerned about in identification.The path is the logic flow that is input to the output in the circuit from circuit.When each logic gate or load were switched with implementation and operation, it produced dynamic load to the distribute power network.The logic of track path is switched to determine load.The usual method that trace logic switches is to be transformed into new output state from input.Yet, in step 26, travel through logic tree (logic tree) backward from outputing to input.The output switching state is traced back to the input combination that to cause output state to change.For logical circuit of clock, can be in circuit latch locates further to divide the path, to reduce the degree of depth of logic tree to be traveled through.The path of being defined belongs to one in following six logic of class paths:
1. the master outputs to primary input (through path)
2. main outputing to latched point (output is caught)
3. latch a little to latching point (inner track)
4. latch a little to primary input (input capture)
5. the latch clock node is to major clock input (clock trees)
6. the latch clock node is to latching point (clock control)
Fig. 3 is the synoptic diagram that is used for illustrating at the logical circuit 50 of the step in circuit recognition logic path.Circuit 50 produces D from the output of 4:1 multiplexer 52
OUTSignal, described 4:1 multiplexer 52 receive and latch output and three data-signals (Data[2:0]) as its input from clock control H latch 54.The selection signal input that arrives multiplexer 52 is the output from 2:4 demoder 56.In the demoder output one is provided as the input that arrives impact damper 58, and it is provided as output signal HOLD.The input of demoder 56 is the output signals from clock control S latch 60 and 61, and clock control S latch 60 and 61 receives input Se12 and Se11 respectively.S latch 60 and the input of 61 clock are from the output of clock buffer 62, clock buffer 62 usefulness are come buffered clock signal CLK from the control signal that the output of clock control E latch 64 receives, and described clock control E latch 64 has signal ENABLE and imports as it.As shown in Figure 3, the logical path of circuit is:
1.Dout＜4:1 multiplexer＜H latch
2.Dout＜4:1 multiplexer＜Data[2:0]
3.Dout＜4:1 multiplexer＜2:4 decoding＜S latch [2:1]
4. maintenance＜impact damper＜2:4 decoding＜S latch [2:1]
5.S latch [2:1]＜clock buffer＜E latch
6.S latch [2:1]＜clock buffer＜Clk
7.E latch＜Clk
8.E latch＜Enable
9.H latch＜Clk
In above-mentioned tabulation,, do not repeat the logical path of share class like the path for for purpose of brevity.
In step 28, the traversal logical path to be determining input vector at each path, and in step 30, determines the weighting at input vector.Owing to may exist and cause the incident exported more than one group, described incident is weighted to determine the providing event group of peak load to the distribute power network.
Property example as an illustration, the phase inverter 70 with input A and output B as shown in Figure 3 will have input vector:
The vector 1:B/＞＞A
The vector 2:B＞＞A/
The indication of this symbolic notation, the logical circuit of being made up of phase inverter will have the input vector shown in above.Vector 1 indication is as input node A loading V
SSThe time, output node B loads V
CCOn the contrary, vector 2 indications are as input node A loading V
CCThe time, output node B loads V
SS
Second illustrative example as shown in Figure 4 comprises three phase inverter 72-74 that are connected in series, wherein node C is as the input of first phase inverter 72, node D is as the output of first phase inverter 72 and the input of second phase inverter 73, node E is as the output of second phase inverter 73 and the input of the 3rd phase inverter 74, and node F is as the output of the 3rd phase inverter 74.Travel through described circuit conversely, the input vector of this simple anti-phase chain circuit is:
The vector 1:F/＞＞E＞＞D/＞＞C
The vector 2:F＞＞E/＞＞D＞＞C/
Each conversion for the node place has three weighting factors to consider and to use.First weighting factor is a dynamic load or from V
CCThe electric charge that draws (being expressed as the C-load).Second weighting considers how soon described conversion takes place, and is for example relevant with the time constant or the response time of distribute power network.This weighting is expressed as Q time=1/T-switches.The 3rd weighting be the distribute power network from the visible impedance of associated DC supernode, be expressed as Z-PDN.These three weighting factors are essentially pre-AC simulation " wave filter ", and it can discern system will be concerned about maximally related those input vectors of simulation of the circuit in regional and the adjoins region on every side with institute.Being used for the low weighting of locating to " node " of low conversion to height and height can be expressed as:
The W node /=C-load * Z-PDN*Q-time (rising)
The W node=C-load * Z-PDN*Q-time (decline)
Property example as an illustration at the weighting W of the node in the chain of inverters (Fig. 5) is:
WF/＝4，WF\＝1，
WE/＝2，WE\＝3，
WD/＝1，WD\＝1，
WC/＝0，WC\＝0
It should be noted that above-mentioned weighted value is to distribute arbitrarily, so that be illustrated more clearly in the notion of weighting.In this example, from V
SSBe transformed into V
CCNode F with 4 weightings, from V
CCBe transformed into V
SSNode F with 1 weighting.Peak load V
CCCan determine by following equation:
Supported V
CC=MAX (vector 1, vector 2)
＝MAX(WF/+WD/，WE/+WC/)
＝MAX(4+1，2+0)
=5 via vector 1
Peak load V
SSCan determine by following equation:
Supported V
SS=MAX (vector 1, vector 2)
＝MAX(WF\+WD\，WE\+WC\)
＝MAX(3+0，1+1)
=3 via vector 1
Therefore, input vector " vector 1 " is and the V that determines at this practical circuit
CCAnd V
SSBoth peak demand are maximally related.Therefore, vector 1 may be used in the simulation that AC that institute is concerned about circuit in the zone responds.
As another illustrative example, the logical circuit with two input nand gates as shown in Figure 5 (wherein nodes X and Y are input, and node Z is its output) has input vector:
Vector 1:Z/＞＞O (X, Y)
The vector 2:Z＞＞A (X/, Y/),
This symbolic notation indication is for exporting Z from V
SSBe transformed into V
CC, X or Y must take place; And for exporting C from V
CCBe transformed into V
SS, X/ and Y/ must take place.Therefore, vector 1 can further be expressed as following reverse amount:
1.Z/＞＞X\.Y\
2.Z/＞＞X, Y-; The load of Y-reaction attitude is 0
3.Z/＞＞X-, Y; The load of X-reaction attitude is 0
4.Z/＞＞X/，Y\
5.Z/＞＞Y/，X\
Symbolic formulation method Y-and X-represent respectively not change among Y and the X.Oppositely amount 2 and 3 can not increase dynamic load in essence, because when their input was not switched, these vectors can not add any dynamic power to model.Therefore, can in the antilogical tree, use oppositely amount 1.The vector 2 of NAND gate circuit defines following reverse amount:
1.Z\＞＞X/，Y/
2.Z＞＞X/, Y-; The load of Y-reaction attitude is 0
3.Z＞＞X-, Y/; The load of A-reaction attitude is 0
In step 32, be concerned about all maximum input vectors of the logical path in regional and the adjoins region are combined into a vector, to prepare to carry out a dry run.It should be noted that each logical path all can produce maximum input vector more than when above input vector of weighting similarly.In addition, should check logical path and its input vector are to determine whether some logical paths in the described logical path are the mutual exclusion path, and the sequential of logical path is such in the mutual exclusion path: they will be never switch simultaneously or in the time constant of a certain number of distribute power network.If logical path does not switch in the window (it can be set to three time constants of distribute power network) at one time, they are quadrature path rather than additivity path so, and should not be combined in together for simulating.Should carry out independent dry run in the case.
Can further consider " window " size of simulation.For instance, in Fig. 7, define and have 49 (49) individual V
CCAnd V
SSThe distribute power network 80 of DC supernode.Described DC supernode block is arranged to 7 * 7 matrixes.It should be noted that Fig. 7 has identical size for the purpose of demonstration notion and with the diagrammatic representation of regular fashion blocks arranged, and in fact do not require and so define the DC supernode.Can be at each n * m size windows operation AC simulates, and analogue window can be overlapping.For instance, as shown in Figure 8, each AC analogue window can be the 3 * 3DC supernode array with one (1) individual overlapping block.Required operation number is nine (9), so that entire chip is simulated.As shown in Figure 9, for another example, each AC analogue window can be the 4 * 4DC supernode array with one (1) individual overlapping block.Required operation number is four (4), so that entire chip is simulated.Overlappingly be not limited to a block width.For instance, available 3 * 3 overlapping AC analogue window with two (2) individual blocks come identical DC supernode is simulated.This will need 25 (25) individual dry runs.Overlapping amount does not need to drop on the block border.For instance, available 4 * 4 overlapping AC analogue window with 2.5 blocks are moved simulation, and this causes nine (9) individual dry runs.
From aforementioned content as seen, analogue window is big more and overlapping more little, cause the number of dry run few more, and the simulated power distributed network is saved trouble more.Therefore, should make the big and overlapping as far as possible amount minimum of window size,, so that acceptable result to be provided.
In step 34, use the maximum input vector of in step 32, collecting to carry out the AC simulation.When carrying out for the first time the AC simulation, at each DC supernode, the medium impedance point that window can the distribute power network is the center.For each optional iteration AC dry run subsequently, under the situation of given current distributing figure, can select or regulate the analogue window border based on the mathematics center through weighting of the load in the distributed network.Using conventional method to carry out the DC simulation descends to determine maximum DC.For example can use the conventional simulation instrument of SPICE, PRIMEPOWER and REDHAWK to carry out AC and DC simulation.
In step 36, can carry out a certain simulation back " filtration ".For instance, can carry out filtration so that the false edge effect of analogue window minimizes.Can minimize or eliminate the edge effect of window operation by some data " filtration " in the overlapping region between the analogue window are come out.For instance,, have the overlapping of three (3) individual DC supernodes, so just abolish the part of overlapping region if the size of AC analogue window is 5 * 5.For instance, the zone of the outside of the electric mid point of the overlapping region of defeasible each dry run.In this example, can from the analog result of each operation, filter out the part that width is 1.5 blocks.Decide on the certain power distributed network, can use other filter width.
In step 38, system can produce the data about vector in the dry run that produces maximum decline distribution plan at each or vector combination.Output can comprise the data of report, curve map and other form, and described data make construction brigade can discern circuit or the logical path that draws maximum current from the distribute power network.Can set a certain threshold value, make that only discerning those in report draws input vector than the more electric current of described threshold value.Then, can modify,, maybe can make the decision of allowing that peak value descends, belong in the tolerance interval because described peak value descends so that correct described problem to circuit design.
Although described the embodiment of this disclosure in detail, it will be understood by one of ordinary skill in the art that they can make various changes, replacement and change to this paper under the situation of the spirit and scope that do not break away from this disclosure.Therefore, all this type of change, replace and change is all wished to be included in the scope as this disclosure of being defined in the appended claims.In claims, device adds the function clause wishes to contain the structure that this paper is described as carrying out institute's recited function, and not only contains structural equipollent, and contains impartial structure.
Claims (45)
1. method, it comprises:
The description of the distribute power network of receiving circuit;
In described distribute power network, define at least one DC supernode;
Receive the logical description of described circuit;
Determine at least one logical path in the described circuit;
Oppositely travel through described at least one logical path, and at least one input vector of definite described at least one logical path, described input vector is described a plurality of nodes in the described logical path and the logical transition at output node place, and described logical transition takes place in response to the combination of the logical transition at least one the input node place in described at least one logical path;
Weighted value is assigned to each logical transition of each node in described at least one input vector;
The weighting that distributed as described of identification indicated to drawing at least one input vector that power has maximum contribution from described distribute power network; With
Simulate the AC response of described at least one input vector, and identification produces at least one logical path of peak load to described distribute power network with maximum contribution through discerning.
2. method according to claim 1, it comprises that further at least one in the described circuit of identification be concerned about the zone, and determines that at least one is concerned about regional at least one interior logical path described in the described circuit.
3. method according to claim 1, its further comprise identification adjoin described at least one be concerned about regional zone, and with described adjoins region be included in described at least one be concerned about in the zone.
4. method according to claim 1 determines that wherein at least one logical path comprises the logical path of determining to have the output that arrives at least one primary input.
5. method according to claim 1 is determined wherein that at least one logical path comprises determining to have to arrive at least one and latch the logical path of output a little.
6. method according to claim 1 is determined wherein that at least one logical path comprises determining to have to arrive at least one and latch a little a little the logical path of latching.
7. method according to claim 1 is determined wherein that at least one logical path comprises and is determined to have a little the logical path of latching that arrives at least one primary input.
8. method according to claim 1 determines that wherein at least one logical path comprises the logical path of determining to have the latch clock node that arrives the major clock input.
9. method according to claim 1, wherein definite at least one logical path comprise determines to have the logical path that latch clock node is a little latched in arrival.
10. method according to claim 1, wherein assign weights comprises that the dynamic load of considering described node place at least in part distributes described weighted value.
11. method according to claim 1, wherein assign weights comprises and considers that at least in part the time quantum that carries out described logical transition at described node place distributes described weighted value.
12. method according to claim 1, wherein assign weights comprises and considers that at least in part the impedance that described node place turns back to the DC supernode of described distribute power network distributes described weighted value.
13. method according to claim 1, it further comprises the DC response of described at least one input vector with maximum contribution through discerning of simulation; With described DC response and described AC response addition; With identification at least one logical path to described distribute power network generation peak load.
14. method according to claim 1 determines that wherein at least one logical path comprises a plurality of logical paths of determining in the described circuit; Determine a plurality of input vectors at each logical path; Weighted value is assigned to each logical transition of each node in described a plurality of input vector; Identification is to drawing a plurality of input vectors that power has maximum contribution from described distribute power network; With the combination described a plurality of input vectors of discerning be used for the simulation.
15. method according to claim 1, it further comprises and defines analogue window size and the overlapping width that is used for described simulation.
16. method according to claim 15, it further comprises by operation filters out data and comes the treatment of simulated result from the zone of the electric mid point outside of described overlapping width at each analogue window.
17. a generation is used for the method for one group of vector of breadboardin, it comprises:
Receive the logical description of described circuit;
Determine at least one logical path in the described circuit;
Oppositely travel through described at least one logical path, and at least one input vector of definite described at least one logical path, described input vector is described the node in the described logical path and the logical transition at output node place, and described logical transition takes place in response to the combination of the logical transition at least one input node place;
Weighted value is assigned to each conversion of each node in described at least one input vector, considers at least in part that wherein described node place states dynamic load, conversion timing sequence and the impedance of distribute power network and distribute described weighted value; With
The weighting that distributed as described of identification indicated to drawing at least one input vector that power has maximum contribution from described distribute power network.
18. method according to claim 17 determines that wherein at least one logical path comprises: determine a plurality of logical paths in the described circuit; Determine a plurality of input vectors at each logical path; Weighted value is assigned to each logical transition of each node in described a plurality of input vector; Identification is to drawing a plurality of input vectors that power has maximum contribution from described distribute power network; With the combination described through identification a plurality of input vectors be used for the simulation.
19. method according to claim 17 is determined wherein that at least one logical path comprises determining to have to arrive at least one and latch the logical path of output a little.
20. method according to claim 17 is determined wherein that at least one logical path comprises determining to have to arrive at least one and latch a little a little the logical path of latching.
21. method according to claim 17 is determined wherein that at least one logical path comprises and is determined to have a little the logical path of latching that arrives at least one primary input.
22. method according to claim 17 determines that wherein at least one logical path comprises the logical path of determining to have the latch clock node that arrives the major clock input.
23. comprising, method according to claim 17, wherein definite at least one logical path determine to have the logical path that latch clock node is a little latched in arrival.
24. method according to claim 17, it comprises that further at least one in the described circuit of identification be concerned about the zone, and determines that at least one is concerned about regional at least one interior logical path described in the described circuit.
25. method according to claim 24, its further comprise identification adjoin described at least one be concerned about regional zone, and with described adjoins region be included in described at least one be concerned about in the zone.
26. go up the computer-readable media that face code has a kind of method for one kind, described method comprises:
The description of the distribute power network of receiving circuit;
In described distribute power network, define at least one DC supernode;
Receive the logical description of described circuit;
Determine at least one logical path in the described circuit;
Oppositely travel through described at least one logical path, and a plurality of input vectors of definite described at least one logical path, each all describes a plurality of nodes in the described logical path and the logical transition at output node place described input vector, and described logical transition takes place in response to the combination of the logical transition at least one the input node place in described at least one logical path;
Weighted value is assigned to each logical transition of each node in each input vector, considers that at least in part described node place states dynamic load, conversion timing sequence and the impedance of distribute power network and distribute described weighted value:
Identification is to drawing a plurality of input vectors that power has maximum contribution from described distribute power network;
Make up described a plurality of input vectors to be used for simulation through discerning; With
Simulate the AC response of described a plurality of input vectors, and identification produces at least one logical path of peak load to described distribute power network with maximum contribution through discerning.
27. method according to claim 26, it comprises that further at least one in the described circuit of identification be concerned about the zone, and determines that at least one is concerned about regional at least one interior logical path described in the described circuit.
28. method according to claim 26, its further comprise identification adjoin described at least one be concerned about regional zone, and with described adjoins region be included in described at least one be concerned about in the zone.
29. method according to claim 26 determines that wherein at least one logical path comprises the logical path of determining to have the output that arrives at least one primary input.
30. method according to claim 26 is determined wherein that at least one logical path comprises determining to have to arrive at least one and latch the logical path of output a little.
31. method according to claim 26 is determined wherein that at least one logical path comprises determining to have to arrive at least one and latch a little a little the logical path of latching.
32. method according to claim 26 is determined wherein that at least one logical path comprises and is determined to have a little the logical path of latching that arrives at least one primary input.
33. method according to claim 26 determines that wherein at least one logical path comprises the logical path of determining to have the latch clock node that arrives the major clock input.
34. comprising, method according to claim 26, wherein definite at least one logical path determine to have the logical path that latch clock node is a little latched in arrival.
35. method according to claim 26, wherein assign weights comprises that the dynamic load of considering described node place at least in part distributes described weighted value.
36. method according to claim 26, wherein assign weights comprises and considers that at least in part the time quantum that described node place carries out described logical transition distributes described weighted value.
37. method according to claim 26, wherein assign weights comprises and considers that at least in part the impedance that described node place turns back to the DC supernode of described distribute power network distributes described weighted value.
38. method according to claim 26, it further comprises: the DC response of simulating described at least one input vector with maximum contribution through discerning; With described DC response and described AC response summation; With identification at least one logical path to described distribute power network generation peak load.
39. a system, it comprises:
The device that is used for the logical description of the description of received power distributed network and circuit;
Be used for defining the device of at least one DC supernode at described distribute power network;
The device that is used at least one logical path of definite described circuit;
The device that is used for oppositely traveling through described at least one logical path and determines at least one input vector of described at least one logical path, described input vector is described a plurality of nodes in the described logical path and the logical transition at output node place, and described logical transition takes place in response to the combination of the logical transition at least one the input node place in described at least one logical path;
Be used for weighted value be assigned to each logical transition of each node of described at least one input vector and the weighting that distributed as described of identification indicated to drawing the device that power has at least one input vector of maximum contribution from described distribute power network; With
Be used to simulate the AC response of described at least one input vector and identification produces device from least one logical path of peak load to described distribute power network with maximum contribution through discerning.
40. according to the described system of claim 39, it comprises that further at least one that be used for discerning described circuit be concerned about the zone and determine that at least one is concerned about the device of at least one logical path that the zone is interior described in the described circuit.
41. according to the described system of claim 39, its further comprise be used for discerning adjoin described at least one be concerned about the zone the zone and with described adjoins region be included in described at least one be concerned about the device in zone.
42. according to the described system of claim 40, the device that wherein is used for determining at least one logical path comprises the device that is used to determine be selected from the logical path of the group that is made up of following logical path: the logical path with output of at least one primary input of arrival, at least one latchs the logical path of output a little to have arrival, have and arrive at least one and latch a little a little the logical path of latching, has a little the logical path of latching that arrives at least one primary input, have the logical path of the latch clock node that arrives the major clock input and have and arrive the logical path that latchs latch clock node a little.
43. the impedance that according to the described system of claim 40, the device that wherein is used for assign weights comprises the dynamic load that is used for considering at least in part described node place, carry out the time quantum of described logical transition at described node place and turn back to the DC supernode of described distribute power network at described node place distributes the device of described weighted value.
44. according to the described system of claim 40, it further comprises the DC response that is used to simulate described at least one input vector with maximum contribution through identification, described DC response and described AC response summation and identification is produced the device of at least one logical path of peak load to described distribute power network.
45. according to the described system of claim 40, wherein be used for determining that the device of at least one logical path comprises: determine described circuit a plurality of logical paths, at each logical path determine a plurality of input vectors, each logical transition, identification of weighted value being assigned to each node in described a plurality of input vector be to drawing power and have a plurality of input vectors of maximum contribution and make up described a plurality of input vectors through identification to be used for simulation from described distribute power network.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US63496004P | 2004-12-09 | 2004-12-09 | |
| US60/634,960 | 2004-12-09 | ||
| US11/180,441 | 2005-07-13 |
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| Publication Number | Publication Date |
|---|---|
| CN101073082A true CN101073082A (en) | 2007-11-14 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 200580042003 Pending CN101073082A (en) | 2004-12-09 | 2005-12-08 | System and method to determine peak power demand in an integrated circuit |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113361219A (en) * | 2020-05-21 | 2021-09-07 | 台湾积体电路制造股份有限公司 | System and method for optimizing integrated circuit design |
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2005
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113361219A (en) * | 2020-05-21 | 2021-09-07 | 台湾积体电路制造股份有限公司 | System and method for optimizing integrated circuit design |
| CN113361219B (en) * | 2020-05-21 | 2023-08-08 | 台湾积体电路制造股份有限公司 | System and method for optimizing integrated circuit design |
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