CN101069153A - Method and device for switching over in a computer system using at least one external signal - Google Patents
Method and device for switching over in a computer system using at least one external signal Download PDFInfo
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- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/16—Error detection or correction of the data by redundancy in hardware
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- G06F11/1629—Error detection by comparing the output of redundant processing systems
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Abstract
A reciprocating pump for pumping a fluid, especially for pumping a fluid such as UV ink which is subject to solidification when exposed to frictional forces. The pump has an internal displacement chamber with an inlet, and outlet, and a plunger which is reciprocally movable in the chamber. The plunger reciprocates through an axial passage in the housing at one end of the chamber, the passage being sized to receive the plunger with a clearance fit. First and second seals are positioned in the axial passage. Each seal is annular in shape and extends between the plunger and housing in sealing contact therewith. The pump housing is free from a bearing which contacts the plunger or guides its motion, such that the sealing contacts between the plunger and seals are the only contacts of the plunger in the housing.
Description
Background technology
The present invention relates to as described in the preamble a kind of device and a kind of method according to independent claims, be used for changing between at least two kinds of mode of operations of a multicomputer system, this multicomputer system is furnished with at least two performance elements and a corresponding processor system.
By the transient fault that alpha particle or cosmic rays caused, become a kind of problem day by day to integrated semiconductor circuit.The voltage peak that alpha particle or cosmic radiation cause by reducing structure width, reduce voltage and improve pulse repetition rate, just can increase following possibility: owing to can make a logical value distortion in the integrated circuit.The result of calculation of distortion may be its consequence.Therefore, in the system relevant, on automobile, must detect above-mentioned the sort of fault reliably especially with reliability.
The misoperation of the ABS-regulating system (anti-blocking brake system) in security-related system, on for example automobile-in these systems, all must detect reliably electronic installation-on the corresponding control device of these systems, all must use the usually redundancy (Redundanz) that is used for Fault Identification.Therefore, for example in known ABS-system, always will make completely that microcontroller doubles, in this, whole ABS-functions all can be calculated on redundant ground, and its consistance is checked.If the result occurs inconsistent, then promptly turn-off the ABS-system.
A microcontroller is made up of following part on the one hand: memory module (for example RAM＜random access memory 〉, ROM＜ROM (read-only memory) 〉, Cache＜cache memory 〉), processor (CPU＜computer central processing unit 〉, Core＜chip 〉), and input/output interface, so-called peripherals (for example A/D＜simulation/number〉converter, CAN-interface＜controller local area network's interface 〉).Because memory element can effectively utilize check code (odd-even check or ECC) and be supervised, and peripherals often can say as the part of a sensor line or operator signals circuit from specialized application and supervised, so exist another kind of redundant additional in unique multiplication of the chip (CPUs-central processing unit) of a microcontroller.
This microcontroller of being furnished with at least two integrated chips also is referred to as dual core or multiple cored structure.Same program segment is carried out on redundant ground of these two kinds of cores and impulsive synchronization ground, and the result of two performance elements is compared, and identifies error then in conforming comparison procedure.This configuration with a multicore system is referred to as comparison pattern below.
Dual core or multiple cored structure also can be used to raise the efficiency in other is used, and promptly are used for improving performance.Two kinds of cores are carried out different programs, thereby reach the purpose of raising the efficiency, and therefore, the structure of this multicore system is referred to as efficiency mode or performance mode.This system is also referred to as the multicomputer system (SMP) of symmetry.
Can utilize the method for conversion to realize the expansion of this system, in other words, according to the difference of its purposes, this multicomputer system can or be pressed the performance mode operation by comparison pattern.Press comparison pattern when work, the output signal of chip is compared each other.When difference occurring, just send an error signal.When pressing performance mode work, described two kinds of chips are to work as the multicomputer system (SMP) of a symmetry, and carry out different programs.
Advantage of the present invention
The system that relates to is well-known at automotive field at first, and these system's reply external events respond, and perhaps should react according to external event.In these systems, advantageously change according to the condition (for example sensor values, system state, vehicle condition) of processor outside.The communication system of employing time control progressively from now on automobile.In conjunction with these communication systems, favourable way is: according to full time of communication system basis or change the mode of operation of a multicomputer system according to incident At All Other Times.
Making in real time, perhaps be: converting the mode of operation of a multicomputer system to non-redundant mode (performance mode) from a kind of redundant mode (comparison pattern), so as to realizing error location and Error processing separately for the useful way of Error processing.Different system model (for example in an automobile regulating system) also may propose different requirements to the optimization process pattern.Therefore, favourable way is: same program can be moved by first mode of operation of processor system in system model 1; At this moment, in system model 2, then preferably undertaken by second mode of operation of processor system.In the prior art, all depend on external signal, promptly can not finish by the program special marker or to the access of a certain memory address to the conversion targetedly of the mode of operation that provides or the inhibition of carrying out for this conversion.
Task of the present invention is, realizes conversion between the different working modes according to an external signal.
Now preferentially introduce a kind of conversion method with regard to a computer system of being furnished with at least two performance elements, in this, between at least two mode of operations, realize conversion, first mode of operation is corresponding to a comparison pattern, second mode of operation is corresponding to a performance mode, it is characterized in that, activate described conversion by at least one signal, this signal is in the outside generation of computer system.Advantageously, this external signal be furnished with a kind of identification signal (Kennung) in other words this signal contain a kind of like this identification signal, wherein have only when having identification signal and just can change.Preferably determine to be transformed into which kind of mode of operation by this identification signal.This identification signal preferably contains a time conditions, determines when by this time conditions and is changed.Advantageously, by the only conversion between a direction realization mode of operation of external signal.Advantageously, just be transformed into comparison pattern by this external signal from performance mode.Advantageously, only realize conversion from the comparison pattern to the performance mode by this external signal.Advantageously, the triggering of this signal indication Interrupt Process.Advantageously, this identification signal is corresponding to the prearranged signals process of the signal of a prearranged signals process (vorgebebener Signalverlauf), a particularly pulse-length modulation.Advantageously, this identification signal is corresponding to a predetermined frequency.Advantageously, this identification signal is corresponding to the predetermined bit string (Bitfolge) of a digital signal.Advantageously, this identification signal is corresponding to the predetermined message-ID (sign) of the information of a communication system.Advantageously, described conversion is by being activated by at least one signal that is produced in the computer system outside and at least one a kind of combination in the information that inside computer system produced.Advantageously, have only when described at least one external signal and described at least one inside computer system information side by side exist, just realize conversion.Advantageously, have only when realizing a kind of release that is used to change of prescribing a time limit according at least one external signal, and when in the release time that limits, having an inside computer system information being used to change or an inside computer system incident at least, just change.Advantageously, on a computer system with at least two performance elements, include a conversion equipment, wherein also contain throw-over gear, these throw-over gears are so designs, make them between at least two kinds of mode of operations, to change, one of them first mode of operation is corresponding to a comparison pattern, one second mode of operation is corresponding to a performance mode, it is characterized in that, include receiving mechanism, it can accept at least one at the signal that the computer system outside is produced, and wherein said conversion can be resulted from the signal activation of computing machine outside.Advantageously, the receiving mechanism that is used to receive described at least one external signal is a kind of interruptable controller.Advantageously, contain receiving mechanism, it receives at least one at the outside signal that produces of computer system; Also include such mechanism, these mechanisms can be with from the same inner signal combination that produces of an identification signal of that signal that the outside received or this signal, wherein said conversion just can be activated by a kind of combination, and this combination is formed in the information that inside computer system produced by at least one signal that is produced in the computer system outside and at least one.
Other advantage and favourable design proposal are by the feature of every claim and instructions and draw.
Description of drawings
Fig. 1 represents a kind of multicomputer system, is furnished with two performance elements, is furnished with the device of the data that are used for these two performance elements of comparison, also is furnished with a converting unit that is used for working mode change;
Fig. 2 represents a kind of multicomputer system, is furnished with two performance elements, is furnished with the device of the data that are used for these two performance elements of comparison, also is furnished with a converting unit and an outside source that produces switching signal that is used for working mode change;
Fig. 3 represents a kind of multicomputer system, are furnished with two performance elements, the device of being furnished with the data that are used for these two performance elements of comparison also is furnished with a converting unit and an outside source that is used for working mode change, and this signal source links to each other with an interruptable controller of multicomputer system;
Fig. 4 represents a kind of multicomputer system, are furnished with two performance elements, the device of being furnished with the data that are used for these two performance elements of comparison also is furnished with a converting unit and an outside source that is used for working mode change, and this signal source links to each other with this multicomputer system through a communication system.
Fig. 5 represents a kind of common conversion and comparing unit.
Embodiment
Below, a performance element both can be expressed as a processor/chip/CPU (CPU (central processing unit)), also can be expressed as a FPU (floating point unit), DSP (digital signal processor), coprocessor or ALU (arithmetic and logical unit).
The present invention relates to the multicomputer system W100 shown in a kind of Fig. 1, be furnished with: at least two performance element W110a, W110b, a comparing unit W120, and a converting unit W150.Performance element links to each other with a converting unit W150 with a comparing unit W120 through selectable intermediate store W111a, a W111b separately.Converting unit W150 has at least two delivery outlets, corresponding to two system interface W130a, W130b.Through above-mentioned interface, just may command register, storer or peripherals such as digital delivery outlet, digital-to-analog (D/A)-converter, communication controler.
This multicomputer system can be operated by at least two kinds of mode of operations, promptly by a kind of comparison pattern VM and a kind of performance mode PM.
In performance mode PM, on different performance elements, carry out different instruction, program segment or program concurrently.By this mode of operation, comparing unit is to remove to activate.By this mode of operation, converting unit W150 is so configuration, makes each performance element link to each other with one of system interface W130a, W130b through alternative intermediate store.Through these system interfaces, the result of a performance element can be written among the storer W170, perhaps it is sent to peripherals W180, a W190.The communication controler (as SPI, LIN, CAN, FlexRay) that peripherals for example can be a simulation-digital converter or communication system.
To activate in order removing, multiple possibility to be arranged for comparing unit.The first can be introduced a signal to comparer, utilizes this signal that this comparer is activated or the removal activation.For this reason, in comparer, must import a kind of additional logical signal, so as to carrying out foregoing.Another possibility is not carry data to be compared to comparer.The third possibility is to ignore the error signal of comparer on System planes.In addition, can also interrupt error signal itself.The something in common of all these possibilities is: they produce a kind of state in system, under this state, when two or more data that may be compared are all inequality, have not just had an effect.Reach above-mentioned state if input or output signal by the measure in the comparer or its, so, this comparer just can be referred to as passive or remove to activate.
Press comparison pattern VM, in described two performance element W110a, W110b, handle identical or similar instruction, program segment or program.Through selectable intermediate store W111a, W111b, the output signal of performance element is directed to comparing unit W120 and converting unit W150.In comparing unit, check the consistance of described two data.After comparing, through a status signal W125, to inform converting unit, whether converting unit can send to one of system interface with among the result of unanimity, and perhaps whether converting unit must be owing to inconsistent this signal that ends of known result.In the case, can send a selectable error signal W155 from comparing unit.This error signal can be can't help comparing unit and sent, and can send W156 by converting unit.
Here, described conversion both can be activated by in the chip of multicomputer system at least one through following execution: the execution of special conversion instruction, the execution of the execution of special instruction sequence, the instruction that clearly marks is perhaps by the access to certain storage address.In the present invention, the conversion between two mode of operations of multicomputer system activates by at least one signal W160, and this signal is that signal source W140 produces by a device of computer system outside, sees shown in Fig. 2.
In first embodiment, conversion is strict with a signal execution.This conversion can so be carried out: strict a kind of character by signal, realize transforming to one second mode of operation from first mode of operation arbitrarily, and this multicomputer system is in the time of reception point of this signal in first mode of operation.
In second embodiment, conversion can so design: strict a kind of character by signal, mode of operation only promptly strictly transforms to second predetermined mode of operation from first predetermined mode of operation along a direction, for example is transformed into comparison pattern from performance mode.If multicomputer system on the time of reception point of signal in second mode of operation of determining as dbjective state, keep switching signal so and multicomputer system no longer had an effect.Conversion is if undertaken by another direction, so must be in addition through a known method, for example according to a processor internal signal or incident, according to access to certain storage address, according to the execution of certain program, program segment or instruction, perhaps still through one second external signal.
The character of above-mentioned signal can be surmounting of the existence of a signal or a signal level or be no more than.
In the 3rd embodiment, the conversion of mode of operation is carried out according at least one signal, this signal is that signal source W140 produces in computer system outside by a device, this signal has also been added an identification signal, perhaps this signal just is surrounded by an identification signal, according to last, only when identification signal is arranged, just can change.Identification signal by this signal just can be determined: which kind of duty multicomputer system should be transformed into.This identification signal can comprise a time conditions and/or corresponding to certain prearranged signal process,
For example:
The gradient of a signal,
The dutycycle of the signal of a pulse-length modulation,
A given frequency of an ac voltage signal, a pulse-length modulation or warbled signal,
Give positioning string for one of a digital signal,
A predetermined message identifier (ID) of an information of a communication system
Identification signal also can be equivalent to a kind of associating of two or more above-mentioned signal process.
In this, signal source W140 can be corresponding to one in the following column element or corresponding to the combination of a plurality of elements in the column element down:
μ C-external timer (for example timer of the time basis of a communication system)
The error signal of a μ C-external unit (for example SG＜indicator〉in monitor)
Sensor signal
Other control device
The status signal of an application system (as the adjustment state of an ABS-system, the limit of internal combustion engine on the automotive system)
Signal source W140 can be exclusively used in first embodiment and produce a switching signal.As shown in Figure 2, this signal source can be passed through an a kind of point-connection W160 and be linked to each other with multicomputer system, particularly directly links to each other with converting unit W150 in this.
Implement in the variant at second shown in Fig. 3, external conversion signal W160 is through an interruptable controller W159 and received as look-at-me.This external signal implements to cause in the variant triggering of an Interrupt Process at this, so the conversion between the mode of operation is just caused by interruptable controller.
But implement as shown in Figure 4, also can use another kind of control device or a kind of intelligence sensor W145 as signal source in the variant at another, this sensor is connected on the processor system through a communication system W165.Digital signal then through communication interface W195 and internal data-/address bus and be introduced to converting unit W150.
It is contemplated that also that is a kind of combination in any that described signal source W140, W145 and signal connect W160, W165 and interruptable controller W159.
Press another enforcement variant of native system, conversion between the mode of operation is not singly carried out by an external signal, but carry out the i.e. combination of at least one extraneous signal and the information, an incident and the signal that produce at inside computer system at least by a kind of the combination.This inside computer system incident for example can be the execution of a programmed instruction or to the access of certain storage address.It is to realize be connected W112a, the W112b shown in Fig. 4 through Fig. 2, Fig. 3 that converting unit W150 obtains this information, promptly between performance element W110a, the W110b between selectable in other words intermediate store W111a, the W111b, the connection between comparing unit W120 and the converting unit W150.The combination of signal is preferably in converting unit W150 inside and carries out.This to be combined in that first implements in variant be so to carry out, and makes conversion between the mode of operation have only when having at least one external signal and at least one internal information simultaneously and just carry out.Implement in the variant at another, only produce the once release of conversion by external signal, this conversion preferably is restricted in time.Once conversion has only and is only possiblely by an internal event then, and this internal event is generation after conversion discharges in a definite time window.
External signal can not discharge for conversion produces, discharges but regain, and be exactly to stop conversion or rather.This also preferably is restricted in time.So just can at first prevent the conversion on some time point, perhaps prevent the conversion under some system state.
In those above embodiment, introduced a kind of multicomputer system of being furnished with two performance elements and two mode of operations respectively.Various features of the present invention can be applied to the multicomputer system with two above performance elements equally.Required in this respect change is mainly on converting unit and comparing unit.
In the ordinary course of things, conversion portion and rating unit see shown in Fig. 5 that these parts are also applicable to the multicomputer system with two above performance elements.Send n signal N140 from n the performance element of being considered to converting unit and comparing unit N100 ..., N14n.This can produce up to n output signal N160 from these input signals ..., N16n.By the simplest situation, promptly by " pure performance mode ", all signal N14i are guided corresponding output signal N16i.Under opposite limiting case, promptly under " pure comparison pattern " situation, all signal N140 ..., N14n can only strict revert among the output signal N16i.
In a system with n performance element and n＞2, can consider mode of operation more than two.Can illustrate how to produce the different mode of operations of imagining with reference to Fig. 5.For this reason, the logical gate that contains a switching logic unit N110 in the figure.This logical gate is at first definite: what output signals are arranged on earth.In addition, switching logic unit N110 also can determine the dependence of output signal to input signal.By mathematical expression molded, also can by the switching logic unit determine one from the amount N140 ..., and N14n) to the amount N160 ..., the function of N16n}.
Then, processing logic N120 is that among the output signal N16i each is determined: input signal helps this output signal with which kind of form.For example for the different possibilities that change are described, ubiquity is not limited to: output signal N160 is by input signal N141 ..., N14m, generation.If m=1, then this is equivalent to the conducting of this signal simply; If m=2, signal N141 then, N142 is compared with regard to consistance.This comparison can synchronous or asynchronous the execution, and it can be carried out by a significance bit or an also available margin tolerance bit by bit or only.
If then there are a plurality of possibilities m＞=3.
First possibility is: relatively more all signals, when having at least two different values, measure an error, to the signalling selectively of this error.
Second possibility is: get a K (K＞m/2) from m-selects.This possibility can relatively be achieved by using.In addition, one in signal is identified as words devious, also can design an error signal.Perhaps, if all signals that are compared are all inequality, also can design another error signal.
The 3rd possibility is: these values are placed under a kind of algorithm.This algorithm for example can form a mean value, and an intermediate value perhaps shows as a kind of tolerance algorithm (FTA).The basis of this tolerance algorithm FTA is: the extreme value in the input value is scratched, and got its average a kind of method on the value of remainder.This mean value can be achieved on the partial amt that forms easily on the HW at one on the total quantity of the value of remainder or preferentially.Be not always need carry out actual specific in the case to each value.In the process of averaging, for example need only use addition and division, FTM, FTA or average and then require a kind of part separating method.In this, also can under enough big extreme cases, send an error signal selectively.
Above-mentioned is the shortcut of comparison operation processing by identification about the different possibilities that a plurality of signal Processing become a signal.
The task of processing logic unit also is thereby each output signal is also determined a kind of comparison operation pattern accurately to affiliated input signal.The combination of the information of the information of switching logic N110 (being aforesaid function) and processing logic (being that each output signal is the determining of comparison operation of each functional value) is exactly a pattern information, and just deterministic model of this pattern information.This information is many-valued in the ordinary course of things very naturally, that is to say not only to represent a logical bit (bit).The not all pattern that can imagine in theory all is significant in a given implementation procedure, so can preferentially limit the number of the pattern of permission.What must emphasize a bit is under the situation of having only two performance elements, just to have only a comparison pattern, so full detail all can only be compressed on the logical bit.
From the conversion of performance mode switch to a comparison pattern, be feature normally: in performance mode, be reflected in the performance element on the different output signals, in comparison pattern, then be reflected on the same output signal with the following fact.Preferably realize it: a part system that has performance element with following condition, all input signal N14i that is taken into account in the part system all directly remain on the corresponding output signal N16i in performance mode in this part system, and then they all are reflected on the output signal in comparison pattern.In addition, on the multicomputer system that has more than three performance elements, this conversion also can be achieved by following step: change pairing.Its performance is as follows: in the ordinary course of things, no matter can performance mode and comparison pattern, though can so limit the quantity of the pattern that is allowed by a given type of the present invention, so as to achieving the above object.But, generally relate to a kind of conversion of from the performance mode to the comparison pattern (with conversely).
Claims (18)
1. the method for the conversion usefulness on a computer system with at least two performance elements, wherein between at least two mode of operations, change, and a kind of first mode of operation is corresponding to a kind of comparison pattern, a kind of second mode of operation is corresponding to a kind of performance mode, it is characterized in that, described conversion activates by at least one signal, and this signal is in the outside generation of computer system.
2. by the described method of claim 1, it is characterized in that this external signal sets a kind of identification signal, perhaps it contains a kind of like this identification signal, wherein has only when having this identification signal, just changes.
3. by the described method of claim 2, it is characterized in that just can determine to be transformed into which kind of mode of operation by identification signal.
4. by the described method of claim 2, it is characterized in that identification signal comprises a kind of time conditions, determine when by this time conditions and change.
5. by the described method of claim 1, it is characterized in that by this external signal, a kind of conversion is just carried out in one direction between two kinds of mode of operations.
6. by the described method of claim 1, it is characterized in that, only be transformed into comparison pattern from performance mode by this external signal.
7. by the described method of claim 1, it is characterized in that, only be transformed into performance mode from comparison pattern by this external signal.
8. by the described method of claim 1, it is characterized in that the triggering of a kind of Interrupt Process of this signal indication.
9. by the described method of claim 2, it is characterized in that identification signal is corresponding to a kind of prearranged signals process of signal of prearranged signal process, particularly a kind of pulse-length modulation.
10. by the described method of claim 2, it is characterized in that identification signal is corresponding to a kind of predetermined frequency.
11., it is characterized in that identification signal is corresponding to a kind of predetermined bit string of digital signal by the described method of claim 2.
12., it is characterized in that identification signal is corresponding to a kind of predetermined message-ID of the information of a communication system by the described method of claim 2.
13., it is characterized in that described conversion is by being activated by at least one signal that produces in the computer system outside and at least one combination in the information of inside computer system generation by the described method of claim 1.
14., it is characterized in that having only under described at least one external signal and the simultaneous situation of described at least one inside computer system information by the described method of claim 13, described conversion is just carried out.
15. by the described method of claim 13, it is characterized in that, have only under the following conditions and just change: according at least one external signal a kind of release of prescribing a time limit is carried out in described conversion, and the incident that has the information of at least one inside computer system or an inside computer system in restricted release time is to be used for described conversion.
16. the device of the conversion usefulness on a kind of computer system with at least two performance elements, wherein comprise throw-over gear, this throw-over gear is so design, make them between at least two kinds of mode of operations, change, wherein first mode of operation is corresponding to a kind of comparison pattern, second mode of operation is corresponding to a kind of performance mode, it is characterized in that, include receiving mechanism, this receiving mechanism receives at least one at the outside signal that produces of computer system, wherein, described conversion is by the signal triggering that produced in the computer system outside.
17., it is characterized in that the receiving mechanism that is used to receive described at least one external signal is a kind of interruptable controller by the described device of claim 16.
18., it is characterized in that include receiving mechanism, they receive at least one signal that is produced in the computer system outside by the described device of claim 16; Also comprise such mechanism: the same inner signal combination that produces of an identification signal of the signal that these mechanisms will receive from the outside or this signal, wherein said conversion is by being triggered by at least one signal that is produced in the computer system outside and at least one a kind of combination in the information that computer-internal produced.
Applications Claiming Priority (7)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DE102004051950.1 | 2004-10-25 | ||
| DE200410051937 DE102004051937A1 (en) | 2004-10-25 | 2004-10-25 | Data distributing method for multiprocessor system, involves switching between operating modes e.g. safety and performance modes, of computer units, where data distribution and/or selection of data source is dependent upon one mode |
| DE102004051937.4 | 2004-10-25 | ||
| DE102004051992.7 | 2004-10-25 | ||
| DE102004051964.1 | 2004-10-25 | ||
| DE102004051952.8 | 2004-10-25 | ||
| DE102005037213.9 | 2005-08-08 |
Publications (2)
| Publication Number | Publication Date |
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| CN101069153A true CN101069153A (en) | 2007-11-07 |
| CN100561424C CN100561424C (en) | 2009-11-18 |
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Family Applications (5)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 200580036590 Pending CN101048760A (en) | 2004-10-25 | 2005-10-25 | Method and device for changing mode and comparing signal in a computer system having at least two processing units |
| CN 200580036404 Expired - Fee Related CN100561424C (en) | 2004-10-25 | 2005-10-25 | Utilize at least one external signal to realize the method and apparatus of changing between the mode of operation of multicomputer system |
| CN 200580036570 Pending CN101048756A (en) | 2004-10-25 | 2005-10-25 | Method and device for changing mode and comparing signal in a computer system having at least two processing units |
| CN 200580036442 Pending CN101048746A (en) | 2004-10-25 | 2005-10-25 | Method and device for switching over in a computer system having at least two execution units |
| CN 200580036537 Pending CN101048753A (en) | 2004-10-25 | 2005-10-25 | Method and device for switching over in a computer system having at least two execution units |
Family Applications Before (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 200580036590 Pending CN101048760A (en) | 2004-10-25 | 2005-10-25 | Method and device for changing mode and comparing signal in a computer system having at least two processing units |
Family Applications After (3)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 200580036570 Pending CN101048756A (en) | 2004-10-25 | 2005-10-25 | Method and device for changing mode and comparing signal in a computer system having at least two processing units |
| CN 200580036442 Pending CN101048746A (en) | 2004-10-25 | 2005-10-25 | Method and device for switching over in a computer system having at least two execution units |
| CN 200580036537 Pending CN101048753A (en) | 2004-10-25 | 2005-10-25 | Method and device for switching over in a computer system having at least two execution units |
Country Status (2)
| Country | Link |
|---|---|
| CN (5) | CN101048760A (en) |
| DE (1) | DE102004051937A1 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114073042A (en) * | 2019-05-16 | 2022-02-18 | 罗伯特·博世有限公司 | Transmitting/receiving device and communication control device for a subscriber station of a serial bus system and method for communication in a serial bus system |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE102012221410A1 (en) * | 2012-11-23 | 2014-06-12 | Zf Friedrichshafen Ag | Communication devices, radio switches and methods of communication |
| DE102015218898A1 (en) * | 2015-09-30 | 2017-03-30 | Robert Bosch Gmbh | Method for the redundant processing of data |
| CN105279046A (en) * | 2015-11-04 | 2016-01-27 | 研华科技(中国)有限公司 | Method for improving reliability of embedded system |
| CN112667450B (en) * | 2021-01-07 | 2022-05-06 | 浙江大学 | Dynamically configurable fault-tolerant system with multi-core processor |
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2004
- 2004-10-25 DE DE200410051937 patent/DE102004051937A1/en not_active Withdrawn
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2005
- 2005-10-25 CN CN 200580036590 patent/CN101048760A/en active Pending
- 2005-10-25 CN CN 200580036404 patent/CN100561424C/en not_active Expired - Fee Related
- 2005-10-25 CN CN 200580036570 patent/CN101048756A/en active Pending
- 2005-10-25 CN CN 200580036442 patent/CN101048746A/en active Pending
- 2005-10-25 CN CN 200580036537 patent/CN101048753A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114073042A (en) * | 2019-05-16 | 2022-02-18 | 罗伯特·博世有限公司 | Transmitting/receiving device and communication control device for a subscriber station of a serial bus system and method for communication in a serial bus system |
| US11632265B2 (en) | 2019-05-16 | 2023-04-18 | Robert Bosch Gmbh | Transceiver unit and communication control unit for a user station of a serial bus system and method for communication in a serial bus system |
| CN114073042B (en) * | 2019-05-16 | 2023-05-09 | 罗伯特·博世有限公司 | Transmitting/receiving device and communication control device for subscriber station of serial bus system and method for communication in serial bus system |
Also Published As
| Publication number | Publication date |
|---|---|
| CN101048753A (en) | 2007-10-03 |
| CN101048760A (en) | 2007-10-03 |
| CN101048746A (en) | 2007-10-03 |
| CN100561424C (en) | 2009-11-18 |
| DE102004051937A1 (en) | 2006-05-04 |
| CN101048756A (en) | 2007-10-03 |
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