CN101067753A - Electric power bias circuit with negative feedback - Google Patents

Abstract

The invention relates to electrical source biasing circuit with negative feedback. It includes biasing generating circuit, mirror image branch circuit, feedback branch circuit, current output branch circuit. The biasing generating circuit is formed by electrical source I1, I2, NOMS tube n1, n2, used to generate bias current. The mirror image branch circuit is formed by PMOS tube p1 and NMOS tube n3, used to image the current to output branch circuit. The feedback branch circuit is formed by electrical source I3, equivalent switch, used to generate current feedback quantity, adjust bias current. The current output branch circuit is formed by PMOS tube p5, used to output stable bias current. The invention fixes the indifferent bias on the fixed value, can stabilize output bias current, and reduce source voltage sensitivity better compared with the existing current bias circuit. It inducts negative feedback, makes output bias current have higher precision by adjusting current in bias generating circuit.

Description

A kind ofly be with degenerative electric power bias circuit

Technical field

The invention belongs to field of analog integrated circuit, be specifically related to a kind of degenerative electric power bias circuit of being with, this circuit can provide the bias current with supply independent effectively.

Background technology

Along with the development of society, make people also more and more higher to the performance requirement of consumption electronic product.Just the performance requirement to corresponding consumer IC is also more and more higher for this.Wherein the effect of biasing circuit mainly is to provide suitable bias current to be used for determining the quiescent point of amplifier for other operational modules.Usually need high-quality biasing circuit at IC interior, so that stable bias current to be provided.For multichannel integrated transporting discharging, because the common biasing circuit of basic use, even also need to consider crosstalking mutually between adjacency channel.

What the biasing circuit of existing and supply independent adopted usually is the supply independent biasing circuit that adopts the different metal-oxide-semiconductor of size to form, be used in the unique definite current value of method that source electrode adds resistance, and order about circuit by extra interpolation startup pipe or start-up circuit and break away from the degeneracy bias point, from the principle, can think a kind of with positive feedback and biasing circuit supply independent.So both the inhibition ability to supply independent was lower, also introduced too much startup pipe.

Publish in publishing house of Xi'an Communications University 2003, translate by people such as Chen Guican in the classical books " analog cmos integrated circuit (IC) design " of the Bi Chadelazhawei that finishes, tell about an electric power bias circuit for 311 pages, but there is not any feedback circuit in it, so its Power Supply Rejection Ratio can't reach a higher precision, make it when high-precision applications, will meet the demands.And the extra start-up circuit of its needs, integrally-built cost performance is not high.

Summary of the invention

The object of the present invention is to provide a kind of degenerative electric power bias circuit of being with, this electric power bias circuit has the ability that works alone, and the circuit area occupied is little, can improve the circuit dynamic property effectively.

Provided by the inventionly be with degenerative electric power bias circuit, this circuit comprises offset generating circuit, mirror image branch, feedback branch and electric current output branch road; Wherein,

Offset generating circuit is used to produce the bias current with supply independent, and it is by current source I1, I2, and NMOS manages n1, and n2 forms, and NMOS pipe n1, n2 form current-mirror structure, and both grid width and breadth length ratio all equate; Current source I1 one termination high level Vcc, the drain electrode of another termination n1; The termination high level Vcc of current source I2, the other end and NMOS pipe n2 drain electrode are joined, and insert mirror image branch; The grid of NMOS pipe n1 connects the grid of NMOS pipe n2, and joins with the leakage level of NMOS pipe n2; The source ground of NMOS pipe n1 and n2; Mirror image branch is used for the electric current of mirror image offset generating circuit, and current mirror is exported branch road to electric current; Mirror image branch is made up of PMOS pipe p1 and NMOS pipe n3; The source electrode of PMOS pipe p1 meets high level Vcc, and its grid links to each other with drain electrode, inserts electric current output branch road, and the drain electrode of receiving NMOS pipe n3; NMOS pipe n3 equates that with the breadth length ratio of NMOS pipe n2 the drain electrode of the grid of NMOS pipe n3 and NMOS pipe n2 is joined, NMOS pipe n3 source ground;

Feedback branch is used to produce the current feedback amount, adjusts the bias current size in the offset generating circuit; Feedback branch is made up of current source I3 and equivalent switch SW; The termination high level Vcc of current source I3, the other end and SW one end join, and the drain electrode of NMOS pipe n2 is joined in the other end of SW and the offset generating circuit;

Electric current output branch road is used to export stable bias current, and an electric current output route PMOS pipe p2 forms; The source electrode of PMOS pipe p2 meets high level Vcc, and the grid of PMOS pipe p1 joins in grid and the mirror image branch, drain electrode output offset electric current.

Electric power bias circuit of the present invention will with the bias stabilization of supply independent in fixing value, this structure can better be stablized the bias current of output compared with existing electric power bias circuit, reduces source voltage sensitivity.Compare with existing biasing, the method that offset generating circuit does not adopt existing left and right sides branch current to equate, but carry out current compensation by the branch road of backfeed loop offset generating circuit, the electric current of two branch roads equates, for the mismatch of branch road, backfeed loop also can play inhibiting effect simultaneously.The present invention introduces the negative feedback notion, makes electric current remain on certain value by the adjusting to the electric current in the offset generating circuit, strengthens the stability of bias current, makes the bias current of output that higher precision be arranged.

Description of drawings

Fig. 1 is the principle schematic of negative feedback biasing circuit of the present invention;

Fig. 2 is a specific implementation circuit diagram of the present invention.

Embodiment

As shown in Figure 1, the degenerative electric power bias circuit of band of the present invention comprises offset generating circuit 1, mirror image branch 2, and feedback branch 3 and electric current output branch road 4 the following describes this circuit working principle.

The image current that current source I1 and I2 produce is flowed through respectively, and NMOS manages n1 and NMOS manages n2, when the electric current among NMOS pipe n1 and the NMOS pipe n2 equates, and the SW disconnection, image current is managed p1 by PMOS, and NMOS manages n3 and is mirrored to PMOS pipe p2 output; When I1 and I2 do not wait, the switch SW conducting, I3 flows into NMOS pipe n2, and flow compensated makes the flow through electric current of NMOS pipe n1 equate with the electric current that the NMOS that flows through manages n2 through the electric current of NMOS pipe n2.Electric current among the NMOS pipe n2 after over-compensation is managed p1 through PMOS, and NMOS pipe n3 exports after being mirrored to PMOS pipe p2.

As shown in Figure 2, the degenerative biasing circuit of band of the present invention comprises offset generating circuit 1, mirror image branch 2, sampling and the common feedback branch of forming 3 of adjusting branch road, electric current output branch road 4 and output control signal 5 compositions.Wherein, the part of the part of feedback branch and offset generating circuit constitutes start-up circuit.Offset generating circuit 1 is by resistance R 1, R2, and PMOS manages p3, and PMOS manages p4, and NMOS manages n1, and NMOS pipe n2 constitutes.The termination high level Vcc of R1, the source electrode of another termination PMOS pipe p3, PMOS pipe p3 is that diode connects, and receives PMOS after its grid and drain electrode link to each other again and manages the grid of p4 and the drain electrode that NMOS manages n1; An end and the high level Vcc of R2 join, the other end is received the source electrode of PMOS pipe p4, the grid of PMOS pipe p4 connects the grid of PMOS pipe p3, grid and the drain electrode of the NMOS pipe n2 that diode connects received in drain electrode, and the emitter of the triode Q1 that is connected with diode of the grid of the grid of NMOS pipe n1, NMOS pipe n3.

Mirror image branch 2 is made of PMOS pipe p1 and NMOS pipe n3, and wherein PMOS pipe p1 source electrode meets high level Vcc, grid with connect the drain electrode of NMOS pipe n3 after drain electrode links to each other, and the PMOS that inserts the electric current output module manages the grid of p2.The grid of NMOS pipe n3 links to each other the source ground of NMOS pipe n3 with the grid of NMOS pipe n2 in the offset generating circuit.

Feedback branch 3 comprises the sampling branch road and regulates branch road two parts, a sampling route PMOS pipe p5, and resistance R 4, R5 forms, and the breadth length ratio of PMOS pipe p5 and PMOS pipe p1 is m: 1 (the m span is 2-10, generally gets and does 2 or 4) is set to 4: 1 here.The source electrode of PMOS pipe p5 meets high level Vcc, and grid connects the grid of PMOS pipe p1, the end of drain electrode connecting resistance R4.The other end of resistance R 4 and resistance R 5 one ends join, and receive the grid of regulating NMOS pipe n4 in the branch road, the other end ground connection of R5.Regulate a route resistance R 3, NMOS pipe n4 and triode Q1 form.One termination high level Vcc of resistance R 3, the other end joins with the drain electrode of NMOS pipe n4 and base stage and the collector of triode Q1, and inserts output control signal module.The grid of NMOS pipe n4 connects the end that resistance R 5 links to each other with resistance R 4 in the sampling branch road, the source ground of NMOS pipe n4.The emitter of triode Q1 connects the grid of NMOS pipe n2 in the biasing generation module, and its collector links to each other with base stage, receives the end of output control signal module and R3.

Electric current output module 4 is made up of PMOS pipe p2, and the source electrode of PMOS pipe p2 meets high level Vcc, and grid and the drain electrode of PMOS pipe p1 are joined in grid and the mirror image branch, the drain electrode output offset electric current of PMOS pipe p2.

Control signal module 5 is made up of reverser INV1, the drain electrode of its input end and NMOS pipe n4, and the end of R3 and base stage and the collector of Q1 link to each other, phase inverter INV1 output terminal output control signal CTRL_OUT.

Resistance R 3, triode Q1, NMOS pipe n2 forms and starts the loop, when power supply just powers on, at via resistance R3, triode Q1, the electric current of flowing through among the NMOS pipe n2, circuit is started working.Electric current among the PMOS pipe p4 NMOS pipe n2 that flows through, the drain terminal electric current I n2 among this electric current and the NMOS pipe n2 mirror image n2 that connected by diode is in NMOS pipe n1, because NMOS pipe n1, the breadth length ratio of NMOS pipe n2 is identical, In1=In2.Id2 is mirrored to In1 among the PMOS pipe p4 once more by the PMOS pipe p3 that diode connects, because PMOS pipe p3, the breadth length ratio of PMOS pipe p4 is identical, and R1 resistance sizes and be not equal to R2, Ip3 is not equal to Ip4, and the size of current of Ip3 and Ip4 is provided by following formula

For PMOS pipe p3 ,-V _Gs3=V _Dd-I _N1R ₁-V _x

For PMOS pipe p4 ,-V _Gs4=V _Dd-I _N2R ₂-V _x

And PMOS pipe p3, p4 is operated in the saturation region,

For PMOS pipe p3, ${\mathrm{<figure-callout\; id="3"\; label="I\; p"\; filenames="A20071005240800101.png"\; state="\{\{state\}\}">I</figure-callout>}}_p=\frac{1}{2}{\mathrm{\&mu;}}_p{C}_{\mathrm{ox}}\frac{W}{L}{(-{\mathrm{<figure-callout\; id="3"\; label="V\; gs"\; filenames="A20071005240800101.png"\; state="\{\{state\}\}">V</figure-callout>}}_{\mathrm{gs}}+V_{\mathrm{Tp}})}^2$

For PMOS pipe p4, ${\mathrm{<figure-callout\; id="4"\; label="I\; p"\; filenames="A20071005240800102.png"\; state="\{\{state\}\}">I</figure-callout>}}_p=\frac{1}{2}{\mathrm{\&mu;}}_p{C}_{\mathrm{ox}}\frac{W}{L}{(-{\mathrm{<figure-callout\; id="4"\; label="V\; gs"\; filenames="A20071005240800102.png"\; state="\{\{state\}\}">V</figure-callout>}}_{\mathrm{gs}}+V_{\mathrm{Tp}})}^2$

So Ip4＜Ip3.If Q1 does not exist, In2=Ip4, In2 are mirrored onto In1 again, and In1 reduces, and so go down, and NMOS manages n1, and PMOS manages p3, and NMOS manages n2, and the electric current among the PMOS pipe p4 can reduce gradually, and is last near zero.For avoiding this situation to take place, Q1 can provide a current component to compensate to the drain terminal electric current I n2 that NMOS manages n2, makes I _N2=I _P4+ I _B1, keep the current stabilization in the biasing main body.

In the mirror image branch, NMOS pipe n3 is 1: 1 with the ratio that biasing produces the breadth length ratio of NMOS pipe n2 in the branch road, electric current among the NMOS pipe n2 is mirrored onto among the NMOS pipe n3, and the PMOS pipe p1 that further connects by diode manages the current mirror that NMOS manages among the n2 among the p5 to PMOS, because the ratio of the breadth length ratio of PMOS pipe p5 and PMOS pipe p1 is 4: 1, the size of current among the PMOS pipe p5 is four times in the NMOS pipe n2 pipe.

In the feedback branch, size of current is that NMOS manages four times among the n2 among the PMOS pipe p5, increases the sensitivity of regulating.Because the electric current variation among the NMOS pipe n2 can cause the electric current variation among the PMOS pipe p5, thereby cause the change in pressure drop on the R5, the grid voltage of NMOS pipe n4 is changed.After the grid voltage of NMOS pipe n4 changed, the electric current I n4 among the NMOS pipe n4 changed, and electric current remains unchanged substantially among the R3, because the size of current among the R3 is

$I_{\mathrm{<figure-callout\; id="3"\; label="R"\; filenames="A20071005240800101.png"\; state="\{\{state\}\}">R</figure-callout>}3}=\frac{V_{\mathrm{cc}}-(V_p+V_{\mathrm{gs}\left(n2\right)}+V_{\mathrm{be}})}{R_3}$

Electric current variation among the NMOS pipe n4 can cause the current component I of compensation _B1Variation, thereby cause that electric current changes among the NMOS pipe n2.

In the phase inverter of control signal module, the breadth length ratio of PMOS pipe is very big, 4-6 is the breadth length ratio of the pipe of the NMOS in phase inverter n pipe doubly, make that like this turn threshold of phase inverter is less, the drain voltage of NMOS pipe n4 hour just can overturn when NMOS pipe n4 conducting, exports the control signal of high level, otherwise, when NMOS pipe n4 did not work, phase inverter was output as zero level, turn-offs other modules.

As shown in Figure 2, when In2 increases a component Δ I who does not expect with respect to In1,

I _n2′＝I _n2+ΔI

I _N2' through NMOS pipe n3, PMOS manages p1, and PMOS pipe p2 is mirrored among the PMOS pipe p2

I _p4＝4I _n2′，

Therefore, the grid step voltage of n4 increases Δ V=Δ IR5, and the electric current among the n4 increases

ΔI _n4＝ΔV·g _m(n4)

Because

I _B1+I _n4＝I _R3

$I_{\mathrm{<figure-callout\; id="3"\; label="R"\; filenames="A20071005240800101.png"\; state="\{\{state\}\}">R</figure-callout>}3}=\frac{V_{\mathrm{cc}}-(V_p+V_{\mathrm{gs}\left(n2\right)}+V_{\mathrm{be}})}{R_3}$

I _B1Reduce Δ I _N4, the electric current among the NMOS pipe n2 becomes

ΔI _n2″＝I _n2+ΔI-ΔI _n3

＝I _n2+ΔI-ΔI _n3

＝I _n2+ΔI-4ΔI·R ₅·g _m(n4)

The suitable R that chooses ₅, g _{M (n4)}Value, can make feedback reach optimum efficiency.

Biasing circuit of the present invention adopts the main body of four metal-oxide-semiconductors and two resistance formation biasing circuits, they produce the bias current with supply independent, mirror image circuit and backfeed loop provide a current component for the biasing main body circuit of supply independent, and the bias current that offset generating circuit is produced plays a stabilization.By adjusting R4, the size of R5 and R3, the current component size of can Control and Feedback returning, stable output.

Behind each parameter setting of this biasing circuit, circuit both can independently be operated in chip internal under the situation of power supply power supply.General this biasing circuit all is used for bias current being provided for other modules at the beginning of the chip power, so its performance is stable most important to chip.After start-up circuit started biasing circuit work, circuit entered normal operating conditions very soon by current mirror.

Claims (4)

1, a kind ofly be with degenerative electric power bias circuit, it is characterized in that: this circuit comprises offset generating circuit (1), mirror image branch (2), feedback branch (3) and electric current output branch road (4);

Offset generating circuit (1) is used to produce the bias current with supply independent, and it is made up of current source I1, I2 and NMOS pipe n1, n2, and NMOS pipe n1, n2 form current-mirror structure, and both grid width and breadth length ratio are all equal; Current source I1 one termination high level Vcc, the drain electrode of another termination n1; The termination high level Vcc of current source I2, the other end and NMOS pipe n2 drain electrode are joined, and insert mirror image branch (2); The grid of NMOS pipe n1 connects the grid of NMOS pipe n2, and joins with the leakage level of NMOS pipe n2; The source ground of NMOS pipe n1 and n2;

Mirror image branch (2) is used for the electric current of mirror image offset generating circuit (1), and current mirror is exported branch road (4) to electric current; Mirror image branch (2) is made up of PMOS pipe p1 and NMOS pipe n3; The source electrode of PMOS pipe p1 meets high level Vcc, and its grid links to each other with drain electrode, inserts electric current output branch road (4), and the drain electrode of receiving NMOS pipe n3; NMOS pipe n3 equates that with the breadth length ratio of NMOS pipe n2 the drain electrode of the grid of NMOS pipe n3 and NMOS pipe n2 is joined, NMOS pipe n3 source ground;

Feedback branch (3) is used to produce the current feedback amount, adjusts the bias current size in the offset generating circuit (1); Feedback branch (3) is made up of current source I3 and equivalent switch SW; The termination high level Vcc of current source I3, the other end and SW one end join, and the drain electrode of NMOS pipe n2 is joined in the other end of SW and the offset generating circuit (1);

Electric current output branch road (4) is used to export stable bias current, and electric current output branch road (4) is made up of PMOS pipe p2; The source electrode of PMOS pipe p2 meets high level Vcc, and the grid of PMOS pipe p1 joins in grid and the mirror image branch (2), drain electrode output offset electric current.

2, according to claim 1ly be with degenerative electric power bias circuit, it is characterized in that: offset generating circuit (1) is by resistance R 1, R2, and PMOS pipe p3, p4 and NMOS pipe n1, n2 constitute, and the breadth length ratio of PMOS pipe p3, p4 is identical; One termination high level Vcc of resistance R 1, the source electrode of another termination PMOS pipe p3, PMOS pipe p3 is that diode connects, and receives PMOS after its grid and drain electrode link to each other again and manages the grid of p4 and the drain electrode that NMOS manages n1; One end and the high level Vcc of resistance R 2 join, the other end is received the source electrode of PMOS pipe p4, the grid of PMOS pipe p4 connects the grid of PMOS pipe p3, grid and the drain electrode of the NMOS pipe n2 that diode connects received in drain electrode, and the emitter of the triode Q1 that is connected with diode of the grid of the grid of NMOS pipe n1, NMOS pipe n3.

3, according to claim 1 and 2ly be with degenerative electric power bias circuit, it is characterized in that: feedback branch (3) comprises the sampling branch road and regulates branch road, a sampling route PMOS pipe p5, resistance R 4, R5 forms, and the breadth length ratio of PMOS pipe p5 and PMOS pipe p1 is m: 1, and the m span is 2-10; The source electrode of PMOS pipe p5 meets high level Vcc, and grid connects the grid of PMOS pipe p1, the end of drain electrode connecting resistance R4; The other end of resistance R 4 and resistance R 5 one ends join, and receive the grid of regulating NMOS pipe n4 in the branch road, the other end ground connection of R5; Regulate a route resistance R 3, NMOS pipe n4 and triode Q1 form; One termination high level Vcc of resistance R 3, the other end joins with the drain electrode of NMOS pipe n4 and base stage and the collector of triode Q1, and inserts output control signal module; The grid of NMOS pipe n4 connects the end that resistance R 5 links to each other with resistance R 4 in the sampling branch road, the source ground of NMOS pipe n4; The emitter of triode Q1 connects the grid of NMOS pipe n2 in the biasing generation module, and its collector links to each other with base stage, receives the end of output control signal module and R3.

4, according to claim 3ly be with degenerative electric power bias circuit, it is characterized in that: the m value is 2 or 4.

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