CN101060100A - Thin film transistor baseplate manufacture method - Google Patents
Thin film transistor baseplate manufacture method Download PDFInfo
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- CN101060100A CN101060100A CN 200610060411 CN200610060411A CN101060100A CN 101060100 A CN101060100 A CN 101060100A CN 200610060411 CN200610060411 CN 200610060411 CN 200610060411 A CN200610060411 A CN 200610060411A CN 101060100 A CN101060100 A CN 101060100A
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Abstract
The disclosed preparation method for TFT base comprises: providing an insulation substrate; forming the grid and pixel electrode with pre-set pattern during a light cover processing; forming doped amorphous silicon pattern, amorphous silicon pattern and the grid insulation layer pattern during another light cover processing; forming a light resistant layer pattern on the doped layer opposite to the grid; depositing a source/drain metal layer on the substrate, doped layer, light resistant pattern and the pixel electrode; removing the light resistant pattern to form source/drain metal layer pattern, etching the part of doped layer opposite to the light resistant layer into a groove; forming the passivated layer pattern, source and drain during another light cover processing. This invention is simple and low cost.
Description
[technical field]
The invention relates to a kind of thin film transistor base plate manufacture method.
[background technology]
At present, LCD replaces conventional cathode ray tube (the Cathode Ray Tube that is used for calculator gradually, CRT) display, and, because characteristics such as LCD has gently, thin, little, make its be fit to very much be applied to desktop PC, laptop computer, personal digital assistant (Personal Digital Assistant, PDA), in portable phone, TV and multiple office automation and the audio-visual equipment.Liquid crystal panel is its primary clustering, its generally comprise a thin film transistor base plate, a colored filter substrate and be clipped in this thin film transistor base plate and this colored filter substrate between liquid crystal layer.
Seeing also Fig. 1, is the structural representation of a traditional thin film transistor base plate 100.This thin film transistor base plate 100 comprises that a substrate 101, is positioned at grid 102, in this substrate 101 and is positioned at gate insulator 103, in this grid 102 and this substrate 101 and is positioned at semiconductor layer 104, on this gate insulator 103 and is positioned at source electrode 105 and drain electrode 106, on this semiconductor layer 104 and this gate insulator 103 and is positioned at passivation layer 107 and in this gate insulator 103, this source electrode 105 and this drain electrode 106 and is positioned at pixel electrode 108 on this passivation layer 107.
One, the first road light shield
(1) forms gate metal layer: a dielectric base 101 is provided, on this dielectric base 101, forms a gate metal layer and one first photoresist layer in regular turn;
(2) form gate pattern: the pattern with the first road light shield carries out exposure imaging to this first photoresist layer, thereby forms a predetermined pattern; This gate metal layer is carried out etching, and then form the pattern of a grid 102, remove first photoresist layer.
Two, the second road light shield
(3) form gate insulator, amorphous silicon and doped amorphous silicon layer: have formation one gate insulator 103, an amorphous silicon and doped amorphous silicon layer and one second photoresist layer on the dielectric base of this grid;
(4) form semiconductor layer pattern: the pattern with the second road light shield carries out exposure imaging to this second photoresist layer, thereby forms a predetermined pattern; This doped amorphous silicon layer and this amorphous silicon layer are carried out etching, and then form semiconductor layer 104, remove second photoresist layer with a predetermined pattern.
Three, the 3rd road light shield
(5) formation source/drain metal layer: on this substrate and this semiconductor layer pattern, form one source/drain metal layer and one the 3rd photoresist layer;
(6) formation source/drain metal layer pattern: the pattern with the 3rd road light shield carries out exposure imaging to the 3rd photoresist layer, thereby forms a predetermined pattern; This source/drain metal layer is carried out etching, and then form an one source pole 105 and a drain electrode 106, and doped amorphous silicon layer is carried out etching form a groove, remove the 3rd photoresist layer again.
Four, the 4th road light shield
(7) form passivation layer: deposition one passivation layer and one the 4th photoresist layer in substrate with this grid, source electrode and drain electrode;
(8) form passivation layer pattern: the pattern with the 4th road light shield carries out exposure imaging to the 4th photoresist layer, thereby forms a predetermined pattern; This passivation layer is carried out etching, and then define the pattern of a passivation layer 107, remove the 4th photoresist layer.
Five, the 5th road light shield
(9) form a conductor layer: in substrate, form a conductor layer and one the 5th photoresist layer with this grid, source electrode, drain electrode and passivation layer pattern;
(10) form pixel electrode pattern: the pattern with the 5th road light shield carries out exposure imaging to the 5th photoresist layer, thereby forms a predetermined pattern; This conductor layer is carried out etching, and then define a conductor layer pattern, promptly pixel electrode pattern 108, remove the 5th photoresist layer.
But this method needs more light shield manufacture process, and the light shield manufacture process comparatively complexity and cost are higher usually, thereby make manufacturing cost higher.In addition, in little shadow production process of light shield manufacture process each time, the pollution of dust and the quality of exposure can directly influence the yield of entire product, therefore, and the chance of the more easy increase reduction product yield of light shield manufacture process.
[summary of the invention]
For solving the complicated and cost problem of higher of above-mentioned thin film transistor base plate manufacturing process, be necessary to provide the thin film transistor base plate that a kind of manufacturing process is simple and cost is low manufacture method.
A kind of thin film transistor base plate manufacture method, its step comprises: a dielectric base is provided; On this dielectric base, deposit a transparent conductive metal layer and a gate metal layer successively; This transparent conductive metal layer is implemented the light shield manufacture process with gate metal layer, form the grid and the pixel electrode of predetermined pattern; In one light shield manufacture process, form impurity-doped amorphous silicon pattern, amorphous silicon pattern and gate insulating layer pattern; Deposition one photoresist layer on this dielectric base, doped amorphous silicon layer and pixel electrode, and be mask with this grid, from a side relative of dielectric base this photoresist layer is exposed with this grid and pixel electrode, on doped amorphous silicon layer to forming a photoresist layer pattern by grid; Deposition one source/drain metal layer on this dielectric base, doped amorphous silicon layer, photoresist layer pattern and pixel electrode; Remove this photoresist layer pattern and on source/drain metal layer segment, formation source/drain metal layer pattern, this doped amorphous silicon layer of a step etching of going forward side by side forms a groove to part that should the photoresist layer pattern; Deposition one passivation layer on this source/drain metal layer pattern and this groove; This passivation layer and source/drain metal layer pattern are implemented the light shield manufacture process one, form passivation layer pattern, source electrode and drain electrode.
Compared to prior art, above-mentioned thin film transistor base plate manufacture method adopts two road light shield manufacture processes with needing in the prior art and the pixel electrode and the grid that form, adopt one light shield manufacture process to form, thereby save the light shield manufacture process one, and, in the step of formation source/drain metal layer pattern, save the light shield of predetermined pattern and directly be that mask exposes to photoresist layer with the grid, make thereby simplify, can effectively reduce cost.
[description of drawings]
Fig. 1 is the thin film transistor base plate structural representation of prior art.
Fig. 2 is the flow chart of the thin film transistor base plate manufacture method of prior art.
Fig. 3 is the schematic diagram of thin film transistor base plate of the present invention.
Fig. 4 is the section enlarged diagram along Fig. 3 line IV-IV.
Fig. 5 is the section enlarged diagram along Fig. 3 line V-V.
Fig. 6 is the flow chart of thin film transistor base plate manufacture method of the present invention.
Fig. 7 is the schematic diagram that forms transparent conductive metal layer, gate metal layer and photoresist layer.
Fig. 8 is the schematic diagram of thin film transistor base plate manufacture method one light shield manufacture process.
Fig. 9 is the schematic diagram that forms light picture group case.
Figure 10 is the schematic diagram of transparent conductive metal layer and gate metal layer pattern.
Figure 11 is the schematic diagram that forms pixel electrode and grid.
Figure 12 is the schematic diagram that forms gate insulator, amorphous silicon and doped amorphous silicon layer.
Figure 13 is the schematic diagram that forms gate insulator, amorphous silicon and doped amorphous silicon layer pattern.
Figure 14 is the schematic diagram that forms photoresist layer.
Figure 15 is the schematic diagram that forms the photoresistance pattern.
Figure 16 is the schematic diagram of formation source/drain metal layer.
Figure 17 is the schematic diagram of formation source/drain metal layer pattern.
Figure 18 is the schematic diagram that forms passivation layer and photoresistance pattern.
Figure 19 is the schematic diagram of shape passivation layer pattern.
Figure 20 is the schematic diagram that removes the photoresist layer pattern.
[embodiment]
Seeing also Fig. 3, is the schematic diagram of thin film transistor base plate of the present invention.This thin film transistor base plate 2 comprises a plurality of gate lines 210, a plurality of data wire 220 and a plurality of common wire 225.These a plurality of gate lines 210 intersect with these a plurality of data wire 220 insulation, and define a plurality of pixel electricity first 200.Each pixel region 200 comprises a thin-film transistor 230, a storage capacitors 240 and a pixel electrode 222.This thin-film transistor 230 is arranged on this gate line 210 and these data wire 220 intersections, and it comprises a grid 223, one source pole 227 and a drain electrode 228.This grid 223 links to each other with these gate line 210 one, and this source electrode 227 is electrically connected with this data wire 220, and this drain electrode 228 is electrically connected with these pixel electrode 222 1 sides.This common wire 225 intersects between pixel electrode 222 and gate line 210 and with this data wire 220, this storage capacitors 240 is arranged on this common wire 225, this storage capacitors 240 comprises a capacitance electrode 229, it is electrically connected with these pixel electrode 222 opposite sides, and this opposite side is relative with a side that connects drain electrode 228.
Seeing also Fig. 4, is the section enlarged diagram along Fig. 3 line IV-IV.This thin film transistor base plate 2 also comprises a dielectric base 201, an electrically conducting transparent line 221, a gate insulating layer pattern 214, an amorphous silicon pattern 215, an impurity-doped amorphous silicon pattern 216 and a passivation layer pattern 219.This electrically conducting transparent line 221, pixel electrode 222 and common wire 225 are arranged at the bottom of this insulation utmost point on 201.This grid 223 is arranged on this electrically conducting transparent line 221 with gate line 210.On the part that intersects with this data wire 220 that this gate insulating layer pattern 214 is arranged on this grid 223, common wire 225 and gate line 210, this amorphous silicon pattern 215 and impurity-doped amorphous silicon pattern 216 are arranged on this gate insulating layer pattern 214 in regular turn.This source electrode 227 and draining 228 is arranged on the impurity-doped amorphous silicon pattern 216 corresponding with this grid 223.This capacitance electrode 229 is arranged on the impurity-doped amorphous silicon pattern 216 corresponding with this common wire 225.This passivation layer pattern 219 is arranged on this thin-film transistor 230 and the storage capacitors 240.
Seeing also Fig. 5, is the section enlarged diagram along Fig. 3 line V-V.This gate line 210 is and the discontinuum of these data wire 220 intersections for disconnecting, yet can be electrically connected the gap of these gate lines 210 by the electrically conducting transparent line 221 of these gate line 210 belows, it can prevent that this gate line 210 from producing with this data wire 220 intersections and open circuit/short circuit.
Seeing also Fig. 6, is the flow chart of thin film transistor base plate manufacture method one better embodiment of the present invention.The manufacture method of this thin film transistor base plate 2 comprises three road light shield manufacture processes, and its concrete steps are as follows:
One, the first road light shield
(S1) form a transparent conductive metal layer and a gate metal layer;
See also Fig. 7, a dielectric base 201 is provided, this dielectric base 201 can be insulation materials such as glass, quartz or pottery; On this dielectric base 201 deposition one transparent conductive metal layer 202, this transparent conductive metal layer 202 can for indium tin oxide (Indium TinOxide, ITO) or indium-zinc oxide (Indium Zinc Oxide, IZO); Deposition one gate metal layer 203 on this transparent conductive metal layer 202, it is metal, molybdenum (Mo), chromium (Cr), tantalum (Ta) or copper (Cu) that its material can be aluminium (Al); Deposition one first photoresist layer 231 on this gate metal layer 203.
(S2) form grid and pixel electrode;
See also Fig. 8, provide a light shield 250 to aim at this first photoresist layer 231, shine this first photoresist layer 231 with ultraviolet light.This light shield 250 is slit light shield (Slit Mask), and it comprises slit area 252 and shading region 251.The light ray energy that the light ray energy that sees through because of this shading region 251 sees through in this slit area 252 is few.Again this photoresist layer 231 is developed, thus formation predetermined pattern as shown in Figure 9, and promptly the part corresponding to this slit area 252 remains photoresist layer 232 remains photoresist layer 233 corresponding to the part of this shading region 251 thin thickness.
See also Figure 10, this gate metal layer 203 and this transparent conductive metal layer 202 are carried out etching, remove this gate metal layer 203 and the transparent conductive metal layer 202 of photoresist layer 232 and 233 unmasked portions, form gate metal layer pattern 213 and transparent conductive metal layer pattern 212.This transparent conductive metal layer pattern 212 comprises three parts such as pixel electrode 222, common wire 225 and electrically conducting transparent line 221.
As shown in figure 11, this residue photoresist layer 232,233 is carried out etching, the photoresist layer 232 of this thinner thickness is all etched away, the corresponding part of grid pole metal layer pattern 213 of etching and this photoresist layer 232 again, it is all etched away, remove residue photoresist layer 233 again and form the grid 223 that is positioned on the electrically conducting transparent line 221.
The manufacturing of this grid 223 of above-mentioned formation has also formed the gate line 210 with these grid 223 one, and this gate line 210 is positioned at this electrically conducting transparent line 221 tops.Promptly this electrically conducting transparent line 221 is positioned at this grid 223 and gate line 210 belows.
Because this gate metal layer 203 and this transparent conductive metal layer 202 are positioned at adjacent level, and grid 223 and pixel electrode 222 are perpendicular to this substrate 201 directions and zero lap, so this step adopts one light shield manufacture process can form grid 223 and pixel electrode 222 simultaneously, compared to prior art, can save light shield one, simplify and make, reduce cost.
Two, the second road light shield
(S3) form gate insulator, amorphous silicon, doped amorphous silicon layer in regular turn;
See also Figure 12, on this dielectric base 201, grid 223, pixel electrode 222 and common wire 225, form the gate insulator 204 that silicon nitride (SiNx) constitutes with chemical gaseous phase depositing process; Use again chemical vapour deposition (CVD) (Chemical Phase Deposition, CVD) method forms an amorphous silicon layer on this gate insulator 204; Carry out one doping process again, this amorphous silicon layer is mixed, form amorphous silicon layer 205 and doped amorphous silicon layer 206.
(S4) form gate insulator, amorphous silicon and impurity-doped amorphous silicon pattern;
See also Figure 13, deposition one second photoresist layer on this doped amorphous silicon layer 206, aim at this second photoresist layer with mask pattern, with this second photoresist layer of ultraviolet light parallel radiation, again this second photoresist layer is developed, this gate insulator 204, amorphous silicon layer 205 and doped amorphous silicon layer 206 are carried out etching, remove the part that gate insulator 204, amorphous silicon layer 205 and doped amorphous silicon layer 206 are not covered by the second photoresist layer structure, form gate insulating layer pattern 214, amorphous silicon pattern 215 and impurity-doped amorphous silicon pattern 216.
(S5) formation source/drain metal layer pattern
See also Figure 14, in this impurity-doped amorphous silicon pattern 216, deposition one the 3rd photoresist layer 241 on dielectric base 201 and the pixel electrode 222, and be mask with this grid 223, the 3rd photoresist layer 241 is exposed and develop from a side relative of dielectric base 201 with this grid 223 and pixel electrode 222, on impurity-doped amorphous silicon pattern 216 to should grid 223 forming the 3rd photoresist layer pattern 242 (as Figure 15), then in this impurity-doped amorphous silicon pattern 216, dielectric base 201, deposition one source/drain metal layer 207 (as Figure 16) on the 3rd photoresist layer pattern 242 and the pixel electrode 222, the 3rd photoresist layer pattern 242 and position source/drain metal layer 207 parts are thereon removed, form one source/drain metal layer pattern 217, the part that 216 pairs of this impurity-doped amorphous silicon pattern of a step etching of going forward side by side should the 3rd photoresist layer pattern 242 forms a groove 226 (as Figure 17).
Three, the 3rd road light shield
(S6) form passivation layer pattern, source electrode and drain electrode;
See also Figure 18, on this groove 226 and source/drain metal layer pattern 217, deposit a passivation layer 209 and one the 4th photoresist layer (figure does not show) in regular turn, aim at the 4th photoresist layer with mask pattern, with ultraviolet light parallel radiation the 4th photoresist layer, again the 4th photoresist layer is developed, form the 4th photoresist layer pattern 252.As shown in figure 19, in regular turn the part that is not covered by the 4th photoresist layer pattern 252 of this passivation layer 209 and source/drain metal layer pattern 217 is carried out etching, the pixel electrode 222 of this part is exposed, and remove the 4th photoresist layer pattern 252 formation source electrodes 227, drain electrode 228, capacitance electrode 229 and passivation layer pattern 219 (as Figure 20).
Compared to prior art, above-mentioned thin film transistor base plate 2 manufacture methods just need to adopt two road manufacturings in the prior art and the pixel electrode 222 and grid 223 that form, adopt one light shield manufacture process to form, thereby save the light shield manufacture process one, and, in the step of formation source/drain metal layer pattern 217, save the light shield of predetermined pattern and be that mask exposes to photoresist layer directly with grid 223, make thereby simplify, can effectively reduce cost.
Claims (10)
1. thin film transistor base plate manufacture method, its step comprises: a dielectric base is provided; On this dielectric base, deposit a transparent conductive metal layer and a gate metal layer successively; This transparent conductive metal layer is implemented the light shield manufacture process with gate metal layer, form the grid and the pixel electrode of predetermined pattern; In one light shield manufacture process, form impurity-doped amorphous silicon pattern, amorphous silicon pattern and gate insulating layer pattern; Deposition one photoresist layer on this dielectric base, doped amorphous silicon layer and pixel electrode, and be mask with this grid, from a side relative of dielectric base this photoresist layer is exposed with this grid and pixel electrode, on doped amorphous silicon layer to forming a photoresist layer pattern by grid; Deposition one source/drain metal layer on this dielectric base, doped amorphous silicon layer, photoresist layer pattern and pixel electrode; Remove this photoresist layer pattern and on source/drain metal layer segment, formation source/drain metal layer pattern, this doped amorphous silicon layer of a step etching of going forward side by side forms a groove to part that should the photoresist layer pattern; Deposition one passivation layer on this source/drain metal layer pattern and this groove; This passivation layer and source/drain metal layer pattern are implemented the light shield manufacture process one, form passivation layer pattern, source electrode and drain electrode.
2. thin film transistor base plate manufacture method as claimed in claim 1, it is characterized in that: the one light shield manufacture process that forms grid and pixel electrode is included in deposition one photoresist layer on this gate metal layer, and providing the slit light shield to the exposure of this photoresist layer and develop forming the step of a photoresist layer pattern, this photoresist layer pattern comprises the zone that a thickness is thicker and the zone of a thinner thickness.
3. thin film transistor base plate manufacture method as claimed in claim 2, it is characterized in that: one light shield manufacture process of this formation grid and pixel electrode further comprises this transparent conductive metal layer of etching and gate metal layer not by the part of this photoresist layer pattern covers, forms transparent conductive metal layer pattern and gate metal layer pattern.
4. thin film transistor base plate manufacture method as claimed in claim 3 is characterized in that: one light shield manufacture process of this formation grid and pixel electrode further comprises the step of this photoresist layer pattern of etching, and the zone of this thinner thickness is all etched away.
5. thin film transistor base plate manufacture method as claimed in claim 4, it is characterized in that: one light shield manufacture process of this formation grid and pixel electrode further comprises this regional corresponding gate metal layer segment that etching is thin with this photoresist layer pattern thickness, the step of the gate line of formation one and this grid one.
6. thin film transistor base plate manufacture method as claimed in claim 5, it is characterized in that: this transparent conductive metal layer pattern comprises further and an electrically conducting transparent line and the common wire of this pixel electrode with one deck that this electrically conducting transparent line is positioned at this grid and gate line below.
7. thin film transistor base plate manufacture method as claimed in claim 6 is characterized in that: this formation impurity-doped amorphous silicon pattern, amorphous silicon pattern are included in the step that forms gate insulator, amorphous silicon, doped amorphous silicon layer and photoresist layer on this dielectric base, grid, pixel electrode and the common wire in regular turn with the light shield manufacture process of gate insulating layer pattern.
8. thin film transistor base plate manufacture method as claimed in claim 7, it is characterized in that: this this formation impurity-doped amorphous silicon pattern, amorphous silicon pattern further comprise the light shield that a predetermined pattern is provided with the light shield manufacture process of gate insulating layer pattern, the step of the exposure and the formation photoresist layer pattern that develops.
9. thin film transistor base plate manufacture method as claimed in claim 1 is characterized in that: one light shield manufacture process of this formation passivation layer pattern, source electrode and drain electrode is included on this source/drain metal layer pattern and the amorphous silicon pattern step of deposit passivation layer and photoresist layer in regular turn.
10. thin film transistor base plate manufacture method as claimed in claim 9, it is characterized in that: one light shield processing procedure of this formation passivation layer pattern, source electrode and drain further comprises the light shield that a predetermined pattern is provided, exposure and the develop step of formation photoresist layer pattern and the step of this passivation layer of etching in regular turn and source/drain metal layer pattern.
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| CNB2006100604115A CN100543968C (en) | 2006-04-21 | 2006-04-21 | The thin film transistor base plate manufacture method |
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|---|---|---|---|
| CNB2006100604115A CN100543968C (en) | 2006-04-21 | 2006-04-21 | The thin film transistor base plate manufacture method |
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| CN101060100A true CN101060100A (en) | 2007-10-24 |
| CN100543968C CN100543968C (en) | 2009-09-23 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101957528A (en) * | 2009-07-14 | 2011-01-26 | 北京京东方光电科技有限公司 | TFT (Thin Film Transistor)-LCD (liquid Crystal Display) array substrate and manufacturing method thereof |
-
2006
- 2006-04-21 CN CNB2006100604115A patent/CN100543968C/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101957528A (en) * | 2009-07-14 | 2011-01-26 | 北京京东方光电科技有限公司 | TFT (Thin Film Transistor)-LCD (liquid Crystal Display) array substrate and manufacturing method thereof |
| CN101957528B (en) * | 2009-07-14 | 2013-02-13 | 北京京东方光电科技有限公司 | TFT (Thin Film Transistor)-LCD (liquid Crystal Display) array substrate and manufacturing method thereof |
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| Publication number | Publication date |
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| CN100543968C (en) | 2009-09-23 |
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