CN101056102A - Meter-checking computing circuit - Google Patents
Meter-checking computing circuit Download PDFInfo
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- CN101056102A CN101056102A CN 200710048775 CN200710048775A CN101056102A CN 101056102 A CN101056102 A CN 101056102A CN 200710048775 CN200710048775 CN 200710048775 CN 200710048775 A CN200710048775 A CN 200710048775A CN 101056102 A CN101056102 A CN 101056102A
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- list item
- meter
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- value
- logical function
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Abstract
The present invention provides a method for realizing the combinational logic circuit through table search operation in the field of designing digital circuit, and the each output bit of table value is represented as a logic function of the input bit of the table index and corresponding logic circuit is also designed. The method includes: a table composed of a series of table values and a series of corresponding table index; each output bit of the table value is represented by the input bit of the table index; the logic function is simplified and then the design of the combinational logic circuit of the logic function is realized. In the table search operation of the multiplexer, the real value table of all the input bits must be decoded entirely, thus, the process is unefficient and is a waste of hardware resources; while in the table search operation of ROM, the process has a high cost and a low speed. The method takes full use of the table characteristic to simplify and optimize the table search operation, and is realized through simple combinational logic, and the operation speed is quick and the hardware resource is saved.
Description
Technical field
The invention belongs to the Design of Digital Circuit field, the combinational logic circuit that specifically relates to a kind of computing of tabling look-up is realized.
Background technology
Popularizing and promoting along with multiple digital audio/video business such as communication, Digital Television, IPTV, mobile TV, video monitoring, Internet videos, design and produce meets newest standards, and (as H.264, MPEG-4) the high-performance multi-media codec chip has become the emphasis of audio frequency and video industry and related chip industry.Because video standard is H.264 when adopting a series of technology and method to improve code efficiency and picture quality, its operand and complexity also improve greatly, so when design chips, abbreviation and optimization be to carry out to the various computings that relate to as far as possible, thereby the operational performance of chip, the cost and the power consumption of minimizing chip improved.
H.264 including the computing of tabling look-up in a large number in the decoder, as being used to judge whether to carry out the threshold alpha of filtering in the block elimination filtering, β tables look-up, tabling look-up among entropy decoding CAVLC or the CABAC.The effectively optimizing of these computings of tabling look-up has material impact for the performance of chip.
Normally, the table look-up hardware implementation method of computing has two kinds: (1) multiplexer; (2) based on the combinational logic of ROM.
As shown in Figure 1, a multiplexer has n bar data input channel and an output channel, and which input channel is the address wire of m position determined link to each other with output channel.The selected input channel of the multiplexer of symbolically is determined by following formula:
Data_Out＝Data_In[Address[k]]
Wherein k is the label of address location.
Realize tabling look-up with multiplexer, multiplexer is imported Data_In with list item value value as data, deciphers Address with the lookup table index index of m position as address wire k, selects which input Data_In passage and exports the Data_Out passage and link to each other.
| |
0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 |
| |
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 2 |
| index | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | 34 | 35 |
| |
2 | 3 | 3 | 3 | 3 | 4 | 4 | 4 | 6 | 6 | 7 | 7 | 8 | 8 | 9 | 9 | 10 | 10 |
| index | 36 | 37 | 38 | 39 | 40 | 41 | 42 | 43 | 44 | 45 | 46 | 47 | 48 | 49 | 50 | 51 | ||
| value | 11 | 11 | 12 | 12 | 13 | 13 | 14 | 14 | 15 | 15 | 16 | 16 | 17 | 17 | 18 | 18 | ||
Table 1
Tabling look-up during computing for example with multiplexer realization table 1, the Data_In (n=52 of 52 data on value hurdle in the table as multiplexer, 52 data input channels), lookup table index index deciphers Address as the address wire k of multiplexer, and (51 need represent with 6bits, so the address wire with the m=6 position), computing of tabling look-up that then this multiplexer can realization table 1.
Multiplexer is to realize tabling look-up simple, the method in common of computing, disclosed as on 05 03rd, 2006, publication number is CN 1767651A, and it is exactly the multiplexer (multiplexer among Fig. 2) that adopts that name is called the parameter calculation circuit of tabling look-up described in the Chinese disclosure of the Invention specification of " the high frequency low frequency of high speed signal of video signal prediction arithmetic unit and method ".But simultaneously,,, and waste hardware resource so this implementation efficient is not high because multiplexer must be deciphered the truth table of all table item index input positions fully.
In addition, simple based on the principle of operation of tabling look-up of ROM, realize but need data/address bus, address bus, decoder etc. to cooperate, and price height, big energy-consuming, speed are slower.
Summary of the invention
The objective of the invention is to overcome above-mentioned deficiency of the prior art, the meter-checking computing circuit that a kind of combinational logic of using in the Design of Digital Circuit field is simple, arithmetic speed is high is provided.
In order to realize the foregoing invention purpose, meter-checking computing circuit of the present invention, comprise:, import the combinational logic circuit that the logical function of position is realized based on each carry-out bit of list item value being expressed as table item index by the table that the table item index of a series of list item values and a series of correspondences is formed.
Described each carry-out bit the list item value is expressed as the logical function of table item index input position, be less list item to occur according to carry-out bit logical value in whole table to set up, have sum-of-product form or product of sum form or use and other forms non-or that represent.Described logical function is through abbreviation.
In addition, during described logic-based function composite design logical circuit, the identical gate circuit that uses between each carry-out bit of list item value can carry out shared, and begins to carry out from shared more position.Can further reduce gate circuit quantity like this.
Meter-checking computing circuit of the present invention is to realize the foregoing invention purpose like this, during specific design, comprises that truth table represents, each carry-out bit of list item value is expressed as logical function, logical function simplification, four steps of gate circuit design of table item index input position:
Step 1: original table is converted to truth table
Step 1.1: it is table item index that the computing of tabling look-up can be regarded input as, is designated as index, and output is the computing of list item value (value).According to the number N um of table item index, determine the number m of input position, promptly represent the length of the binary string of index, m satisfies:
Num＞＞m＝0，(Num＞＞(m-1))＞0
Wherein "＞＞" the expression shifting function.
Similarly, determine the number n of carry-out bit according to the span of list item value.When the list item value is got nonnegative integral value, the length of the binary string of expression value, n satisfies:
value＞＞n＝0，(value＞＞(n-1))＞0
Step 1.2: the binary string i that the index index of original table is converted to the m position
M-1i
M-2Λ i
1i
0, list item value value is converted to the binary string o of n position as output
N-1o
N-2Λ o
1o
0, generate truth table.
Step 2: logical function is represented
This step is each carry-out bit o
jBe expressed as input position i
M-1i
M-2Λ i
1i
0Logical function:
o
j＝f(i
m-1，i
m-2，Λ，i
1，i
0)
Logical function can be long-pending sum, product of sum form.
At each carry-out bit o
j(j=0,1, A, n-1), carry out following operation:
Step 2.1: find out o
j=1 or 0 list item if it is less to equal 1 list item, is just found out o
j=1 list item; If it is less to equal 0 list item, just find out o
j=0 list item.
Step 2.2: the logical function of representing each list item with logical AND, logic OR, logic NOT.
Step 2.3: to o
jThe logical function of=1 list item carries out logic OR, obtains o
jLong-pending sum logical function, perhaps to o
jThe logical function of=0 list item carries out logical AND, obtains o
jThe product of sum logical function.
Step 3: logical function simplification
Utilize the logical function simplification theorem, or utilize logical function simplification software, the long-pending sum or the product of sum logical function of each carry-out bit carried out abbreviation, the abbreviation that obtains the logical function of each carry-out bit is expressed.
Step 4: gate circuit design
According to the logical function behind the abbreviation, design use with door, not gate and or door realize the tabling look-up combinational logic circuit of computing, between each carry-out bit total gate circuit carry out shared, and the shared maximum gate circuit of design earlier, to reach best shared effect, further reduce gate circuit.
Through above-mentioned several steps, finally design meter-checking computing circuit of the present invention, as shown in Figure 2.
Because meter-checking computing circuit of the present invention utilizes the list item value to be constant, each list item value carry-out bit is expressed as the logical function that table item index is imported the position, design corresponding combinational logic circuit.Replace multiplexer of the prior art with this invention, avoided multiplexer the truth table of all table item index input positions must be deciphered fully, efficient is not high, the shortcoming of waste hardware resource.Than the realization of tabling look-up based on ROM, the hardware resource of storage item value has been saved in this invention, has reduced cost, and do not need data/address bus, the cooperation of address bus realizes.
When meter-checking computing circuit of the present invention had special circumstances in the list item value, as in the table when identical list item value is arranged, logical function was more simple, and it is obvious to optimize effect, and implementation efficiency is higher.And the list item value of the table that the computing of tabling look-up is operated can be that the fixed point form is represented or relocatable is represented.
Description of drawings
Fig. 1 is the multiplexer schematic diagrams of using more;
Fig. 2 is a meter-checking computing circuit of the present invention.
Embodiment
Below in conjunction with embodiment, meter-checking computing circuit of the present invention is described in further detail.
In the present embodiment, be example with the computing of tabling look-up of table 1 (H.264 the table 8-16 in the standard, threshold value beta), design a concrete meter-checking computing circuit according to the present invention.
Step 1: original table (table 1) is converted to truth table
The table item index index number of this table is Num=52, so need represent the input position with m=6 position binary string, is expressed as from high to low: i
5i
4i
3i
2i
1i
0
List item value value is 18 to the maximum, so represent carry-out bit with n=5 position binary string, is expressed as o from high to low
4o
3o
2o
1o
0
Original table (table 1) just converts following truth table (table 2) to like this.
| Input position i 5i 4i 3i 2i 1i 0 | Carry-out bit o 4o 3o 2o 1o 0 | Input position i 5i 4i 3i 2i 1i 0 | Carry-out bit o 4o 3o 2o 1o 0 |
| 0 0 0 0 0 0 | 0 0 0 0 0 | 0 1 1 0 1 0 | 0 0 1 1 0 |
| 0 0 0 0 0 1 | 0 0 0 0 0 | 0 1 1 0 1 1 | 0 0 1 1 0 |
| 0 0 0 0 1 0 | 0 0 0 0 0 | 0 1 1 1 0 0 | 0 0 1 1 1 |
| 0 0 0 0 1 1 | 0 0 0 0 0 | 0 1 1 1 0 1 | 0 0 1 1 1 |
| 0 0 0 1 0 0 | 0 0 0 0 0 | 0 1 1 1 1 0 | 0 1 0 0 0 |
| 0 0 0 1 0 1 | 0 0 0 0 0 | 0 1 1 1 1 1 | 0 1 0 0 0 |
| 0 0 0 1 1 0 | 0 0 0 0 0 | 1 0 0 0 0 0 | 0 1 0 0 1 |
| 0 0 0 1 1 1 | 0 0 0 0 0 | 1 0 0 0 0 1 | 0 1 0 0 1 |
| 0 0 1 0 0 0 | 0 0 0 0 0 | 1 0 0 0 1 0 | 0 1 0 1 0 |
| 0 0 1 0 0 1 | 0 0 0 0 0 | 1 0 0 0 1 1 | 0 1 0 1 0 |
| 0 0 1 0 1 0 | 0 0 0 0 0 | 1 0 0 1 0 0 | 0 1 0 1 1 |
| 0 0 1 0 1 1 | 0 0 0 0 0 | 1 0 0 1 0 1 | 0 1 0 1 1 |
| 0 0 1 1 0 0 | 0 0 0 0 0 | 1 0 0 1 1 0 | 0 1 1 0 0 |
| 0 0 1 1 0 1 | 0 0 0 0 0 | 1 0 0 1 1 1 | 0 1 1 0 0 |
| 0 0 1 1 1 0 | 0 0 0 0 0 | 1 0 1 0 0 0 | 0 1 1 0 1 |
| 0 0 1 1 1 1 | 0 0 0 0 0 | 1 0 1 0 0 1 | 0 1 1 0 1 |
| 0 1 0 0 0 0 | 0 0 0 1 0 | 1 0 1 0 1 0 | 0 1 1 1 0 |
| 0 1 0 0 0 1 | 0 0 0 1 0 | 1 0 1 0 1 1 | 0 1 1 1 0 |
| 0 1 0 0 1 0 | 0 0 0 1 0 | 1 0 1 1 0 0 | 0 1 1 1 1 |
| 0 1 0 0 1 1 | 0 0 0 1 1 | 1 0 1 1 0 1 | 0 1 1 1 1 |
| 0 1 0 1 0 0 | 0 0 0 1 1 | 1 0 1 1 1 0 | 1 0 0 0 0 |
| 0 1 0 1 0 1 | 0 0 0 1 1 | 1 0 1 1 1 1 | 1 0 0 0 0 |
| 0 1 0 1 1 0 | 0 0 0 1 1 | 1 1 0 0 0 0 | 1 0 0 0 1 |
| 0 1 0 1 1 1 | 0 0 1 0 0 | 1 1 0 0 0 1 | 1 0 0 0 1 |
| 0 1 1 0 0 0 | 0 0 1 0 0 | 1 1 0 0 1 0 | 1 0 0 1 0 |
| 0 1 1 0 0 1 | 0 0 1 0 0 | 1 1 0 0 1 1 | 1 0 0 1 0 |
Table 2
Step 2: logical function is represented
For simplicity, 6 input position i
5i
4i
3i
2i
1i
0Use capitalization A, B, C, D, E, F represents, use the alphabetical A of line, B, C, D, E, F represents their logic NOT respectively, and AB represents the logical AND of A and B, and A+B represents the logic OR of A and B.
Carry-out bit o
4Logical function, divide following three steps to try to achieve:
(1), finds out o
4The list item that value is less.Herein, o
4=1 list item has only 6, so get o
4=1 truth table (table 3):
| A B C D E F | o 4 |
| 1 0 1 1 1 0 | 1 |
| 1 0 1 1 1 1 | 1 |
| 1 1 0 0 0 0 | 1 |
| 1 1 0 0 0 1 | 1 |
| 1 1 0 0 1 0 | 1 |
| 1 1 0 0 1 1 | 1 |
| Other | 0 |
Table 3
(2), input is expressed as importing the logic NOT of position and the logical function of logical AND, specifically see the following form by (table 4):
| A B C D E F | |
| 1 0 1 1 1 0 | A BCDE F |
| 1 0 1 1 1 1 | A BCDEF |
| 1 1 0 0 0 0 | AB C D E F |
| 1 1 0 0 0 1 | AB C D EF |
| 1 1 0 0 1 0 | AB C DE F |
| 1 1 0 0 1 1 | AB C DEF |
Table 4
(3), o
4Logical function just can be expressed as the long-pending sum of 6 inputs in the table 4: o
4=A BCDE F+A BCDEF+AB C D E F+AB C D EF+AB C DE F+AB C DEF
Similarly, can try to achieve o
3o
2o
1o
0Logical function, as shown in table 5:
| o 3＝ ABCDE F+ ABCDEF+A B C D E F+A B C D E F+A BC DE F+A B C DEF+A B CD E F+A B CD EF +A B CDE F+A B CDEF+A BC D E F+A BC D EF+A BC DEf+A BC DEF+A BCD E F+A BCD EF |
| o 2＝ AB CDEF+ ABC D E F+ ABC D EF+ ABC DE F+ ABC DEF+ ABCD E F+ ABCD EF+A B CDE F +A B CDEF+A BC D E F+A BC D EF+A BC DE f+A BC DEF+A BCD E F+A BCD eF |
| o 1＝ AB C D E F+ AB C D EF+ AB C DE F+ AB C DEF+ AB CD E F+ AB CD EF+ AB CDE F+ ABC DE F + ABC DEF+ ABCD E F+ ABCD EF+A B C DE F+A B C DEF+A B CD E F+A B CD EF +AbC DE F+A BC DEF+ABCD E F+A BCD EF+AB C DE F+AB C DEF |
| o 0＝ AB C DEF+ AB CD F F+ AB CD EF+ AB CDE F+ ABCD E F+ ABCD EF+A B C D E F +A B C D EF+A B CD E F+A B CD EF+A BC D E F+A BC D EF+A BCD E F +A BCD EF+AB C D E F+AB C D EF |
Table 5
Step 3: logical function simplification
According to the logical function simplification theorem, above logical function is carried out abbreviation.Can adopt logical function simplification software to carry out, obtain following result (table 6) behind the abbreviation
| o 4＝A BCDE+AB C D o 3＝ ABCDE+A B C+A B E+A B D o 2＝ AB CDEF+ ABC D+ ABC E+A B CDE+A BC D+A BC E o 1＝ AB C E+ AB C F+ AB DE+ ABD E+A B DE+A BD E+B C DE o 0＝ AB C DEF+ ABD E+ AB CD F+A B E+A C D E |
Table 6
Step 4: gate circuit design.
Design corresponding combinational logic gate circuit according to the logical function behind the abbreviation that obtains in the step 3.
From top instantiation we as can be seen, the computing of tabling look-up of the present invention can realize very simply with the combinational logic gate circuit of the logical function behind the abbreviation, for example carry-out bit o
4Utilize 7 with door, 2 not gates, 1 or can realize.Logical circuit between each carry-out bit can also be shared, for example o
3And o
2Sharing A BC, o
2, o
1And o
0Sharing A B C.And in order further to reduce gate circuit, shared more gate circuit is preferentially designed, to improve shared efficient, for example preferentially design E and D with door, rather than design E and F with door because the shared number of times of DE is more than EF.
Although above the illustrative embodiment of the present invention is described; but should be understood that; the invention is not restricted to the scope of embodiment; to those skilled in the art; as long as various variations appended claim limit and the spirit and scope of the present invention determined in; these variations are conspicuous, and all utilize innovation and creation that the present invention conceives all at the row of protection.
Claims (8)
1. the realization combinational logic circuit of computing of tabling look-up, it is characterized in that, described table is made up of the table item index of a series of list item values and a series of correspondences, the carry-out bit number of list item value is determined by list item value span, table item index input position number is determined by the list item number, described combinational logic circuit is based on and each carry-out bit of list item value is expressed as the logical function of table item index input position realizes.
2. meter-checking computing circuit according to claim 1, it is characterized in that, described each carry-out bit list item value binary string is expressed as the logical function of table item index input position, is less list item to occur according to carry-out bit logical value in whole table to set up.
3. meter-checking computing circuit according to claim 1, its feature exists, and described logical function is a sum-of-product form, perhaps product of sum form or use and other forms non-or that represent.
4. meter-checking computing circuit according to claim 1 is characterized in that described logical function is through abbreviation.
5. meter-checking computing circuit according to claim 1 is characterized in that, during described logic-based function composite design logic gates, the identical gate circuit that uses between each carry-out bit of list item value can carry out shared.
6. meter-checking computing circuit according to claim 1 is characterized in that, during described logic-based function composite design logic gates, and the shared more gate circuit of design earlier.
7. meter-checking computing circuit according to claim 1 is characterized in that, the list item value in the described table is represented with the fixed point form.
8. meter-checking computing circuit according to claim 1 is characterized in that, the list item value in the described table is represented with relocatable.
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|---|---|---|---|
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2017121056A1 (en) * | 2016-01-12 | 2017-07-20 | Boe Technology Group Co., Ltd. | Selection circuit and electronic device |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2017121056A1 (en) * | 2016-01-12 | 2017-07-20 | Boe Technology Group Co., Ltd. | Selection circuit and electronic device |
| CN105610418B (en) * | 2016-01-12 | 2019-01-08 | 京东方科技集团股份有限公司 | A kind of selection circuit and electronic equipment |
| US10305463B2 (en) | 2016-01-12 | 2019-05-28 | Boe Technology Group Co., Ltd. | Selection circuit and electronic device |
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