CN101055891A - Wall embedded grid structure and its making method - Google Patents
Wall embedded grid structure and its making method Download PDFInfo
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- CN101055891A CN101055891A CN 200610073181 CN200610073181A CN101055891A CN 101055891 A CN101055891 A CN 101055891A CN 200610073181 CN200610073181 CN 200610073181 CN 200610073181 A CN200610073181 A CN 200610073181A CN 101055891 A CN101055891 A CN 101055891A
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Abstract
An inlay wall grid structure includes a semiconductor substrate, a groove located in arrangement is in the semiconductor substrate, a grid oxide layer disposed in the groove, as well as a conducting layer disposed on the grid oxide layer, in which the semiconductor substrate in the groove is of multilayer ladder structure. Thd thickness of the grid oxide layer on each ladder face of the multilayer ladder structure can be not identical. Besides, the inlay wall grid structure should also include a plurality of doped regions disposed in the semiconductor substrate under the multilayer ladder structure, and the doping concentration and doping kind of the each doped region under each ladder may be different. The overall length of the carrier channel of this multistage grid structure is the sum of the width (W) and double heights (2H) of this multilayer ladder structure.
Description
Technical field
The present invention relates to a kind of wall embedded grid structure and preparation method thereof, wall embedded grid structure of particularly a kind of charge carrier passage length that increases transistor by the multistage grid structure in the groove and preparation method thereof.
Background technology
A kind of known mos field effect transistor 10 of Fig. 1 illustration (Metal-Oxide-Semiconductor Field Effect Transistor, MOSFET).This transistor 10 is considerable a kind of basic electronic components, and it mainly is to be made of semiconductor substrate 12, gate oxide 14, metal conducting layer 16 and two doped regions 18 (as the drain electrode and the source electrode of transistor) that are arranged in this semiconductor substrate 12.In addition, this transistor 10 comprises the silicon nitride gap wall 22 that is arranged at these metal conducting layer 16 sidewalls in addition, in order to this metal conducting layer 16 of electrical isolation.
Though the transistor 10 of Fig. 1 has been widely used among integrated circuit, but along with the integration of semiconductor technology improves constantly, component size is constantly dwindled, the size of conventional transistor 10 and charge carrier passage length also relatively dwindle, cause these two doped regions 18 to influence the switch control ability of 16 pairs of these charge carrier passages 24 of this metal conducting layer with charge carrier passage 24 interactions that are arranged at gate oxide 14 belows, promptly cause so-called short charge carrier channelling effect (short channeleffect).
Summary of the invention
The present invention's main purpose provides wall embedded grid structure of a kind of charge carrier passage length by interior the multistage grid structure of groove increase transistor and preparation method thereof, the start voltage that dopant concentration in the gate oxide thickness of each stepped surfaces that it also can be by controlling this multistage grid structure and the semiconductor substrate of each ladder below and kind are adjusted this wall embedded grid structure.
For achieving the above object, the present invention proposes a kind of wall embedded grid structure, it comprises semiconductor substrate, be arranged at groove in this semiconductor substrate, be arranged at the gate oxide in this groove and be arranged at conductive layer on this gate oxide, and wherein the semiconductor substrate in this groove is the surface that multistage grid structure and this gate oxide cover this multistage grid structure.The gate oxide thickness of each stepped surfaces of this multistage grid structure can be inequality.In addition, this wall embedded grid structure comprises the doped region in a plurality of semiconductor substrates that are arranged at this multistage grid structure below in addition, and the doping content of these a plurality of doped regions and admixture kind can be inequality.
According to above-mentioned purpose, the present invention proposes a kind of preparation method of wall embedded grid structure, its at first form have opening mask layer on semiconductor substrate, form again and have the groove of multistage grid structure in the semiconductor substrate of this opening below.Afterwards, carry out thermal oxidation technology, form the conductive layer that fills up this groove at least again to form gate oxide in this groove.Preferably, form groove and in the semiconductor substrate of this opening below, comprise and utilize this mask layer to be etching mask, carry out etch process to form first recess in the semiconductor substrate of this opening below.Afterwards, utilize deposition and etch-back technics to form first clearance wall wall within this first recess, utilize this mask layer and this first clearance wall to be etching mask again, this semiconductor substrate of etching is to form in the semiconductor substrate of second recess between this first clearance wall.
Form groove and can comprise in addition in the semiconductor substrate of this opening below and carry out repeatedly doping process, admixture is implanted in the semiconductor substrate of this multistage grid structure below, the dopant dose of wherein above-mentioned repeatedly doping process and admixture kind can be inequality.Furtherly, the admixture of above-mentioned repeatedly doping process is selected from the group of nitrogen ion, nitrogen ion, nitrous oxide ion and nitrogen oxide ion composition, can suppress the reaction rate of follow-up thermal oxidation technology, that is controls the thickness of this gate oxide.In addition, the admixture boracic admixture of above-mentioned repeatedly doping process or phosphorous admixture can be adjusted the start voltage of this wall embedded grid structure.
With the charge carrier passage of known technology is to adopt horizontal structure and the only rough width that equals this grid of its length is compared, it is the summation of width (W) and two times of height (2H) of this multistage grid structure that the charge carrier passage of wall embedded grid structure of the present invention adopts multistage grid structure and its entire length, obviously have long charge carrier passage length than known technology, can effectively solve short charge carrier channelling effect.Moreover the present invention is by carrying out repeatedly the doping process of different admixtures and dopant dose, the thickness of this gate oxide of may command and the start voltage (V of this wall embedded grid structure in the preparation process of this multistage grid structure
Th), and then the usefulness of oxide-semiconductor control transistors.
Description of drawings
A kind of known mos field effect transistor of Fig. 1 illustration;
The preparation method of Fig. 2 to Fig. 9 illustration wall embedded grid structure of the present invention;
The preparation method of the multistage grid structure of Figure 10 to Figure 13 illustration another embodiment of the present invention; And
The wall embedded grid structure of Figure 14 illustration another embodiment of the present invention.
The main element symbol description
10 transistors, 12 semiconductor substrates
14 gate oxides, 16 conductive layers
18 doped regions, 22 clearance walls
24 charge carrier passages, 30 wall embedded grid structures
32 semiconductor substrates, 34 mask layers
36 openings, 37 first surfaces
38 first recesses, 40 dielectric layers
40 ' the first clearance walls, 41 second surfaces
42 second recesses, 44 ' the second clearance walls
45 the 3rd surfaces, 46 the 3rd recesses
48 multistage grid structure, 48 ' multistage grid structure
50 groove 52A doped regions
52B doped region 52C doped region
54 gate oxides, 54 ' gate oxide
56 conductive layers, 58 charge carrier passages
60 doped regions, 62 mask layers
62 ' mask layer, 62 " mask layers
72A predetermined portions 72B predetermined portions
76 multistage grid structure, 80 grooves
90 wall embedded grid structures
Embodiment
The preparation method of Fig. 2 to Fig. 9 illustration the present invention's wall embedded grid structure 30.At first form and have the mask layer 34 of opening 36 on semiconductor substrate 32 (for example silicon substrate), utilize this mask layer 34 to be etching mask again, carry out first recess 38 that etch process has first surface 37 with formation in the semiconductor substrate 32 of these opening 36 belows, this first surface 37 comprises the bottom surface and the sidewall of this first recess 38.This mask layer 34 is preferably by dielectric material (for example silica) and constitutes.Afterwards, carry out doping process, the semiconductor substrate 32 of admixture being implanted these first recess, 38 belows is to form doped region 52A, as shown in Figure 3.
With reference to Fig. 4, carry out depositing operation, form dielectric layer 40 on this semiconductor substrate 32, this dielectric layer 40 is preferably bottom surface and the sidewall that is constituted and covered this first recess 38 by silica.Afterwards, carry out etch-back technics to form first clearance wall 40 ' wall within this first recess 38, utilize this mask layer 34 and this first clearance wall 40 ' for etching mask again, this semiconductor substrate 32 of etching has second recess 42 of second surface 41 with formation, and this second surface 41 comprises the bottom surface and the sidewall of this second recess 42.The depth D 1 of this first recess 38 is less than the depth D 2 of this second recess 42.Then, carry out doping process, the semiconductor substrate 32 of admixture being implanted these second recess, 42 belows is to form doped region 52B, as shown in Figure 5.
With reference to Fig. 6, utilize deposition and etch-back technics, form second clearance wall 44 ' wall within this second recess 42.This second clearance wall 44 ' be preferably by silica constitutes.Afterwards, utilize this mask layer 34, this first clearance wall 40 ' and this second clearance wall 44 ' be etching mask, this semiconductor substrate 32 of etching has the 3rd recess 46 on one the 3rd surface 45 with formation, and this 3rd surface 45 comprises the bottom surface and the sidewall of the 3rd recess 46.Then, carry out doping process, the semiconductor substrate 32 of admixture being implanted the 3rd recess 46 belows is to form doped region 52C, as shown in Figure 7.
With reference to Fig. 8, utilize etch process remove this mask layer 34, this first clearance wall 40 ' and this second clearance wall 44 ', promptly form groove 50 among this semiconductor substrate 32, and first recess 38 in this groove 50, second recess 42 and the 3rd recess 46 constitute multistage grid structure 48.Afterwards, carry out thermal oxidation technology to form gate oxide 54 in these semiconductor substrate 32 surfaces and carry out depositing operation to form conductive layer 56 on this gate oxide 54.The spy's, the gate oxide 54 of this thermal oxidation technology formation covers this multistage grid structure 48.
Afterwards, gate oxide 54 and the conductive layer 56 that utilizes the photoengraving carving technology to remove a part promptly finished this wall embedded grid structure 30.Then, utilize this wall embedded grid structure 30 to carry out another doping process to form two doped regions 60 (as source electrode and drain electrode) among the semiconductor substrate 32 of these wall embedded grid structure 30 both sides, as shown in Figure 9 for the doping mask.Furtherly, the charge carrier passage 58 of this wall embedded grid structure 30 is positioned at the semiconductor substrate 32 of these multistage grid structure 48 belows, and its entire length is about the summation of width (W) and two times of height (2H) of this multistage grid structure 48.
The dopant dose of Fig. 3, Fig. 5 and doping process shown in Figure 7 can be inequality, that is the doping content of above-mentioned a plurality of doped region 52A, 52B and 52C can be inequality, and doping process is not limited to only implant side under each recess, also can be the surface of whole corresponding recess.Furtherly, the nitrogenous admixture of the admixture of above-mentioned repeatedly doping process, the group that it is selected from nitrogen ion, nitrogen ion, nitrous oxide ion and nitrogen oxide ion composition can suppress the reaction rate of follow-up thermal oxidation technology, that is controls the thickness of this gate oxide 54.So, the nitrogenous admixture of different dopant doses can cause each ladder (recess) surface of this multistage grid structure 48 to have gate oxide inequality 54 thickness, and can cause the thickness of gate oxide 54 of a certain recess surface of this multistage grid structure 48 to be different from the thickness of the gate oxide 54 of this another recess surface, and be controlled the start voltage of this wall embedded grid structure 30.
The preparation method of the multistage grid structure 80 of Figure 10 to Figure 13 illustration another embodiment of the present invention.At first form mask layer 62 on semiconductor substrate 32, utilize the photoengraving carving technology to remove the mask layer 62 of predetermined portions 72A again, the mask layer 62 of reservation ' then the cover semiconductor substrate 32 of presumptive area.Preferably, this mask layer 62 is photoresist layer or dielectric layer (for example silica formation).Afterwards, utilize that this mask layer 62 ' for etching mask, this semiconductor substrate 32 of etching can form one deck ladder 74A among this semiconductor substrate 32, as shown in figure 11.
With reference to Figure 12, utilize the photoengraving carving technology remove the mask layer 62 of predetermined portions 72B ', " be etching mask, this semiconductor substrate 32 of etching is with formation groove 80; it has the multistage grid structure 76 of two layers of ladder 74A, 74B, as shown in figure 13 to utilize the mask layer 62 of reservations again.Furtherly, can form groove by the technology that repeats Figure 12 and Figure 13 with different ladder numbers layer hierarchic structure.
The wall embedded grid structure 90 of Figure 14 illustration another embodiment of the present invention.The thickness of the gate oxide 54 of wall embedded grid structure 30 on this multistage grid structure 48 of comparing Fig. 7 is identical, the gate oxide 54 of the wall embedded grid structure 90 of Figure 14 ' this multistage grid structure 48 ' on thickness and inequality.The preparation method of this wall embedded grid structure 90 is identical generally with the wall embedded grid structure of Fig. 7 30, only in the doping content of the first surface 37 of first recess 38 doping content less than the 3rd surface 45 of the second surface 41 of second recess 42 and the 3rd recess 46.So, the multistage grid structure 48 of formation ' gate oxide 54 ' in the thickness difference of each stepped surfaces.Furtherly, the thickness of the gate oxide 54 on the first surface 37 is greater than the gate oxide 54 on second surface 41 and the 3rd surface 45.
In addition, the admixture of above-mentioned repeatedly doping process use also can be selected boracic admixture or phosphorous admixture for use except aforementioned nitrogenous admixture, that is the admixture kind of above-mentioned repeatedly doping process can be inequality.Furtherly, this boracic admixture or phosphorous admixture can increase the interior carrier concentration of this charge carrier passage 58, and are adjusted the start voltage of this wall embedded grid structure 90.
With the charge carrier passage of known technology is to adopt horizontal structure and the only rough width that equals this grid of its length is compared, it is the summation of width (W) and two times of height (2H) of this multistage grid structure that the charge carrier passage of wall embedded grid structure of the present invention adopts multi-step knot and its entire length, obviously have long charge carrier passage length than known technology, can effectively solve short charge carrier channelling effect.Moreover, among one of the present invention embodiment by in the preparation process of this multistage grid structure, carrying out repeatedly the doping process of different admixtures and dopant dose, the thickness of this gate oxide of may command and the start voltage of this wall embedded grid structure, and then the usefulness of oxide-semiconductor control transistors.
The present invention's technology contents and technical characterstic disclose as above, yet the person of ordinary skill in the field still may be based on the present invention's teaching and announcement and done all replacement and improvement that does not deviate from spirit of the present invention.Therefore, the present invention's protection range should be not limited to those disclosed embodiments, and should comprise various replacement and the improvement that do not deviate from the present invention, and is contained by claim.
Claims (20)
1. wall embedded grid structure is characterized in that comprising:
Semiconductor substrate has groove, and this groove in semiconductor substrate be multistage grid structure, it has at least one first recess and one second recess;
Gate oxide is arranged in this groove; And
Conductive layer is arranged on this gate oxide.
2. the wall embedded grid structure according to claim 1 is characterized in that this gate oxide covers on this multistage grid structure of this groove.
3. the wall embedded grid structure according to claim 1 is characterized in that this first recess has first surface, and this second recess has second surface, and the gate oxide thickness on this first surface is different from the gate oxide thickness on this second surface.
4. the wall embedded grid structure according to claim 3 it is characterized in that the degree of depth of the degree of depth of this first recess less than this second recess, and the gate oxide thickness on this first surface is greater than the gate oxide thickness on this second surface.
5. the wall embedded grid structure according to claim 1 is characterized in that also comprising a plurality of doped regions, is arranged in the semiconductor substrate of this multistage grid structure below.
6. the wall embedded grid structure according to claim 5 is characterized in that these a plurality of doped regions comprise:
First doped region is arranged in the semiconductor substrate of this first recess below; And
Second doped region is arranged in the semiconductor substrate of this second recess below, and wherein the doping content of this second doped region is different from the doping content of this first doped region.
7. the wall embedded grid structure according to claim 5 is characterized in that the admixture kind of above-mentioned a plurality of doped region is inequality.
8. the wall embedded grid structure according to claim 1 is characterized in that comprising the charge carrier passage in addition, is arranged in the semiconductor substrate of this beneath trenches.
9. the preparation method of a wall embedded grid structure is characterized in that comprising the following step:
Form mask layer on semiconductor substrate, this mask layer has opening;
Form groove in the semiconductor substrate of this opening below, wherein the semiconductor substrate in this groove is multistage grid structure;
Carry out thermal oxidation technology, form gate oxide in this groove; And
Form conductive layer, it fills up this groove at least.
10. according to the preparation method of the described wall embedded grid structure of claim 9, it is characterized in that forming this groove and in the semiconductor substrate of this opening below, comprise and carry out repeatedly doping process, admixture is implanted in the semiconductor substrate of this multistage grid structure below.
11., it is characterized in that the dopant dose of above-mentioned repeatedly doping process is inequality according to the preparation method of the described wall embedded grid structure of claim 10.
12., it is characterized in that the admixture kind of above-mentioned repeatedly doping process is inequality according to the preparation method of the described wall embedded grid structure of claim 10.
13., it is characterized in that the admixture of above-mentioned repeatedly doping process is selected from the group of nitrogen ion, nitrogen ion, nitrous oxide ion and nitrogen oxide ion composition according to the preparation method of the described wall embedded grid structure of claim 10.
14., it is characterized in that the admixture boracic admixture or the phosphorous admixture of above-mentioned repeatedly doping process according to the preparation method of the described wall embedded grid structure of claim 10.
15., it is characterized in that forming groove and in the semiconductor substrate of this opening below, comprise according to the preparation method of the described wall embedded grid structure of claim 9;
Form first recess in the semiconductor substrate of this opening below;
Form first clearance wall wall within this first recess; And
Utilize this first clearance wall to be etching mask, this semiconductor substrate of etching is to form second recess.
16., it is characterized in that before forming this first clearance wall that other comprises and carries out doping process with in the semiconductor substrate of admixture being implanted this first recess below according to the preparation method of the described wall embedded grid structure of claim 15.
17., it is characterized in that comprising in addition and carry out doping process with in the semiconductor substrate of admixture being implanted this second recess below according to the preparation method of the described wall embedded grid structure of claim 15.
18., it is characterized in that comprising in addition the following step according to the preparation method of the described wall embedded grid structure of claim 15:
Form second clearance wall wall within this second recess; And
Utilize this second clearance wall to be etching mask, this semiconductor substrate of etching is to form the 3rd recess.
19., it is characterized in that the formation of this multistage grid structure comprises according to the preparation method of the described wall embedded grid structure of claim 9;
Utilize this mask layer to be etching mask, this semiconductor substrate of etching;
Remove the mask layer of reservations branch; And
Utilize this mask layer to be etching mask, this semiconductor substrate of etching.
20., it is characterized in that this mask layer is photoresist layer or dielectric layer according to the preparation method of the described wall embedded grid structure of claim 19.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2006100731816A CN100468768C (en) | 2006-04-10 | 2006-04-10 | Wall embedded grid structure and its making method |
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| Application Number | Priority Date | Filing Date | Title |
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| CNB2006100731816A CN100468768C (en) | 2006-04-10 | 2006-04-10 | Wall embedded grid structure and its making method |
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| CN101055891A true CN101055891A (en) | 2007-10-17 |
| CN100468768C CN100468768C (en) | 2009-03-11 |
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| CNB2006100731816A Expired - Fee Related CN100468768C (en) | 2006-04-10 | 2006-04-10 | Wall embedded grid structure and its making method |
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102738226A (en) * | 2011-04-07 | 2012-10-17 | 南亚科技股份有限公司 | Power device with trenched gate structure and method of fabricating the same |
| CN104022028A (en) * | 2014-06-11 | 2014-09-03 | 上海华力微电子有限公司 | Grid electrode structure and manufacturing method thereof |
| CN109755325A (en) * | 2017-11-01 | 2019-05-14 | 北京大学 | A kind of novel double-groove type metal oxide semiconductor barrier Schottky diode structure and implementation method |
| CN110400846A (en) * | 2019-08-19 | 2019-11-01 | 无锡橙芯微电子科技有限公司 | With ladder deep trouth shield grid MOS structure and production method |
| CN111446167A (en) * | 2020-03-16 | 2020-07-24 | 绍兴同芯成集成电路有限公司 | Process for generating multi-step groove transistor by using polymer isolation layer |
| CN111564495A (en) * | 2020-04-08 | 2020-08-21 | 中国科学院微电子研究所 | Dual channel MOSFET, buried channel transistor and method of manufacture |
-
2006
- 2006-04-10 CN CNB2006100731816A patent/CN100468768C/en not_active Expired - Fee Related
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102738226A (en) * | 2011-04-07 | 2012-10-17 | 南亚科技股份有限公司 | Power device with trenched gate structure and method of fabricating the same |
| CN104022028A (en) * | 2014-06-11 | 2014-09-03 | 上海华力微电子有限公司 | Grid electrode structure and manufacturing method thereof |
| CN109755325A (en) * | 2017-11-01 | 2019-05-14 | 北京大学 | A kind of novel double-groove type metal oxide semiconductor barrier Schottky diode structure and implementation method |
| CN110400846A (en) * | 2019-08-19 | 2019-11-01 | 无锡橙芯微电子科技有限公司 | With ladder deep trouth shield grid MOS structure and production method |
| CN111446167A (en) * | 2020-03-16 | 2020-07-24 | 绍兴同芯成集成电路有限公司 | Process for generating multi-step groove transistor by using polymer isolation layer |
| CN111564495A (en) * | 2020-04-08 | 2020-08-21 | 中国科学院微电子研究所 | Dual channel MOSFET, buried channel transistor and method of manufacture |
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| Publication number | Publication date |
|---|---|
| CN100468768C (en) | 2009-03-11 |
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