CN101051829A - Reverse gate delay line with delay regulating circuit - Google Patents
Reverse gate delay line with delay regulating circuit Download PDFInfo
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- CN101051829A CN101051829A CN 200710089731 CN200710089731A CN101051829A CN 101051829 A CN101051829 A CN 101051829A CN 200710089731 CN200710089731 CN 200710089731 CN 200710089731 A CN200710089731 A CN 200710089731A CN 101051829 A CN101051829 A CN 101051829A
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- delay line
- reverse gate
- gate delay
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Abstract
The invention discloses NOT gate delay circuit (NGDC) with lag adjustment circuit. The digital circuit includes following portions and relevant connections: multiple NOT gates of NGDC are connected in series; multiple NOT gates of replicated NGDC are connected in series; any flip flop unit (FFU) is connected to corresponding NOT gate of the replicated NGDC; FFU is in use for storing binary information; encoder is connected to multiple FFU; delay selector is connected to the encoder and multiple NOT gates of NGDC respectively. The method includes steps: NOT gates of replicated NGDC receive first signal; first FFU receives second signal, which possesses time delay related to first signal; FFU is in use for storing binary information generated by first signal and second signal; number of related NOT gates is decided by binary information. The invention possesses function not sensitive to temperature of individual NOT gate, voltage of power supply, and influence from fabricating process.
Description
Technical field
The present invention relates to a kind of reverse gate delay line, specially refer to a kind of apparatus and method that are used for determining in reverse gate delay line received signal time delay with delay regulating circuit.
Background technology
Delay Element is made of the Different Logic function that similarly is inverter and so on, is used for signal path is inserted in default delay.If desired a plurality of these type of delay cells are used for the panel data transmission, then this type of unit will be subjected between individual elements, for example bad influence of coupling on temperature, supply voltage, manufacture process and the chip.The Delay Element that similarly is reverse gate delay line and so on uses widely in various data transmission systems.Above-mentioned Delay Element mainly is applied as: insert in the signal path with known time interval, postpone or corrected signal shape, for example its duty cycle and cycle to increase.All Delay Elements all utilize via accumulateing essential transmission delay in transistorized.The adjustment of transistor size (width, length) and operating condition (capacitive load, temperature, voltage supply etc.) will cause signal delay control to a certain degree.Manufacture process can cause in Delay Element chips-to the difference of-chip.
At present, in conventional art, reverse gate delay line uses usually and insert default delay in signal path.Yet this type of reverse gate delay line also can be subjected between indivedual locks: the bad influence of coupling on temperature, supply voltage, manufacture process and the chip.In other words, the time delay of reverse gate delay line can be along with between indivedual locks: the bad influence of coupling on temperature, supply voltage, manufacture process and the chip and changing.
In addition, the extra and great reason that postpone to change is to stride the thermal gradient of this chip, and this chip has for example power consumption of some functional unit uneven distribution of frequency drives and bus driver.When this power consumption changes in time by change driving the source, the signal delay that this thermal gradient can change between data channel to be wanted.
Therefore, how a kind of Improvement type delay device that is used for data channel that has is provided, it can determine the time delay in the reverse gate delay line received signal, its influence for temperature, supply voltage and manufacture process between indivedual anti-phase locks simultaneously is also insensitive, becomes problem demanding prompt solution.
Summary of the invention
Technical problem to be solved by this invention provides a kind of reverse gate delay line with delay regulating circuit, it can determine the time delay in this reverse gate delay line received signal, and its influence for temperature, supply voltage and manufacture process between indivedual anti-phase locks is also insensitive.
In order to realize above-mentioned technical problem, on the one hand, the invention provides a kind of digital circuit, it comprises: a reverse gate delay line and a delay regulating circuit is characterized in that: described reverse gate delay line comprises a plurality of anti-phase locks that are connected in series that are used to receive a sequence data; Described delay regulating circuit comprises that a delay selector, encoder, flip-flop array and one duplicate reverse gate delay line; The described reverse gate delay line that duplicates comprises a plurality of anti-phase locks that are connected in series, and these a plurality of anti-phase locks are used to receive first signal; Described flip-flop array is made up of a plurality of flip-flops, any flip-flop is electrically connected to this corresponding anti-phase lock that duplicates reverse gate delay line, these a plurality of flip-flops are used to store binary message, and its first flip-flop receives the secondary signal that has time delay with respect to described first signal; Described encoder is electrically connected to this a plurality of flip-flops, and it is according to the binary message that is stored in a plurality of flip-flops, in order to determine the number of the required anti-phase lock of this reverse gate delay line; Described delay selector electrically connects a plurality of anti-phase lock of described encoder and reverse gate delay line respectively, it is caused the delay of this sequence data by the anti-phase lock of described reverse gate delay line, the number of the anti-phase lock of this reverse gate delay line is that the output by encoder decides.
Described a plurality of flip-flop is a D-type flip-flop.
The described a plurality of anti-phase lock that duplicates reverse gate delay line is identical with a plurality of anti-phase lock of reverse gate delay line.
Time delay in the described reverse gate delay line institute receiving sequence data is insensitive for the influence of temperature, supply voltage or manufacture process between indivedual anti-phase locks.
Described first signal is to rise the edge signal and fall one of edge signal.
Described secondary signal is to rise the edge signal and fall one of edge signal.
On the other hand, the invention provides a kind of method that is used for being provided at the digital circuit time delay, may further comprise the steps in regular turn:
A reverse gate delay line is provided, and it comprises a plurality of anti-phase locks that are connected in series that are used for the receiving sequence data;
Provide one to duplicate reverse gate delay line, it comprises a plurality of anti-phase locks that are connected in series, and these a plurality of anti-phase locks are designed to receive first signal;
A plurality of flip-flops are provided, wherein first flip-flop of these a plurality of flip-flops receives secondary signal, it has the time delay with respect to described first signal, and these a plurality of flip-flops are used to store the binary message that is produced by described first signal and secondary signal;
Decide the number of anti-phase lock required in the described reverse gate delay line according to the binary message that in described a plurality of flip-flops, stores;
And the delay that causes described sequence data by the anti-phase lock of this reverse gate delay line, the number of the anti-phase lock of this reverse gate delay line is that the output by described encoder decides.
Described a plurality of flip-flop is a D-type flip-flop.
The described a plurality of anti-phase lock that duplicates reverse gate delay line is identical with a plurality of anti-phase lock of described reverse gate delay line.
Time delay in the described reverse gate delay line institute receiving sequence data is insensitive for the influence of temperature, supply voltage or manufacture process between indivedual anti-phase locks.
Described first signal is to rise the edge signal and fall one of edge signal.
Described secondary signal is to rise the edge signal and fall one of edge signal.
Owing to adopted technique scheme, the a plurality of anti-phase lock that wherein duplicates in the reverse gate delay line receives first signal, a plurality of flip-flops are used to store binary message, its first flip-flop receives the secondary signal that has time delay with respect to described first signal, encoder is according to the binary message that is stored in a plurality of flip-flops, in order to determine the number of the required anti-phase lock of this reverse gate delay line, cause the delay of this sequence data by the anti-phase lock of reverse gate delay line, the number of the anti-phase lock of reverse gate delay line is decided by the output of encoder, therefore, the present invention has for the temperature between indivedual anti-phase locks, supply voltage, and the insensitive function of the influence of manufacture process.
Description of drawings
The present invention is further detailed explanation below in conjunction with the drawings and specific embodiments.
Fig. 1 is for having the circuit diagram of the preferential embodiment of reverse gate delay line of delay regulating circuit according to the present invention.
Fig. 2 has the signal PA that rises edge and the oscillogram of signal PB for the above-mentioned preferential embodiment's according to the present invention.
Among the figure, reverse gate delay line 110, anti-phase lock 110-1～anti-phase lock 110-N, sequence data 111, delayed sequence data 111
1～111
N-1, postpone selection wire 120, delayed sequence data 121, encoder 130, signal 131, flip-flop array 140, flip-flop 140-1～140-N duplicates reverse gate delay line 150, anti-phase lock 150-1～150-N, signal PA, inhibit signal PA
1～PA
N-1, signal PB, time durations T.
Embodiment
As shown in Figure 1, it is the circuit diagram that the present invention has the preferential embodiment of reverse gate delay line of delay regulating circuit.A kind of digital circuit comprises a reverse gate delay line 110 and a delay regulating circuit.The D-type flip-flop array 140 that delay regulating circuit comprises a delay selector 120, encoder 130, be made up of a plurality of D-type flip-flops (DFF) 140-1 to 140-N and one duplicate reverse gate delay line 150.Duplicate reverse gate delay line 150 and have the circuit structure identical with reverse gate delay line 110, for example: transistor size (width, length), with operating condition (capacitive load, temperature, voltage supply etc.).Use delay regulating circuit with the time delay of decision in 110 receiving sequence data of reverse gate delay line, the influence of its temperature for indivedual anti-phase locks, supply voltage and manufacture process is also insensitive.
In the present embodiment, reverse gate delay line 110 comprises a plurality of anti-phase lock 110-1 to 110-N that are connected in series, and wherein N is as required and default natural number, and will change according to specific implementation method.The anti-phase lock 110-1 receiving sequence data 111 of reverse gate delay line 110.Anti-phase lock 110-1 to 110-N-1 successively with its content delivery to next anti-phase lock.That is to say, on the reference frequency signal that each applied (not icon), sequence data 111 is sent to anti-phase lock 110-1, delayed sequence data 111
1Be sent to anti-phase lock 110-2 from anti-phase lock 110-1, with delayed sequence data 111
2Be sent to anti-phase lock 110-3 from anti-phase lock 110-2, with delayed sequence data 111
3Be sent to anti-phase lock 110-4 from anti-phase lock 110-3 ..., with delayed sequence data 111
N-2Be sent to anti-phase lock 110-N-1 from anti-phase lock 110-N-2, and with delayed sequence data 111
N-1Be sent to anti-phase lock 110-N from anti-phase lock 110-N-1.In other words, sequence data 111 is sent to next anti-phase lock gradually, with the response reference frequency signal.The respectively output of anti-phase lock 110-1 to 110-N electrically connects with postponing selector 120, and its content can be sent to delay selector 120, with the response reference frequency signal.The output that postpones selector 120 is that the output valve by encoder 130 is determined.This promptly is that in response to the output valve of encoder 130, delay selector 120 is downloaded in anti-phase lock 110-1 to the 110-N output.The sequence data 111 that a plurality of anti-phase lock postponed is that the output valve by encoder 130 is determined.
Duplicate reverse gate delay line 150 and comprise a plurality of anti-phase lock 150-1 to 150-N that are connected in series, wherein N is as required and default natural number, and will depend on its execution and change.Duplicate reverse gate delay line 150 and have the circuit structure identical with reverse gate delay line 110, for example: transistor size (width, length), with operating condition (capacitive load, temperature, voltage supply etc.).Duplicate preceding (or back) edge of reverse gate delay line 150 received signal PA.Each anti-phase lock 150-1 to 150-N is sent to next anti-phase lock with its content.This promptly is on the reference frequency signal that is applied (not icon), signal PA to be sent to anti-phase lock 150-1, with inhibit signal PA
1Be sent to anti-phase lock 150-2 from anti-phase lock 150-1, with inhibit signal PA
2Be sent to anti-phase lock 150-3 from anti-phase lock 150-2, with inhibit signal PA
3Be sent to anti-phase lock 150-4 from anti-phase lock 150-3 ..., with inhibit signal PA
N-2Be sent to anti-phase lock 150-N-1 from anti-phase lock 150-N-2, and with inhibit signal PA
N-1Be sent to anti-phase lock 150-N from anti-phase lock 150-N-1.In other words, signal PA is sent to next anti-phase lock gradually, with the response reference frequency signal.Each output of anti-phase lock 150-1 to 150-N is connected to: each corresponding D-type flip-flop (DFF) 140-1 to 140-N.In other words, the output valve of anti-phase lock 150-1 to 150-N is stored in respectively among corresponding D-type flip-flop (DFF) 140-1 to 140-N with the response reference frequency signal.
After the T, signal PB is sent to D-type flip-flop (DFF) 140-1 during anti-phase lock 150-1 received signal PA a period of time, wherein, this signal PB has the time delay T with respect to signal PA, sees Fig. 2.This time postpones T and is directly proportional with the cycle of reference frequency signal.For example, behind T during anti-phase lock 150-1 received signal PA a period of time, signal PB is sent to D-type flip-flop (DFF) 140-1.This D-type flip-flop (DFF) 140-1 stores of binary message, and the basic function of this D-type flip-flop (DFF) is: store of binary message, i.e. binary one or 0.Suppose at time durations T, the edge that rises of signal PA is sent to anti-phase lock 150-4 from anti-phase lock 150-1, promptly this moment, D-type flip-flop (DFF) 140-4 was used to store binary message 1, other D-type flip-flop (DFF) is used for storing binary message 0, its exceptant is D-type flip-flop (DFF) 140-1 and 140-4, it is used for storing binary message 1, with the response reference frequency signal, therefore, the binary message that this is stored in the D-type flip-flop (DFF) can be defined as " 1001000000 ... 00 ".In addition, the output electric property of D-type flip-flop (DFF) 140-1 to 140-N is connected to encoder 130.Encoder 130 can be according to stored binary message in this D-type flip-flop, and calculates the number at the required anti-phase lock of reverse gate delay line 110.In above example, the number of the required anti-phase lock of reverse gate delay line 110 is 3.Therefore, encoder 130 output signals 131, are used for default delay is placed in signal path to select the number of reverse gate delay line 110 required anti-phase locks to postponing selector 120, reverse gate delay line 110 has three required anti-phase locks, with response signal 131.Postpone the output that selector 120 will receive anti-phase lock 110-3, and output is through the delayed sequence data 121 of optimization.In a word, the present invention is used for and will inserts default delay optimization at this signal path, it can determine the time delay in this reverse gate delay line received signal, and the influence of its temperature for indivedual anti-phase locks, supply voltage and manufacture process and insensitive.
By above explanation as can be known, it reaches purpose of the present invention fully and effectively.The purpose of the foregoing description is to illustrate function of the present invention and structural principle, and can and can not depart from this principle with this embodiment change.In a word,, should illustrate that obviously those skilled in the art can carry out various variations and remodeling though the present invention has enumerated above-mentioned preferred implementation.Therefore, unless such variation and remodeling have departed from scope of the present invention, otherwise all should be included within protection scope of the present invention.
Claims (16)
1, a kind of digital circuit comprises: a reverse gate delay line (110) and a delay regulating circuit is characterized in that:
Described reverse gate delay line (110) comprises a plurality of anti-phase locks that are connected in series that are used to receive a sequence data;
Described delay regulating circuit comprises that a delay selector (120), an encoder (130), a flip-flop array (140) and one duplicate reverse gate delay line (150); The described reverse gate delay line (150) that duplicates comprises a plurality of anti-phase locks that are connected in series, and these a plurality of anti-phase locks are used to receive first signal; Described flip-flop array (140) is made up of a plurality of flip-flops, any flip-flop is electrically connected to this corresponding anti-phase lock that duplicates reverse gate delay line (150), these a plurality of flip-flops are used to store binary message, and its first flip-flop receives the secondary signal that has time delay with respect to described first signal; Described encoder (130) is electrically connected to this a plurality of flip-flops, and it is according to the binary message that is stored in a plurality of flip-flops, in order to determine the number of the required anti-phase lock of this reverse gate delay line (110); Described delay selector (120) electrically connects a plurality of anti-phase lock of described encoder (130) and reverse gate delay line (110) respectively, it is caused the delay of this sequence data by the anti-phase lock of described reverse gate delay line (110), the number of the anti-phase lock of this reverse gate delay line (110) is that the output by encoder (130) decides.
2, according to the described digital circuit of claim 1, it is characterized in that: described a plurality of flip-flops are D-type flip-flops.
3, according to the described digital circuit of claim 1, it is characterized in that: the described a plurality of anti-phase lock that duplicates reverse gate delay line (150) is identical with a plurality of anti-phase lock of reverse gate delay line (110).
4, according to the described digital circuit of claim 2, it is characterized in that: the described a plurality of anti-phase lock that duplicates reverse gate delay line (150) is identical with a plurality of anti-phase lock of described reverse gate delay line (110).
5, according to the described digital circuit of claim 1, it is characterized in that: the time delay in described reverse gate delay line (110) the institute receiving sequence data is insensitive for the influence of temperature, supply voltage or manufacture process between indivedual anti-phase locks.
6, according to the described digital circuit of claim 4, it is characterized in that: the time delay in described reverse gate delay line (110) the institute receiving sequence data is insensitive for the influence of temperature, supply voltage or manufacture process between indivedual anti-phase locks.
7, according to the described digital circuit of claim 1, it is characterized in that: described first signal is to rise the edge signal and fall one of edge signal.
8, according to the described digital circuit of claim 1, it is characterized in that: described secondary signal is to rise the edge signal and fall one of edge signal.
9, a kind of method that is used for being provided at the digital circuit time delay may further comprise the steps in regular turn:
A reverse gate delay line (110) is provided, and it comprises a plurality of anti-phase locks that are connected in series that are used for the receiving sequence data;
Provide one to duplicate reverse gate delay line (150), it comprises a plurality of anti-phase locks that are connected in series, and these a plurality of anti-phase locks are designed to receive first signal;
A plurality of flip-flops are provided, wherein first flip-flop of these a plurality of flip-flops receives secondary signal, it has the time delay with respect to described first signal, and these a plurality of flip-flops are used to store the binary message that is produced by described first signal and secondary signal;
Decide the number of anti-phase lock required in the described reverse gate delay line (110) according to the binary message that in described a plurality of flip-flops, stores;
And the delay that causes described sequence data by the anti-phase lock of this reverse gate delay line (110), the number of the anti-phase lock of this reverse gate delay line (110) is that the output by described encoder (130) decides.
10, in accordance with the method for claim 9, it is characterized in that: described a plurality of flip-flops are D-type flip-flops.
11, in accordance with the method for claim 9, it is characterized in that: the described a plurality of anti-phase lock that duplicates reverse gate delay line (150) is identical with a plurality of anti-phase lock of described reverse gate delay line (110).
12, in accordance with the method for claim 11, it is characterized in that: the described a plurality of anti-phase lock that duplicates reverse gate delay line (150) is identical with a plurality of anti-phase lock of described reverse gate delay line (110).
13, in accordance with the method for claim 9, it is characterized in that: the time delay in described reverse gate delay line (110) the institute receiving sequence data is insensitive for the influence of temperature, supply voltage or manufacture process between indivedual anti-phase locks.
14, according to the described method of claim 12, it is characterized in that: the time delay in described reverse gate delay line (110) the institute receiving sequence data is insensitive for the influence of temperature, supply voltage or manufacture process between indivedual anti-phase locks.
15, in accordance with the method for claim 9, it is characterized in that: described first signal is to rise the edge signal and fall one of edge signal.
16, in accordance with the method for claim 9, it is characterized in that: described secondary signal is to rise the edge signal and fall one of edge signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200710089731 CN101051829A (en) | 2007-03-23 | 2007-03-23 | Reverse gate delay line with delay regulating circuit |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200710089731 CN101051829A (en) | 2007-03-23 | 2007-03-23 | Reverse gate delay line with delay regulating circuit |
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| CN101051829A true CN101051829A (en) | 2007-10-10 |
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| CN 200710089731 Pending CN101051829A (en) | 2007-03-23 | 2007-03-23 | Reverse gate delay line with delay regulating circuit |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102832943A (en) * | 2011-06-15 | 2012-12-19 | 联发科技（新加坡）私人有限公司 | Time-to-digital converter |
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2007
- 2007-03-23 CN CN 200710089731 patent/CN101051829A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102832943A (en) * | 2011-06-15 | 2012-12-19 | 联发科技（新加坡）私人有限公司 | Time-to-digital converter |
| CN102832943B (en) * | 2011-06-15 | 2015-06-03 | 联发科技（新加坡）私人有限公司 | Time-to-digital converter |
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