CN101051450A - Time sequence generating circuit and time sequence generating method for display device - Google Patents
Time sequence generating circuit and time sequence generating method for display device Download PDFInfo
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Abstract
The present invention provides a time sequence generation circuit of display unit and its time sequence generation method. It is used for a display unit with a horizontal drive circuit and a vertical drive circuit. The described horizontal drive circuit and vertical drive circuit respectively have a first horizontal displacement register and a first vertical displacement register. Said the sequence generation circuit includes a time sequence generation circuit includes a time sequence generator and a second horizontal displacement register or a second vertical displacement register. The invented time sequence generation method is characterized by that it utilizes second horizontal displacement register to produce a time sequence data and transfer said time sequence data to time sequence generator, according to said time sequence data said time sequence generator can produce a time sequence control signal to control horizontal drive circuit. Besides, it also can utilize second vertical displacement register to produce time sequence data; according to said time sequence data said time sequence generator can produce a time sequence control signal to control vertical drive circuit.
Description
Technical field
The invention relates to a kind of display device, refer to the sequential control circuit and the sequential production method of display device especially.
Background technology
Scientific and technological now flourish, the information product kind is weeded out the old and bring forth the new, and has satisfied popular different demand.Early stage display is cathode-ray tube (CRT) (Cathode Ray Tube mostly, CRT) display, because it is bulky big with power consumption, and the radiant rays that is produced is for the user of long-time use display, the doubt of harm health is arranged, therefore, display on the market gradually will be by LCD (Liquid Crystal Display, LCD) the old CRT monitor of replacement now.That LCD has is compact, low radiation and advantages such as power consumption is low, also so become the existing market main flow.
See also Fig. 1, it is the calcspar of prior art LCD.As shown in the figure, the prior art LCD comprises a sequential generator 10 ', a vertical drive circuit 20 ' and a horizontal drive circuit 30 '.Clock generator 10 ' reception vertical synchronizing signal Vsync, horizontal-drive signal Hsync and master clock signal MCK are as input signal, to produce two groups of control signals with control vertical drive circuit 20 ' and horizontal drive circuit 30 ', signal and data displaying picture that viewing area 45 ' is transmitted according to vertical drive circuit 20 ' and horizontal drive circuit 30 '.
Above-mentioned two groups of control signals are respectively a vertical input clock signal VST, a vertical movement clock signal VCK and a horizontal input clock signal HST, a horizontal displacement clock signal HCK.Vertical drive circuit 20 ' comprises shift register 22 ' and shift register 32 ' respectively with horizontal drive circuit 30 '.Vertical input clock signal VST produces according to vertical synchronizing signal Vsync, and inputs to the shift register 22 ' of vertical drive circuit 20 '.Shift register 22 ' produces a plurality of vertical selection clock signals successively according to vertical movement clock signal VCK, with control viewing area 45 ' display frame.The horizontal input clock signal HST of horizontal drive circuit 30 ' reception also produces sampling clock signal according to horizontal displacement clock signal HCK, for horizontal drive circuit 30 ' according to the sampling clock signal image data of taking a sample, for viewing area 45 ' display frame.
Moreover clock generator 10 ' comprises one first counter 12 ' and one second counter 14 ' in addition.First counter 12 ' is in order to the number of counting clock signal, and when the counting number arrived a threshold value, first counter 12 ' promptly can send a timing control signal to horizontal drive circuit 30 ', with controlling level driving circuit 30 '.For example, order about the sampled data that horizontal drive circuit 30 ' keeps sampling image data gained, convert the shows signal of a simulation to be sent to a digital analog converter (figure does not paint), and export viewing area 45 ' to.Equally, second counter 14 ' is in order to the number of counting clock signal, and when the counting number arrived a threshold value, second counter 14 ' promptly can control signal to vertical drive circuit 20 ' by transmission timing, with control vertical drive circuit 20 '.
But,,, so on circuit, need more hardware circuit and increase design complexities and area occupied and increase power consumption to produce timing control signal because above-mentioned method must usage counter.
Based on above-mentioned factor, the improvement project of correlation technique has as shown in Figure 1 been proposed now, announce patent of invention No. 535136 as TaiWan, China, its technology contents is roughly as follows.As shown in Figure 2, itself and Fig. 1 difference are that clock generator 10 ' need not be provided with counter, and can return a time series data (timing data) to clock generator 10 ' by vertical drive circuit 20 ' and horizontal drive circuit 30 ' original shift register 22 ' with shift register 32 ' respectively.Clock generator 10 ' produces timing control signal and is sent to vertical driver 20 ' and horizontal driver 30 ' according to time series data, with control vertical driver 20 ' and horizontal driver 30 '.So, clock generator 10 ' can produce timing control signal under the situation that counter need not be set.
But, when bilateral scanning, because many timing control signals must produce during blank (blanking), if calculate with typical 10% blank cycle, resolution for output is the display of 240 * 320 pixels, as shown in Figure 3A, just need the shift register 32 ' of horizontal drive circuit 30 ' add each about 28 grades of illusory (dummy) shift register 34 ' end to end, produce timing control signal to produce clock generator 10 ' the required time series data; The shift register 22 ' of vertical drive circuit 20 ' also is like this.
The shift register 22 ' that this kind mode will make vertical drive circuit 20 ' and horizontal drive circuit 30 ' and shift register 32 ' the shared length increases many, and exceeds display panel 40 ' length up and down, and increases power consumption.For the width size requirements increasingly stringent of display panel 40 ' frame-saw up and down, so design does not meet requirement now now.Moreover, shown in Fig. 3 B, if 28 grades of illusory shift registers 34 ' are arranged at other place of display panel 40 ' respectively, just the signal transmission is postponed, so easy generation problem, and can't carry out bilateral scanning smoothly, cause two-way switching difficulty.
Therefore, the present invention is directed to the problems referred to above and propose a kind of sequential control circuit and sequential control method of display device, not only can improve progression long, the complexity that increases design and the shortcoming that increases power consumption of vertical drive circuit and the original shift register of horizontal drive circuit, can solve the problem of the two-way switching difficulty when carrying out bilateral scanning again.
Summary of the invention
A purpose of the present invention is to provide a kind of sequential control circuit and sequential control method of display device, it is provided with shift register in addition by corresponding vertical drive circuit and horizontal drive circuit, long with the progression of avoiding vertical drive circuit and the original shift register of horizontal drive circuit, and increase the complexity that designs, and can carry out bilateral scanning smoothly.
Another object of the present invention is to provide a kind of sequential control circuit and sequential control method of display device, it is provided with shift register in addition by corresponding vertical drive circuit and horizontal drive circuit, and use low-frequency clock signal to produce time series data, to reach the purpose that reduces consumed power.
The sequential control circuit of display device of the present invention and sequential control method are used to have a display device of a horizontal drive circuit, and horizontal drive circuit has one first horizontal shifting register.Sequential control circuit of the present invention comprises a sequential generator and one second horizontal shifting register.Control method of the present invention is by clock generator, receive a horizontal-drive signal and a master clock signal, produce a horizontal input clock signal, one first horizontal displacement clock signal and one second horizontal displacement clock signal, horizontal input clock signal and first horizontal displacement clock news are sent to first horizontal shifting register, and produce a sampling clock signal, an image data is used to take a sample, with the viewing area of show image in display device, the horizontal input clock signal of transmission and second horizontal displacement clock news are sent to second horizontal shifting register in addition, and produce a time series data and be sent to clock generator, with according to this time series data, produce a timing control signal and be sent to horizontal drive circuit, with the controlling level driving circuit.
Moreover, the sequential control circuit of display device of the present invention also can be used for controlling a vertical drive circuit of display device, and vertical drive circuit has one first vertical transfer register, and this sequential control circuit that is used to control vertical drive circuit comprises clock generator equally and one second vertical transfer register is arranged.Sequential control method of the present invention is to receive a vertical synchronizing signal and master clock signal by clock generator, produces a vertical input clock signal, one first vertical movement clock signal and one second vertical movement clock signal; Afterwards, transmit the vertical input clock signal and first vertical movement clock signal to the first vertical transfer register, select clock signal, be used to control a viewing area of display device to produce plural number; In addition, transmit the vertical input clock signal and second vertical movement clock signal to the second vertical transfer register, to produce a time series data and to be sent to clock generator, clock generator is according to time series data, produce a timing control signal and transmit vertical drive circuit, with the control vertical drive circuit.
The sequential control circuit of display device of the present invention comprises clock generator and second horizontal shifting register and second vertical transfer register.Sequential control method of the present invention produces the horizontal input clock signal and the second horizontal displacement clock signal by clock generator.Second horizontal shifting register produces time series data and is sent to clock generator according to the horizontal input clock signal and the second horizontal displacement clock signal.Clock generator produces timing control signal and transmits horizontal drive circuit with the controlling level driving circuit according to time series data.Second vertical transfer register is equally according to the vertical input clock signal and the second vertical movement clock signal that clock generator produced, supply clock generator according to time series data and produce time series data, produce timing control signal and be sent to vertical drive circuit, with the control vertical drive circuit, so cpable of lowering power consumption, and can carry out bilateral scanning smoothly.
Description of drawings
Fig. 1 is the calcspar of prior art LCD;
Fig. 2 is the calcspar of another prior art LCD;
Fig. 3 A is arranged at the position view of display panel for the prior art shift register;
Fig. 3 B is arranged at the another location synoptic diagram of display panel for the prior art shift register;
Fig. 4 is the calcspar of a preferred embodiment of the present invention;
Fig. 5 is the sequential chart of the retiming clock signal of the present invention and prior art; And
Fig. 6 is the calcspar of another preferred embodiment of the present invention.
Drawing reference numeral:
1 display device, 10 ' clock generator
12 ' first counter, 14 ' second counter
20 ' vertical drive circuit, 22 ' shift register
30 ' horizontal drive circuit, 32 ' shift register
34 ' illusory shift register 40 display panels
45 viewing areas, 10 clock generators
20 horizontal drive circuits, 22 first horizontal shifting registers
24 second horizontal shifting registers, 26 breech lock modules
260 sampling latch circuits 262 keep latch circuit
28 digital analog converters, 30 vertical drive circuits
32 first vertical transfer registers, 34 second vertical transfer registers
45 viewing areas, 50 voltage conversion circuits
Embodiment
See also Fig. 4, it is the calcspar of a preferred embodiment of the present invention.Timing sequence generating device of the present invention is used for display device; As shown in the figure, display device 1 includes a sequential generator 10, a horizontal drive circuit 20, a vertical drive circuit 30, and all is arranged at a glass substrate (figure does not paint), is display panel (figure does not paint).Horizontal drive circuit 20 and vertical drive circuit 30 all couple a viewing area 45 of display panel.Clock generator 10 of the present invention receives vertical synchronizing signal Vsync, horizontal-drive signal Hsync and the master clock signal MCK that external device (ED) (for example computer system) is supplied with, to produce vertical input clock signal VST, the first vertical movement clock signal VCK1, the second vertical movement clock signal VCK2, horizontal input clock signal HST, the first horizontal displacement clock signal HCK1 and the second horizontal displacement clock signal HCK2.Clock generator 10 produces horizontal input clock signal HST according to horizontal-drive signal Hsync, and produces the first horizontal displacement clock signal HCK1 and the second horizontal displacement clock signal HCK2 according to master clock signal MCK.Clock generator 10 also produces vertical input clock signal VST according to vertical synchronizing signal Vsync, and produces the first vertical movement clock signal VCK1 and the second vertical movement clock signal VCK2 according to master clock signal MCK.
In addition, the frequency of the second horizontal displacement clock signal HCK2 can be less than or equal to the frequency of the first horizontal displacement clock signal HCK1.The frequency of the second vertical movement clock signal VCK2 also can be less than or equal to the frequency VCK1 of the first vertical movement clock.
The vertical drive circuit 30 of display device 1 has one first vertical transfer register 32.First vertical transfer register 32 receives the vertical input clock signal VST and the first vertical movement clock signal VCK1.First vertical transfer register 32 is as aforementioned first horizontal shifting register 22, be to postpone vertical input clock signal VST and produce a selection clock signal according to the first vertical movement clock signal VCK1, be used to select the vertical scan line (figure does not paint) of viewing area 45, promptly control the vertical scan line (figure does not paint) of viewing area 45.In addition, sequential control circuit of the present invention is provided with one second vertical transfer register 34 with respect to vertical drive circuit 30, it is according to the second vertical movement clock signal VCK2, postpone vertical input clock signal VST and produce a sequential clock signal, and transmit a time series data to clock generator 10 according to this sequential clock signal, clock generator 10 produces timing control signal and is sent to vertical drive circuit 30 according to time series data, with control vertical drive circuit 30.For example, when during a certain, carrying out the local repressentation pattern, can utilize timing control signal control vertical drive circuit 30 during this is a certain, to carry out the local repressentation pattern.
Because horizontal drive circuit 20 has multiple different designs mode with vertical drive circuit 30, have more than and be used for two kinds of above-mentioned situations so be used for the timing control signal of controlling level driving circuit 20 and vertical drive circuit 30, above-mentionedly be used for control and keep latch circuit 262 and carry out the local repressentation pattern and only be two embodiment of the present invention.Timing control signal of the present invention is required with the design of vertical drive circuit 30 and be used for different situations according to horizontal drive circuit 20, and the time series data of second horizontal shifting register 24 of the present invention and second vertical transfer register 34 clock generator that is back to 10 promptly returns pairing time series data according to the sequential of timing control signal, produces timing control signal for clock generator 10.
From the above, sequential control circuit of the present invention produces timing control signal by second horizontal shifting register 24 or second vertical transfer register 34, promptly do not need the prior art horizontal drive circuit or the illusory shift register passback time series data of vertical drive circuit shown in Fig. 3 A and Fig. 3 B, and produce timing control signal.So, first horizontal shifting register 24 of horizontal drive circuit 20 or vertical drive circuit 30 and the length of first vertical transfer register 34 will can not exceed the length up and down of display panel, the problem of signal transmission delay also can not take place, so can promote the demonstration usefulness of display.
See also Fig. 5, it is the sequential chart of the retiming clock signal of the present invention and prior art.Because prior art is the original shift register at horizontal drive circuit and vertical drive circuit illusory shift register is set more, the cycle of the retiming clock signal that illusory shift register like this produced is the clock signal that original shift register produced that is same as horizontal drive circuit and vertical drive circuit, so the progression of illusory shift register can be higher, and area occupied and increase power consumption.
As shown in Figure 5, if will produce the timing control signal of high levle in time T 1, the illusory shift register of prior art must have 20 grades at least, so that to clock generator 10, produce needed timing control signal according to time series data for clock generator 10 at 3rd level and the 19th grade passback time series data.Yet, the cycle of the retiming clock signal that shift register produced that the present invention sets up does not need the cycle of the clock signal that produced with original shift register the same, so the progression of the shift register that the present invention sets up under less than the situation of commonly using illusory shift register, just can produce required timing control signal.As shown in the figure, the shift register that the present invention sets up only needs 4 grades, can produce the timing control signal of high levle in time T 1.Because the frequency of the retiming clock signal that the present invention sets up is less than the frequency of the retiming clock signal of the illusory shift register of prior art, can produce timing control signal, so the progression of shift register can significantly lower and then reduce power, and can improve because of the long design area that influences display panel of the progression of shift register.
In addition, the timing control signal that sequential control circuit produced of display device 1 of the present invention is not limited to use at horizontal drive circuit 20 and vertical drive circuit 30, also can be used in other circuit.As shown in Figure 6, it is the calcspar of another preferred embodiment of the present invention.In the display panel of full integration (full integration), include a voltage conversion circuit 50 usually.Voltage conversion circuit 50 is coupled with a reference voltage, a common voltage and an interface (Interface, I/F), export higher positive voltage or negative voltage with a DC voltage changing outside input, for example a 3V voltage transitions is become 6V voltage and-3V voltage uses for other circuit.Yet other circuit that receives this voltage is not to move always, in order to save power, and can be with voltage conversion circuit 50 temporary closes during other circuit does not move.Second horizontal shifting register 24 of the present invention or second vertical transfer register 34 can provide clock signal to voltage conversion circuit 50 as timing control signal, and control voltage conversion circuit 50, and export timing control signal to horizontal drive circuit 20 after changing the timing control signal voltage quasi position, with controlling level driving circuit 20.In addition, also can provide time series data to clock generator 10, and correspondence produce timing control signal and is sent to voltage conversion circuit 50, with control voltage conversion circuit 50 by second horizontal shifting register 24 or second vertical transfer register 34.
In sum, the sequential control circuit of display device of the present invention comprises clock generator and second horizontal shifting register and second vertical transfer register.Sequential control method of the present invention produces the horizontal input clock signal and the second horizontal displacement clock signal by clock generator.Second horizontal shifting register produces time series data and is sent to clock generator according to the horizontal input clock signal and the second horizontal displacement clock signal.Clock generator produces timing control signal and transmits horizontal drive circuit with the controlling level driving circuit according to time series data.Second vertical transfer register is equally according to the vertical input clock signal and the second vertical movement clock signal that clock generator produced, supply clock generator according to time series data and produce time series data, produce timing control signal and be sent to vertical drive circuit, with the control vertical drive circuit, so cpable of lowering power consumption, and can carry out bilateral scanning smoothly.
The above is preferred embodiment of the present invention only, is not to be used for limiting the scope that the present invention is contained, and the equalization of doing according to shape of the present invention, structure and/or feature changes and modifies such as, all should be included in the claim of the present invention.
Claims (20)
1. timing sequence generating circuit, it is used for a display device, this display device has a vertical drive circuit and a horizontal drive circuit, this vertical drive circuit has one first vertical transfer register, this horizontal drive circuit has one first horizontal shifting register, it is characterized in that described timing sequence generating circuit comprises:
One sequential generator, receive a vertical synchronizing signal, one horizontal-drive signal and a master clock signal, produce a vertical input clock signal, one horizontal input clock signal, one first vertical movement clock signal, one first horizontal displacement clock signal, one second vertical movement clock signal and one second horizontal displacement clock signal, described first vertical transfer register produces plural clock signal and described first horizontal shifting register selected according to described vertical input clock signal and the described first vertical movement clock signal and produces plural number selection clock signal according to described horizontal input clock signal and the described first horizontal displacement clock signal, is used to control a viewing area of described display device;
One second vertical transfer register, according to described vertical input clock signal and the described second vertical movement clock signal, produce a time series data and be sent to described clock generator, this clock generator is according to described time series data, produce a timing control signal and be sent to described vertical drive circuit, to control this vertical drive circuit; And
One second horizontal shifting register, according to described horizontal input clock signal and the described second horizontal displacement clock signal, produce described time series data and be sent to described clock generator, this clock generator is according to this time series data, produce described timing control signal and be sent to described horizontal drive circuit, to control this horizontal drive circuit.
2. timing sequence generating circuit as claimed in claim 1, it is characterized in that, the frequency of the described second vertical movement clock signal is less than or equal to the frequency of the described first vertical movement clock signal, and the frequency of the described second horizontal displacement clock signal is less than or equal to the frequency of the described first horizontal displacement clock signal.
3. timing sequence generating circuit as claimed in claim 1, it is characterized in that, the progression of described second vertical transfer register is less than or equal to the progression of described first vertical transfer register, and the progression of described second horizontal shifting register is less than or equal to the progression of described first horizontal shifting register.
4. timing sequence generating circuit as claimed in claim 1, it is characterized in that described clock generator produces described vertical input clock signal according to described vertical synchronizing signal, and, produce described horizontal input clock signal according to described horizontal-drive signal.
5. timing sequence generating circuit as claimed in claim 1, it is characterized in that, described clock generator produces the described first vertical movement clock signal, the described first horizontal displacement clock signal, the described second vertical movement clock signal and the described second horizontal displacement clock signal according to described master clock signal.
6. the sequence generating method of a display device, it is used for a display device, this display device has a vertical drive circuit and a horizontal drive circuit, this vertical drive circuit has one first vertical transfer register, this horizontal drive circuit has one first horizontal shifting register, it is characterized in that described method comprises:
According to a vertical synchronizing signal, one horizontal-drive signal and a master clock signal produce a vertical input clock signal, a horizontal input clock signal, one first vertical/horizontal shift clock signal, one first horizontal displacement clock signal, one second vertical movement clock signal and one second horizontal displacement clock signal;
Transmit described vertical input clock signal and the described first vertical movement clock signal to described first vertical transfer register, and transmit described horizontal input clock signal and the described first horizontal displacement clock signal to described first horizontal shifting register, produce plural number and select clock signal, be used to control a viewing area of described display device;
Transmit described vertical/horizontal input clock signal and the described second vertical/horizontal shift clock signal to, the second vertical/horizontal shift register and transmit described horizontal input clock signal and the described second horizontal displacement clock signal to, second horizontal shifting register, produce a time series data respectively; And
According to described time series data, produce a timing control signal respectively and be sent to described vertical drive circuit and described horizontal drive circuit, to control this vertical drive circuit and this horizontal drive circuit.
7. sequence generating method as claimed in claim 6, it is characterized in that, the frequency of the described second vertical movement clock signal is less than or equal to the frequency of the described first vertical movement clock signal, and the frequency of the described second horizontal displacement clock signal is less than or equal to the frequency of the described first horizontal displacement clock signal.
8. sequence generating method as claimed in claim 6, it is characterized in that, the progression of described second vertical transfer register is less than or equal to the progression of described first vertical transfer register, and the progression of described second horizontal shifting register is less than or equal to the progression of described first horizontal shifting register.
9. sequence generating method as claimed in claim 6, it is characterized in that, produce the step of a vertical input clock signal and a horizontal input clock signal, be respectively according to described vertical synchronizing signal and horizontal-drive signal, produce described vertical input clock signal and described horizontal input clock signal.
10. sequence generating method as claimed in claim 6, it is characterized in that, produce the step of one first vertical movement clock signal, one first horizontal displacement clock signal, one second vertical movement clock signal and one second horizontal displacement clock signal, be according to described master clock signal, produce the described first vertical/horizontal shift clock signal, the described first horizontal displacement clock signal, the described second vertical movement clock signal and the described second horizontal displacement clock signal.
11. display device, it has a vertical drive, a horizontal drive apparatus and a timing sequence generating circuit, and this vertical drive circuit has a vertical transfer register, and this horizontal drive circuit has a horizontal shifting register, it is characterized in that described timing sequence generating circuit comprises:
One sequential generator, receive a vertical synchronizing signal, one horizontal-drive signal and a master clock signal, produce a vertical input clock signal, one horizontal input clock signal, one first vertical movement clock signal, one first horizontal displacement clock signal, one second vertical movement clock signal and one second horizontal displacement clock signal, described first vertical transfer register produces plural clock signal and described first horizontal shifting register selected according to described vertical input clock signal and the described first vertical movement clock signal and produces plural number selection clock signal according to described horizontal input clock signal and the described first horizontal displacement clock signal, is used to control a viewing area of described display device;
One second vertical transfer register, according to described vertical input clock signal and the described second vertical movement clock signal, produce a time series data and be sent to described clock generator, this clock generator is according to described time series data, produce a timing control signal and be sent to described vertical drive circuit, to control this vertical drive circuit; And
One second horizontal shifting register, according to described horizontal input clock signal and the described second horizontal displacement clock signal, produce described time series data and be sent to described clock generator, this clock generator is according to this time series data, produce described timing control signal and be sent to described horizontal drive circuit, to control this horizontal drive circuit.
12. display device as claimed in claim 11, it is characterized in that, the frequency of the described second vertical movement clock signal is less than or equal to the frequency of the described first vertical movement clock signal, and the frequency of the described second horizontal displacement clock signal is less than or equal to the frequency of the described first horizontal displacement clock signal.
13. display device as claimed in claim 11, it is characterized in that, the progression of described second vertical transfer register is less than or equal to the progression of described first vertical transfer register, and the progression of described second horizontal shifting register is less than or equal to the progression of described first horizontal shifting register.
14. display device as claimed in claim 11, it is characterized in that described clock generator produces described vertical input clock signal according to described vertical synchronizing signal, and, produce described horizontal input clock signal according to described horizontal-drive signal.
15. display device as claimed in claim 11, it is characterized in that, described clock generator produces the described first vertical movement clock signal, the described first horizontal displacement clock signal, the described second vertical movement clock signal and the described second horizontal displacement clock signal according to described master clock signal.
16. display packing, it is used for a display device, this display device has a vertical drive circuit and a horizontal drive circuit, this vertical drive circuit has one first vertical transfer register, this horizontal drive circuit has one first horizontal shifting register, it is characterized in that this display packing comprises:
According to a vertical synchronizing signal, one horizontal-drive signal and a master clock signal produce a vertical input clock signal, a horizontal input clock signal, one first vertical/horizontal shift clock signal, one first horizontal displacement clock signal, one second vertical movement clock signal and one second horizontal displacement clock signal;
Transmit described vertical input clock signal and the described first vertical movement clock signal to described first vertical transfer register, and transmit described horizontal input clock signal and the described first horizontal displacement clock signal to described first horizontal shifting register, produce plural number and select clock signal, be used to control a viewing area of described display device;
Transmit described vertical/horizontal input clock signal and the described second vertical/horizontal shift clock signal to, the second vertical/horizontal shift register and transmit described horizontal input clock signal and the described second horizontal displacement clock signal to, second horizontal shifting register, produce a time series data respectively; And
According to described time series data, produce a timing control signal respectively and be sent to described vertical drive circuit and described horizontal drive circuit, to control this vertical drive circuit and this horizontal drive circuit.
17. display packing as claimed in claim 16, it is characterized in that, the frequency of the described second vertical movement clock signal is less than or equal to the frequency of the described first vertical movement clock signal, and the frequency of the described second horizontal displacement clock signal is less than or equal to the frequency of the described first horizontal displacement clock signal.
18. display packing as claimed in claim 16, it is characterized in that, the progression of described second vertical transfer register is less than or equal to the progression of described first vertical transfer register, and the progression of described second horizontal shifting register is less than or equal to the progression of described first horizontal shifting register.
19. display packing as claimed in claim 16, it is characterized in that, produce the step of a vertical input clock signal and a horizontal input clock signal, be respectively according to described vertical synchronizing signal and horizontal-drive signal, produce described vertical input clock signal and described horizontal input clock signal.
20. display packing as claimed in claim 16, it is characterized in that, produce the step of one first vertical movement clock signal, one first horizontal displacement clock signal, one second vertical movement clock signal and one second horizontal displacement clock signal, be according to described master clock signal, produce the described first vertical/horizontal shift clock signal, the described first horizontal displacement clock signal, the described second vertical movement clock signal and the described second horizontal displacement clock signal.
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| CNB2007100958082A CN100561562C (en) | 2007-04-04 | 2007-04-04 | The timing sequence generating circuit of display device and sequential production method |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101868817B (en) * | 2007-11-20 | 2015-01-07 | 皇家飞利浦电子股份有限公司 | Power saving transmissive display |
| CN110767167A (en) * | 2018-10-31 | 2020-02-07 | 昆山国显光电有限公司 | Display screen and display terminal |
| CN113264262A (en) * | 2021-06-25 | 2021-08-17 | 京东方科技集团股份有限公司 | Tray and transportation device |
-
2007
- 2007-04-04 CN CNB2007100958082A patent/CN100561562C/en active Active
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101868817B (en) * | 2007-11-20 | 2015-01-07 | 皇家飞利浦电子股份有限公司 | Power saving transmissive display |
| CN110767167A (en) * | 2018-10-31 | 2020-02-07 | 昆山国显光电有限公司 | Display screen and display terminal |
| CN113264262A (en) * | 2021-06-25 | 2021-08-17 | 京东方科技集团股份有限公司 | Tray and transportation device |
| CN113264262B (en) * | 2021-06-25 | 2023-02-17 | 京东方科技集团股份有限公司 | Tray and transportation device |
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| CN100561562C (en) | 2009-11-18 |
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