CN101051228A

CN101051228A - Converter real time controller

Info

Publication number: CN101051228A
Application number: CN 200710034920
Authority: CN
Inventors: 倪大成; 刘可安
Original assignee: Zhuzhou CSR Times Electric Co Ltd
Current assignee: Zhuzhou CRRC Times Electric Co Ltd
Priority date: 2007-05-14
Filing date: 2007-05-14
Publication date: 2007-10-10
Anticipated expiration: 2027-05-14
Also published as: CN100461046C

Abstract

A real time controller of inverter is prepared for connecting fixed-point CPU, the first floating-point CPU, the second floating-point CPU, power supply unit and clock generating unit separately to programmable logic unit, carrying out access and dispatch on the first and the second floating-point CUP by fixed-point CPU through master-slave mode special high speed parallel host port bus, providing data isolation and data driving for access of fixed-point CPU to two floating-point CPU by buffer unit in order to set data buffer unit for writing and reading necessary data in two said floating-point CPU.

Description

Converter real time controller

Technical field

The present invention is mainly concerned with the control field of current transformer, refers in particular to a kind of converter real time controller.

Background technology

The traction convertor real-time controller is one of most critical link of current transformer control, is determining the quality of current transformer output, and the stability and the reliability of current transformer control.Now, in the real-time controller field various scheme is arranged both at home and abroad, therefore, real-time controller also just has different hardware structures accordingly.At present, external all is the framework that adopts many floating-points CPU+FPGA usually, though the controller of this framework has dropped into commercial utilization, and entered the volume production stage, but it is too tediously long on the construction cycle, need write a large amount of logic control software according to the controller requirement, thereby bring huge human cost expense.In addition, in different control occasions, it is cumbersome that system carries out the cutting change.Referring to shown in Figure 4, what the inverter controller of domestic present main flow adopted is the framework of single knuckle CPU+2 fixed point CPU, this systematic comparison is stable, reliable, but, what the mode of swap data adopted between the CPU is the mode of the asynchronous swap data of twoport storage unit access (hereinafter to be referred as dual port RAM), therefore, it is longer to delay time on data transmission, makes whole computation period also long; In addition, use dual port RAM to conduct interviews, the probability of exchanges data conflict is higher, therefore, sums up application experience for a long time, and we think, develop a kind of new real-time controller framework, and the problem of improving and replenishing above-mentioned control architecture is very necessary.

Summary of the invention

The technical problem to be solved in the present invention just is: at the technical matters of prior art existence, the present invention propose a kind of simple in structure, do not have the conflict swap data by high-speed real-time, finish the converter real time controller of the purpose in final shortening core calculations cycle.

For solving the problems of the technologies described above, the solution that the present invention proposes is: a kind of converter real time controller, it is characterized in that: it comprises FPGA (Field Programmable Gate Array) control module and the fixed point CPU that links to each other with the FPGA (Field Programmable Gate Array) control module respectively, the first floating-point CPU, the second floating-point CPU, buffer cell, power conversion unit and clock generation unit, fixed point CPU, the first floating-point CPU links to each other with programmable logic cells respectively with the second floating-point CPU, fixed point CPU conducts interviews to the first floating-point CPU and the second floating-point CPU by the parallel main frame mouth bus of master-slave mode specialized high-speed, scheduling, buffer cell provides data isolation and data-driven for fixed point CPU to the visit between the first floating-point CPU and the second floating-point CPU, and being used for is to be provided with the data buffer unit that is used for reading or writing necessary data in the first floating-point CPU and the second floating-point CPU.

The described first floating-point CPU or the second floating-point CPU link to each other with the pulse latch units by outside expansion bus XD, are used for externally exporting or latching the first floating-point CPU or the gating pulse of the second floating-point CPU by calculating.

The described first floating-point CPU or the second floating-point CPU link to each other with AD conversion unit by outside expansion bus XD, are used for importing current transformer through the feedback sample after controlling.

Compared with prior art, advantage of the present invention just is:

1, simple in structure, be easy to system trimming; Above-mentioned fixed point+two Floating-point DSP structures can be configured as fixed point+two Floating-point DSP or fixed point+many Floating-point DSP structure according to system's computing needs.

2, the speed of data processing and exchange is very fast, and is real-time; DSP adopts high performance computation kernel and parallel 32 bus structure, has eliminated the bottleneck of data processing in the real-time control.

3, versatility is stronger, is easy to system upgrade and regenerates; Be equipped with signal sampling and pulse generation general in the Industry Control in the real-time controller and latched passage, can adapt to the control requirement of multiple occasion, the bus interface that carries of controller can be applied in the various control system easily in addition.

4, be easy to software programming, and make things convenient for the transplanting of software; What the embedded software of controller all adopted is that the popular c program in control field is write.

5, cost is lower, is fit to use in batches.Controller adopts the comparatively popular and low DSP of cost of industry as core CPU, has effectively reduced system cost and buying difficulty.

Description of drawings

Fig. 1 is a framed structure synoptic diagram of the present invention;

Fig. 2 is a principle schematic of the present invention;

Fig. 3 is the circuit theory synoptic diagram of the embodiment of the invention;

Fig. 4 is the framed structure synoptic diagram of prior art middle controller.

Marginal data:

1, fixed point CPU 2, the first floating-point CPU

3, the second floating-point CPU 4, pulse buffer unit

5, AD conversion unit 6, power conversion unit

7, clock generation unit 8, buffer cell

9, data buffer unit

Embodiment

Below with reference to the drawings and specific embodiments the present invention is described in further details.

Referring to Fig. 1, Fig. 2 and shown in Figure 3, converter real time controller of the present invention, it comprises FPGA (Field Programmable Gate Array) control module 9 and the fixed point CPU1 that links to each other with FPGA (Field Programmable Gate Array) control module 9 respectively, the first floating-point CPU2, the second floating-point CPU3, buffer cell 8, power conversion unit 6 and clock generation unit 7, fixed point CPU1, the first floating-point CPU2 links to each other with programmable logic cells 9 respectively with the second floating-point CPU3, and fixed point CPU1 conducts interviews to the first floating-point CPU2 and the second floating-point CPU3 by the parallel main frame mouth bus (hereinafter to be referred as HPI) of master-slave mode specialized high-speed, scheduling.The HPI bus is to conduct interviews by the DMA of the first floating-point CPU2 and the second floating-point CPU3 inside (direct memory access) mode, the many access conflicts that conduct interviews by dual port RAM in the scheme have in the past been avoided, can improve the dispatching efficiency of fixed point CPU1 greatly, also can accelerate the computing velocity of the first floating-point CPU2 and the second floating-point CPU3 core algorithm greatly.Exchanges data to the first floating-point CPU2 and the second floating-point CPU3 manages, the first floating-point CPU2 and the second floating-point CPU3 are then as long as hew out data buffer unit 9 in internal storage unit, data necessary is read or write from data buffer unit 9, this process is all carried out under the high-speed parallel state, computation period influence for the first floating-point CPU2 and the second floating-point CPU3 is very little, exchange between data in the data buffer unit 9 and the fixed point CPU1 is then finished on the backstage by DMA (direct memory visit) mode, in this way, promptly realized management with fixed point CPU1 and calculating with the high-speed data exchange between the first floating-point CPU2 and the second floating-point CPU3, therefore, this framework is very suitable for controlling in real time occasion.Buffer cell 8 provides data isolation and data-driven for fixed point CPU1 to the visit between the first floating-point CPU2 and the second floating-point CPU3.In the present embodiment, the first floating-point CPU2 or the second floating-point CPU3 link to each other with pulse latch units 4 by outside expansion bus XD, are used for externally exporting or latching the first floating-point CPU2 or the gating pulse of the second floating-point CPU3 by calculating.The first floating-point CPU2 or the second floating-point CPU3 link to each other with AD conversion unit 5 by outside expansion bus XD, are used for importing current transformer through the feedback sample after controlling.The CPU1 that wherein fixes a point is wanting resource abundanter aspect the configuration of peripheral hardware, has both stronger calculation process ability simultaneously; The first floating-point CPU2 and second floating-point CPU3 arithmetic capability aspect model calculation are quite strong; And FPGA (Field Programmable Gate Array) control module 9 (CPLD) is relative simple to the management of bus and logic, uses fixed point CPU1 down two floating-point CPU to be managed and dispatch the auxiliary of CPLD.The first floating-point CPU2 or the second floating-point CPU3 externally export and latch (before upgrading, keeping previous pulse) by the gating pulse that calculates next time always by pulse latch units 4.The feedback of current transformer load is by after the sensor, and the AD conversion unit 5 of process real-time controller inside has been finished the feedback sample to controlled variable, thereby reaches the purpose of closed-loop control.After power conversion unit 6 is imported by external power source, the power supply of the inner needed various grades of the controlled device of conversion, as 1.2v, 1.8v etc.Clock generation unit 7 as required, provides clock according to the parameter that pre-sets for each CPU.

Principle of work: after system powered on, power conversion unit 6, was successively started and the corresponding power supply that needs in the plate is provided according to pre-set order by several DC/DC transducers.Each CPU that clock generation unit 7 is respectively in the controller provides clock signal.Fixed point CPU1 finishes the initialization of oneself getting electric back according to the clock that clock generation unit 7 provides.Its RDY, CTL and address wire are connected with CPLD respectively, by CPLD its steering logic are carried out sequential control and address decoder, finish the visit to the outside.The working condition of the first floating-point CPU2 and the second floating-point CPU3 is similar with fixed point CPU1, the associated control signal of its HPI port separately is connected with CPLD, finishes fixed point CPU1 visits the passage sequential of the first floating-point CPU2 and the second floating-point CPU3 by HPI foundation.Fixed point CPU1 is by its outside expansion bus MD[0:15] through the HPI bus HD[0:15 of buffer cell and the first floating-point CPU2 and the second floating-point CPU3] connect data channel foundation.The first floating-point CPU2 or the second floating-point CPU3 are by himself outside expansion bus XD[0:15] connect with pulse latch units 4, under the control of CPLD, press some cycles, latch the pulse that to export, the pulse output amplitude of pulse latch units 4 is 0～5V, frequency and dutycycle determine that by software design personnel oneself the pulse passage number is 8 the tunnel.The first floating-point CPU2 or the second floating-point CPU3 are by self outside expansion bus XD[0:15] read the data of AD conversion unit 5, the input of AD conversion unit 5 totally eight tunnel, input range ± 10V.

Claims

1, a kind of converter real time controller, it is characterized in that: it comprises FPGA (Field Programmable Gate Array) control module (9) and the fixed point CPU (1) that links to each other with FPGA (Field Programmable Gate Array) control module (9) respectively, the first floating-point CPU (2), the second floating-point CPU (3), buffer cell (8), power conversion unit (6) and clock generation unit (7), fixed point CPU (1), the first floating-point CPU (2) links to each other with programmable logic cells (9) respectively with the second floating-point CPU (3), fixed point CPU (1) conducts interviews to the first floating-point CPU (2) and the second floating-point CPU (3) by the parallel main frame mouth bus of master-slave mode specialized high-speed, scheduling, buffer cell (8) provides data isolation and data-driven for fixed point CPU (1) to the visit between the first floating-point CPU (2) and the second floating-point CPU (3), and being used for is to be provided with the data buffer unit (9) that is used for reading or writing necessary data in the first floating-point CPU (2) and the second floating-point CPU (3).

2, converter real time controller according to claim 1, it is characterized in that: the described first floating-point CPU (2) or the second floating-point CPU (3) link to each other with pulse latch units (4) by outside expansion bus XD, are used for externally exporting or latching the first floating-point CPU (2) or the gating pulse of the second floating-point CPU (3) by calculating.

3, converter real time controller according to claim 1 and 2, it is characterized in that: the described first floating-point CPU (2) or the second floating-point CPU (3) link to each other with AD conversion unit (5) by outside expansion bus XD, are used for importing current transformer through the feedback sample after controlling.