CN101043576A - Image processing apparatus for improving image quality using accumulator and correlation method thereof - Google Patents
Image processing apparatus for improving image quality using accumulator and correlation method thereof Download PDFInfo
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- CN101043576A CN101043576A CN 200610068204 CN200610068204A CN101043576A CN 101043576 A CN101043576 A CN 101043576A CN 200610068204 CN200610068204 CN 200610068204 CN 200610068204 A CN200610068204 A CN 200610068204A CN 101043576 A CN101043576 A CN 101043576A
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Abstract
The related image processor comprises: a carry-save accumulator with a first input port for receiving the signal and an second input port, a first buffer with an input port coupled with the accumulator and an output port coupled with last second input port, a carry-transfer adder coupled with last buffer, and a CPU with an input port coupled with the adder and an output port to generate output signal.
Description
Technical field
The present invention relates to a kind of image processing apparatus and correlation technique thereof that promotes image quality, particularly a kind of image processing apparatus and correlation technique thereof that utilizes the carry reserve accumulator to promote image quality.
Background technology
For digital camera, digital camera or LCD, for the vividness that increases color and the stability of image, we need add up the metrical information of original image, with as the foundation of adjusting.The information that these metrical informations can count whole pictures is the more the better, but if will add up the information of whole pictures, then meets just before the not enough problem of clock speed.The settling mode of prior art is, an image division is become a plurality of circles, only calculates the characteristic value of this circle, go to calculate another circle again next time, this image for static state is effective, but for dynamic digital camera or LCD, then must seek new settling mode.
The operation principle of CRT and LCD display all is to produce a complete picture control by horizontal-drive signal and vertical synchronizing signal, the external world can be in due course between point produce picture signal, can on screen, produce image.In an image, each picture frame is all drawn by the scan line of electron gun, it is essential return after electron gun is scanning a scan line, therefore in image processing apparatus, must comprise the signal of telling electron gun to return to speed, this signal be horizontal-drive signal (Horizontal SynchronizationSignal, Hsync); Similarly, scanning after a figure, image processing apparatus can send a vertical synchronizing signal, and (Vertical Synchronization Signal Vsync) makes electron gun do the action of vertical retrace.
Please refer to Fig. 1.Fig. 1 is the schematic diagram that prior art one image processing apparatus is handled metrical information.When electron gun when having scanned a scan line, this image processing apparatus can send a horizontal-drive signal Hsync (Hsync is a low level), scanning after a figure, this image processing apparatus can send a vertical synchronizing signal Vsync (Vsync is a low level).Clock CLK is to be the signal of T one-period, in the time of a scan line of scanning (Hsync is a high level), this image processing apparatus can carry out a carry in each period T and transmit addition (Carry-pass Adding, CPA), promptly metrical information is carried out complete add operation, comprise generation one summation (Sum) and carry output (Carry Out).In next cycle T, this image processing apparatus can carry out once complete carry again and transmit add operation.
Please refer to Fig. 2.Fig. 2 is the schematic diagram of a carry-propagation adder 22.Carry-propagation adder 22 comprises three inputs, and first input end 222 is to be used for receiving a summand A
1 Second input 224 is the summation input Sin that are used for importing previous stage, the 3rd input 226 is the carry input Cin that are used for importing previous stage, carry-propagation adder 22 comprises two outputs, first output 228 is to be used for exporting summation output Sout, and second output 229 is to be used for exporting carry output Cout.Carry-propagation adder 22 is to be used for the numerical value that three inputs are imported is carried out add operation, and the logical operation of summation output Sout is Sout=A
1Λ Sin Λ Cin promptly carries out anti-or logical operation to three input values.The logical operation of carry output Cout is Cout=A
1Sin|A
1Cin|SinCin carries out three input values and logical operation earlier in twos, carries out once more at last or logical operation.
Because this image processing apparatus must carry out once complete add operation in each period T in the prior art, promptly metrical information is carried out the addition of carry, need the expensive time, with present clock speed, therefore the metrical information that can handle must become a plurality of circles with an image division very little, is the add operation that unit carries out metrical information respectively with a plurality of circles, respectively those circles are done the image adjustment, but this kind way can cause the bad of image.If produce the image quality better image, then must be with whole the carry addition that carries out metrical information that image is complete, but not become a plurality of circles to go to calculate and carry out the image adjustment respectively image division, though so can obtain the better image quality but relative essential the use longer operation time, therefore how to promote calculation process speed and in the limited time, handle more operand, promptly become an important topic that promotes image quality.
Summary of the invention
The present invention provides a kind of image processing apparatus that utilizes the carry reserve accumulator to promote image quality, and this image processing apparatus comprises an adjuster, a carry reserve accumulator, one first buffer, a carry-propagation adder and a central processing unit.Adjuster comprises a first input end, be used for receiving a batch total amount information, one second input, be coupled to the output of central processing unit, be used for receiving output signal, and an output, be coupled to the first input end of carry reserve accumulator, adjuster is handled according to output signal and this batch total amount information, produces a processing signals.The carry reserve accumulator comprises a first input end, be coupled to regulator output, in order to receive this processing signals, and one second input, be used for receiving the result who once exports before the carry reserve accumulator, the carry reserve accumulator is to be used for the information and executing carry of two inputs is kept addition.First buffer comprises an input, is coupled to the carry reserve accumulator, and an output, is coupled to second input of carry reserve accumulator.Carry-propagation adder is coupled to first buffer, is used for all carries of first buffer output are carried out add operation.Central processing unit comprises an input, is coupled to carry-propagation adder, and an output, is coupled to second input of adjuster, is used for handling calculating metrical information later, produces this output signal.
The invention provides a kind of image processing apparatus that utilizes the carry reserve accumulator to promote image quality, this image processing apparatus comprises delayer, a carry reserve accumulator, one first buffer, a carry-propagation adder, a multiplexer, a controller and a central processing unit of an A/D converter, a plurality of series connection.A/D converter is that the data transaction that is used for receiving becomes numerical data.The delayer of a plurality of series connection is coupled to A/D converter, and each delayer is to be used for delaying a predetermined clock cycle.Multiplexer is to be coupled to a plurality of delayers and central processing unit, multiplexer has a control end, and multiplexer is that an output signal that is used for receiving according to control end produces the sampled signal that the numerical data of A/D converter output is taken a sample.Controller is coupled to A/D converter, multiplexer and carry reserve accumulator, and controller is taken a sample to digital data according to sampled signal, to produce a processing signals.The carry reserve accumulator comprises a first input end and is coupled to controller, in order to the reception processing signals, and one second input, be used for receiving the result who once exports before the carry reserve accumulator.First buffer comprises an input and is coupled to the carry reserve accumulator, and an output, is coupled to second input of carry reserve accumulator.Carry-propagation adder is coupled to first buffer, is used for all carries of first buffer output are carried out add operation.Central processing unit comprises an input, is coupled to carry-propagation adder, and an output, is coupled to the control end of multiplexer, is used for handling calculating metrical information later, produces this output signal.
The invention provides a kind of carry of utilizing and keep the method that summation promotes image quality, this method was included in the predetermined clock cycle carries out the computing of a carry reservation summation to the metrical information of a pixel; And when vertical synchronizing signal is effective, will carries out the carry of carry reservation add operation generation and carry out a carry transmission add operation.
Description of drawings
Fig. 1 is the schematic diagram that prior art one image processing apparatus is handled metrical information.
Fig. 2 is the schematic diagram of a carry-propagation adder.
Fig. 3 handles the schematic diagram of metrical information for the present invention's one image processing apparatus.
Fig. 4 uses the schematic diagram of the circuit of a carry reserve accumulator for the present invention.
Fig. 5 is the schematic diagram of a carry reserve accumulator.
Fig. 6 is the schematic diagram of the present invention's one image processing apparatus.
Fig. 7 is the schematic diagram of another image processing apparatus of the present invention.
The reference numeral explanation
The parallel synchronizing signal of Vsync vertical synchronizing signal Hsync
CLK, CLK
1Clock T, T
1Cycle
The input of Sin summation input Cin carry
Sout, the output of SUM summation output Cout carry
226,426 the 3rd input A
1, A
iSummand
228,428,446 first outputs
229,429,448 second outputs
40 circuit, 44 D flip-flops
48 shift units
The FA full adder
U
0～(n-1), V
0～(n-1), W
0～(n-1)Input value
S
0～S
N-1Summation output
C
0～C
N-1Carry output
60,70 image processing apparatus, 62 adjusters
42,64,50 carry reserve accumulators, 66 first buffers
22,46,68 carry-propagation adders, 67 second buffers
69 central processing units
222,422,442,462,622,642 first input ends
224,424,444,464,624,644 second inputs
662,682,672,692,482 inputs
626,646,664,684,674,694,484,764 outputs
72 A/D converter DL
1～DL
nDelayer
74 multiplexers, 744 control ends
76 controllers
Embodiment
Please refer to Fig. 3.Fig. 3 handles the schematic diagram of metrical information for the present invention's one image processing apparatus.When electron gun when having scanned a scan line, this image processing apparatus can send a horizontal-drive signal Hsync (Hsync is a low level), scanning after a figure, this image processing apparatus can send a vertical synchronizing signal Vsync (Vsync is a low level).Clock CLK
1Be to be T one-period
1Signal, scanning a scan line time in (Hsync is a high level), this image processing apparatus can be in each period T
1(Carry-save Adding CSA), produces the output of a summation and a carry, at next cycle T to carry out a carry reservation addition
1The time, this image processing apparatus can carry out a carry again and keep addition, but the carry input addition of previous stage when vertical synchronizing signal Vsync is low level, just can not done once complete add operation with the carry output of each grade generation.As shown in Figure 3, utilizing the carry that can allow the carry time of CPA in the general prior art the present invention use to keep addition calculates in the period at this section and compared in the past more metrical information, therefore employed method is compared in image processing apparatus of the present invention and the prior art, in the identical time, image processing apparatus of the present invention can be handled more metrical information.
Please refer to Fig. 4.Fig. 4 uses the schematic diagram of the circuit 40 of a carry reserve accumulator for the present invention.Circuit 40 comprises a carry reserve accumulator 42, a D flip-flop 44, a carry-propagation adder 46 and a shift unit 48.Carry reserve accumulator 42 comprises three inputs, and first input end 422 is to be used for receiving a summand A
iSecond input 424 is second outputs 448 that are coupled to D flip-flop 44, the 3rd input 426 is first outputs 446 that are coupled to D flip-flop 44, carry reserve accumulator 42 comprises two outputs, first output 428 is to be used for producing summation output S, and second output 429 is to be used for producing carry output C.The input 482 of shift unit 48 is second outputs 429 that are coupled to carry reserve accumulator 42, and shift unit 48 is exported C with carry and be multiply by twice, that is mends one 0 position in the back of carry output C.The first input end 442 of D flip-flop 44 is first outputs 428 that are coupled to carry reserve accumulator 42, and second input 444 of D flip-flop 44 is the outputs 484 that are coupled to shift unit 48, clock CLK
1For one-period is T
1Signal, every through one-period T
1, D flip-flop 44 just can be delivered to output with the result.Carry-propagation adder 46 comprises two inputs, first input end 462 is first outputs 446 that are coupled to D flip-flop 44, second input 464 is second outputs 448 that are coupled to D flip-flop 44, carry-propagation adder 46 is to be used for numerical value addition that two inputs are received, and produces summation output SUM.
Please refer to Fig. 5.Fig. 5 is the schematic diagram of a carry reserve accumulator 50.Carry reserve accumulator 50 is adders of n position, and it comprises n full adder FA, and each full adder FA comprises three inputs, is used for receiving U respectively
i, V
i, W
i, each full adder FA carries out add operation to the numerical value that three inputs are imported, summation output S
0～S
N-1Logical operation be S
i=U
iΛ V
iΛ W
i, promptly three input values are carried out anti-or logical operation; Carry output C
0～C
N-1Logical operation be C
i=U
iV
i| V
iW
i| U
iW
i, earlier three input values are carried out and logical operation in twos, carry out once more at last or logical operation, wherein, i=0～(n-1).
Please refer to Fig. 6.Fig. 6 is the schematic diagram of the present invention's one image processing apparatus 60.Image processing apparatus 60 comprises an adjuster 62, a carry reserve accumulator 64, one first buffer 66, a carry-propagation adder 68, one second buffer 67 and a central processing unit 69.Adjuster 62 comprises a first input end 622 and is used for receiving one group of image metrical information, and one second input 624, be coupled to the output 694 of central processing unit 69, be used for receiving an output signal, adjuster is handled according to this output signal and this batch total amount information, produces a processing signals.Carry reserve accumulator 64 comprises a first input end 642, be coupled to the output 626 of adjuster 62, in order to receive this processing signals, and one second input 644, be used for receiving the result who once exports before the carry reserve accumulator 64, carry reserve accumulator 64 is to be used for the information and executing carry of two inputs 642,644 is kept addition.First buffer 66 comprises an input 662 and an output 664, and input 662 is the outputs 646 that are coupled to carry reserve accumulator 64, and output 664 is second inputs 644 that are coupled to carry reserve accumulator 64.The input 682 of carry-propagation adder 68 is the outputs 664 that are coupled to first buffer 66, is used for all carries of first buffer, 66 outputs are carried out add operation.Every through a clock CLK
1Period T
1The time, first buffer 66 just can carry out an add operation, and the result is exported by output 664.Second buffer 67 comprises a first input end 672 and an output 674, and first input end 672 is the outputs 684 that are coupled to carry-propagation adder 68, and output 674 is the inputs 692 that are coupled to central processing unit 69.When vertical synchronizing signal Vsync was low level, second buffer 67 just can export the result to output 674.Central processing unit 69 comprises an input 692 and an output 694, input 692 is the outputs 674 that are coupled to second buffer 67, output 694 is second inputs 624 that are coupled to adjuster 62, is used for handling calculating metrical information later, produces this output signal.Wherein, image processing apparatus 60 is digital camera or digital camera.For digital camera or digital camera, the image metrical information that strengthens quality can comprise Automatic white balance, focusing and the required information such as chrominance information, gradient information and monochrome information of automatic exposure automatically carried out.
Please refer to Fig. 7.Fig. 7 is the schematic diagram of another image processing apparatus 70 of the present invention.Image processing apparatus 70 comprises the delayer DL of an A/D converter 72, a plurality of series connection
1-DL
n, a carry reserve accumulator 64, one first buffer 66, a carry-propagation adder 68, second buffer 67, a multiplexer 74, a controller 76 and a central processing unit 69.A/D converter 72 is that the analog input signal that is used for receiving converts numerical data to.The delayer DL of these a plurality of series connection
1-DL
nBe coupled to A/D converter 72, each delayer is to be used for delaying a predetermined clock cycle.For example, when always having the delayer of 15 series connection, this predetermined clock cycle that then each delayer postponed is 1/16 clock cycle, therefore control the number of the delayer number of series connection, each delayer of may command is the predetermined clock cycle that is used for delaying, can further carry out phase delay to the clock cycle by those delayers again, this kind phase delay technology does not repeat them here by general known.
Multiplexer 74 is to be coupled to this a plurality of delayer DL
1-DL
nAnd central processing unit 69, multiplexer 74 has a control end 744, and multiplexer 74 is to be used for producing the sampled signal that the numerical data of A/D converter 72 outputs is taken a sample according to the output signal that control end 744 is received.Controller 76 is to be coupled to A/D converter 72, multiplexer 74 and carry reserve accumulator 64, and controller 76 is taken a sample to digital data according to sampled signal, to produce processing signals.Controller 100 is coupled to A/D converter 72, multiplexer 74 and carry reserve accumulator 64, and controller 100 is taken a sample to digital data according to sampled signal, to produce processing signals.Carry reserve accumulator 64 comprises a first input end 642, be coupled to the output 764 of this controller 76, in order to receive this processing signals, and one second input 644, be used for receiving the result who once exports before the carry reserve accumulator 64, carry reserve accumulator 64 is to be used for the information and executing carry of two inputs 642,644 is kept addition.First buffer 66, carry-propagation adder 68 and second buffer 67 are identical with first buffer 66, carry-propagation adder 68 and second buffer 67 that Fig. 6 is mentioned.Central processing unit 69 comprises an input 692 and an output 694, is respectively coupled to the output 674 of second buffer 67 and the control end 744 of multiplexer 74, is used for handling calculating metrical information later, produces this output signal.Wherein, image processing apparatus 70 is liquid crystal indicators.For liquid crystal indicator, metrical information can comprise gradient information, adjusts image by the gradient information of calculating pixel and pixel, can make the image of liquid crystal indicator output have the better image quality.
Above-described embodiment only is used for illustrating the present invention, does not limit to category of the present invention.The image processing apparatus of being mentioned in the literary composition 60,70 is not limited to digital camera, digital camera or liquid crystal indicator, can also be other image device.Can promote the speed of calculating metrical information by the present invention, the image metrical information that wherein strengthens quality is not limited to carries out Automatic white balance, focusing and the required information such as chrominance information, gradient information and monochrome information of automatic exposure automatically, and any other metrical information all belongs to category of the present invention.
As from the foregoing, the invention provides a kind of method of utilizing the carry reserve accumulator to promote image quality, in cycle the metrical information of a pixel is carried out a carry in a predetermined clock and keep add operation, and then when vertical synchronizing signal is effective, will carries out the carry of carry reservation add operation generation and carry out a carry transmission add operation.Thus, the present invention is by the time of saving carry, can handle the continuous data of tens of times even hundreds of times, does a great deal of good greatly for the lifting of image quality.
The above only is preferred embodiment of the present invention, and all equalizations of being done according to the present patent application claim change and modify, and all should belong to covering scope of the present invention.
Claims (12)
1. image processing apparatus that utilizes the carry reserve accumulator to promote image quality includes:
One carry reserve accumulator, it comprises a first input end, in order to receiving a processing signals, and one second input, be used for receiving the result who once exports before this carry reserve accumulator, this carry reserve accumulator is to be used for the information and executing carry of two inputs is kept addition;
One first buffer, it comprises an input, is coupled to this carry reserve accumulator, and an output, is coupled to this second input of this carry reserve accumulator;
One carry-propagation adder is coupled to this first buffer, is used for all carries of this first buffer output are carried out add operation; And
One central processing unit, it comprises an input, is coupled to this carry-propagation adder, and an output, is used for handling calculating metrical information later, to produce an output signal.
2. image processing apparatus as claimed in claim 1, it comprises in addition:
One adjuster, this adjuster comprises a first input end, be used for receiving a batch total amount information, one second input is coupled to the output of this central processing unit, is used for receiving this output signal, an and output, be coupled to the first input end of this carry reserve accumulator, this adjuster is handled according to this output signal and this batch total amount information, produces this processing signals.
3. image processing apparatus as claimed in claim 2, it is a digital camera.
4. image processing apparatus as claimed in claim 2, it is a digital camera.
5. image processing apparatus as claimed in claim 1, it comprises one second buffer in addition, and this second buffer comprises a first input end, is coupled to this carry-propagation adder, and an output, is coupled to this central processing unit.
6. image processing apparatus as claimed in claim 1, wherein, this batch total amount information can be a monochrome information, a gradient information or a colourity information of an image pixel.
7. image processing apparatus as claimed in claim 1, it comprises in addition:
One A/D converter, the data transaction that is used for receiving becomes numerical data;
The delayer of a plurality of series connection is coupled to this A/D converter, and each delayer is to be used for delaying a predetermined clock cycle;
One multiplexer is coupled to these a plurality of delayers and this central processing unit, and this multiplexer is to be used for producing a sampled signal according to this output signal; And
One controller is coupled to this A/D converter, this multiplexer and this carry reserve accumulator, and this controller is taken a sample to this numerical data according to this sampled signal, to produce this processing signals.
8. image processing apparatus as claimed in claim 7, it is a liquid crystal indicator.
9. one kind is utilized carry to keep the method that summation promotes image quality, includes:
In cycle the metrical information of a pixel is carried out a carry in a predetermined clock and keep the summation computing; And
When vertical synchronizing signal is effective, will carries out the carry of carry reservation add operation generation and carry out a carry transmission add operation.
10. method as claimed in claim 9, it comprises the metrical information of handling after calculating in addition.
11. method as claimed in claim 10, wherein, handling and calculating metrical information later is this calculating metrical information later to be carried out image white balance processing, an image focusing process or an image exposure handle.
12. method as claimed in claim 9, wherein, this metrical information can be a monochrome information, a gradient information or a colourity information of this pixel.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200610068204A CN100583943C (en) | 2006-03-20 | 2006-03-20 | Image processing apparatus for improving image quality using accumulator and correlation method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200610068204A CN100583943C (en) | 2006-03-20 | 2006-03-20 | Image processing apparatus for improving image quality using accumulator and correlation method thereof |
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| Publication Number | Publication Date |
|---|---|
| CN101043576A true CN101043576A (en) | 2007-09-26 |
| CN100583943C CN100583943C (en) | 2010-01-20 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103279323A (en) * | 2013-05-31 | 2013-09-04 | 福建星网锐捷网络有限公司 | Adder |
-
2006
- 2006-03-20 CN CN200610068204A patent/CN100583943C/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103279323A (en) * | 2013-05-31 | 2013-09-04 | 福建星网锐捷网络有限公司 | Adder |
| CN103279323B (en) * | 2013-05-31 | 2016-12-07 | 福建星网锐捷网络有限公司 | A kind of adder |
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| Publication number | Publication date |
|---|---|
| CN100583943C (en) | 2010-01-20 |
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