CN101040271A - 用于优化dma信道选择的方法和系统 - Google Patents
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Abstract
本发明提供一种主机总线适配器,其耦合到网络和主机计算系统。所述主机总线适配器包含直接存储器存取(“DMA”)模式检测模块,其从仲裁模块接收DMA信道标识符信息,所述仲裁模块从多个DMA信道接收请求,其中所述DMA模式检测模块包含DMA计数器,所述DMA计数器对所述仲裁模块专门服务单个DMA信道的次数进行计数,且如果DMA计数器值等于阈值,那么所述DMA模式检测模块启用单信道模式,在所述单信道模式期间,忽略标准交易规则来确定用于传送数据的DMA请求长度。启用所述单信道模式达某一持续时间。所述主机总线适配器包含基于规则的分段逻辑,其可通过主机总线适配器固件和/或单信道模式条件的检测而被启用和/或禁用。
Description
技术领域
本发明涉及计算系统,且更明确地说,涉及优化直接存储器存取(“DMA”)信道仲裁。
背景技术
通常使用存储区域网络(“SAN”),其中使多个存储器存储装置可用于各种主机计算系统。通常通过各种控制器/适配器来将SAN中的数据从多个主机系统(其包含计算机系统、服务器等)移动到存储系统。
主机系统通常包含若干功能组件。这些组件可包含中央处理单元(CPU)、主存储器、输入/输出(“I/O”)装置和流式存储装置(streaming storage device)(例如,磁带驱动器)。在常规系统中,主存储器经由系统总线或本地存储器总线耦合到CPU。主存储器用于在执行时间向CPU提供对存储在主存储器中的数据和/或程序信息的存取权。通常,主存储器由随机存取存储器(RAM)电路组成。具有CPU和主存储器的计算机系统通常被称为主机系统。
主机系统通常使用接口(例如,“PCI”总线接口)经由主机总线适配器(“HRA”,也可称为“控制器”和/或“适配器”)与存储系统通信。PCI代表外围组件互连(PeripheralComponent Interconnect),由Intel Corporation开发的本地总线标准。PCI标准全文以引用的方式并入本文中。大多数现代计算系统除包含较一般的扩展总线(例如,ISA总线)外还包含PCI总线。PCI是64位总线,且可以33或66MHz的时钟速度运行。
PCI-X是另一标准总线,其与使用PCI总线的现有PCI卡兼容。PCI-X将PCI的数据传送速率从132MBps改进为多达1GBps。PCI-X标准由IBM、Hewlett PackardCorporation和Compaq Corporation开发,以提高高带宽装置(例如,千兆位以太网标准(Gigabit Ethernet standard)和光纤信道标准(Fibre Channel Standard))以及作为群集的一部分的处理器的性能。
也使用各种其它标准接口来将数据从主机系统移动到存储装置。光纤信道是这样的一个标准。光纤信道(其全文以引用的方式并入本文中)是美国国家标准学会(AmericanNational Standard Institute,ANSI))提出的一组标准,其提供针对存储的串行传输协议和网络协议(例如,HIPPI、SCSI、IP、ATM和其它协议)。光纤信道提供输入/输出接口以满足信道和网络用户两者的需求。
iSCSI是基于小型计算机系统接口(“SCSI”)的另一标准(其全文以引用的方式并入本文中),其使主机计算机系统能够与包含磁盘和磁带装置、光学存储装置以及打印机和扫描仪的多种外围装置一起执行块数据输入/输出(“I/O”)操作。
主机系统与外围装置之间的传统的SCSI连接是通过并行布线进行的,且受到距离和装置支持约束条件的限制。对于存储应用来说,开发iSCSI以利用基于光纤信道和千兆位以太网标准的网络结构。iSCSI在已建立的联网基础设施上利用SCSI协议,且界定用于在TCP/IP网络上启用块存储应用的构件。iSCSI界定SCSI协议与TCP/IP的映射。
HBA使用DMA模块来在存储器位置之间或存储器位置与输入/输出端口之间执行数据传送。DMA模块通过利用传送控制信息来初始化DMA单元中的控制寄存器而起作用,而不涉及微处理器。传送控制信息通常包含源地址(待传送的数据块的开头部分的地址)、目的地地址和数据块的大小。DMA单元向装置提供地址和总线控制信号并从装置中提供地址和总线控制信号,以用于读取和/或写入循环。
在DMA单元中建构特定信道,以允许存储装置将数据直接传送到存储器存储装置且从存储器存储装置传送数据。可通过来自存储装置或主机系统的DMA请求信号(DREQ)来激活信道。DMA单元接收所述DREQ;提供DMA确认信号(DACK);且通过所述信道将数据传送到存储装置或从存储装置传送数据。HBA通常使用多个DMA信道,且具有仲裁模块,所述仲裁模块对于PCI(或PCI-Express)链路的存取进行仲裁。这允许HBA通过有效地处理命令、状态和数据来对(信道之间的)上下文进行仲裁和切换。以周期性短脉冲的形式对多个信道提供服务。在每个仲裁循环之后,当连接到选定信道时,即使所述选定信道与先前仲裁循环中的先前选定的信道相同,也存在用于对数据管线进行重新加载的额外时间。因此,如果多个信道不在使用中,那么最小仲裁循环增加了(多个时钟循环的)等待时间且影响整体性能。等待时间的原因是对于每一DMA循环来说都必须加载并更新某些资源。当连续的请求从同一DMA信道出现,且其它信道都不请求存取时,每次对所述同一信道提供服务时都存在额外的损失,因为在有效信道被重新初始化(或“重新装备”)的时间期间,另一信道不传送数据。
HBA常常必须在DMA信道之间,尤其在同时处理状态、命令和数据时,执行频繁的上下文切换。在其它情况下,HBA可通过主要使用单个DMA信道来操作。这在(例如)发生较大数据传送且特定DMA单元获得存取权的情况下发生。这些情况(即,单信道使用或频繁的上下文切换)是不可预测的。常规HBA不能自动感测单信道使用和相应地调节仲裁循环。
并且,工业标准(例如,PCI-Express标准)提供关于存储器读取/写入请求何时必须基于最大有效负载、最大读取请求大小和地址/数据对准而终止的交易规则。由于这些规则的缘故,较大DMA请求可能必须被分段成较小区块。在常规系统中,在准许同一DMA信道对下一片段进行另一请求之前,接收第一数据片段的完成。这是因为每个DMA信道仅允许一个未解决的请求。重复请求-响应序列,直到整个DMA请求完成为止。如果单个信道重复地用于较大数据传送,那么请求-响应-请求循环消极地影响整体性能。
因此,需要一种系统和方法,其可自动感测同一DMA信道是否正用于数据传送;将某一标准请求和分段规则禁用某一周期;且通过减小仲裁频率来有效率地传送数据。
发明内容
在本发明的一个方面,提供一种主机总线适配器,其耦合到网络和主机计算系统。所述主机总线适配器包含直接存储器存取(“DMA”)模式检测模块,其从仲裁模块接收DMA信道标识符信息,所述仲裁模块从多个DMA信道接收请求,其中所述DMA模式检测模块包含DMA计数器,其对所述仲裁模块专门服务单个DMA信道的次数进行计数,且如果DMA计数器值等于阈值,那么所述DMA模式检测模块启用单信道模式,在所述单信道模式期间,忽略标准交易规则来确定用于传送数据的DMA请求长度。启用所述单信道模式,持续某一持续时间。所述主机总线适配器包含基于规则的分段逻辑,其可通过主机总线适配器固件和/或单信道模式条件的检测而被启用和/或禁用。
DMA模式检测模块包含寄存器,其存储阈值,且所述阈值是可编程的。所述多个DMA信道包含位于主机总线适配器的接收和发射路径中的DMA信道。
在本发明的另一方面,提供一种允许主机计算系统通过网络与多个装置通信的系统。所述系统包含主机总线适配器,所述主机总线适配器包含DMA模式检测模块,其从仲裁模块接收DMA信道标识符信息,所述仲裁模块从多个DMA信道接收请求,其中所述DMA模式检测模块包含DMA计数器,其对所述仲裁模块专门服务单个DMA信道的次数进行计数,且如果DMA计数器值等于阈值,那么所述DMA模式检测模块启用单信道模式,在所述单信道模式期间,忽略标准交易规则来确定用于传送数据的DMA请求长度。所述主机总线适配器包含基于规则的分段逻辑,其可通过主机总线适配器固件和/或单信道模式条件的检测而被启用和/或禁用。
DMA模式检测模块包含寄存器,其存储阈值,且所述阈值是可编程的。
提供一种可通过网络与多个装置通信的主机计算系统。所述计算系统耦合到主机总线适配器,所述主机总线适配器包含DMA模式检测模块,其从仲裁模块接收DMA信道标识符信息,所述仲裁模块从多个DMA信道接收请求,其中所述DMA模式检测模块包含DMA计数器,其对所述仲裁模块专门服务单个DMA信道的次数进行计数,且如果DMA计数器值等于阈值,那么所述DMA模式检测模块启用单信道模式,在所述单信道模式期间,忽略标准交易规则来确定用于传送数据的DMA请求长度。
所述主机总线适配器包含基于规则的分段逻辑,其可通过主机总线适配器固件和/或单信道模式条件的检测而被启用和/或禁用。
在本发明的又一方面,提供一种用于通过使用HBA而在主机计算系统与多个装置之间传送数据的方法。所述方法包含:确定HBA中的同一DMA信道是否已得到专门服务持续某一持续时间;和启用单信道模式,在所述单信道模式期间,忽略标准交易规则来确定用于在主机计算系统与多个装置之间传送数据的DMA请求长度。
已经提供了此简要概括,使得可快速地理解本发明的本质。可参考以下关于附图作出的对本发明优选实施例的详细描述来获得对本发明的更完整的理解。
附图说明
现将参看优选实施例的附图来描述本发明的前述特征和其它特征。在附图中,相同组件具有相同参考标号。所说明的实施例意图在于说明而非限制本发明。附图包含以下各图:
图1A是展示SAN的各个组件的方框图;
图1B是根据本发明一个方面使用DMA模式选择的主机总线适配器的方框图;
图1C展示根据本发明一个方面使用DMA模式选择模块的多个DMA单元的方框图;
图1D展示根据本发明一个方面DMA模式选择模块的方框图;和
图2是根据本发明一个方面用于DMA处理的可执行步骤的过程流程图。
不同图中使用类似参考标号指示类似或相同项目。
具体实施方式
为了有助于理解优选实施例,将描述SAN和HBA的一般结构和操作。接着,将参考主机系统和HBA的一般结构来描述优选实施例的特定结构和操作。
SAN概述:
图1A展示SAN系统100,其使用HBA 106(称为“适配器106”)以便通过使用光纤信道存储区域网络114和115而在具有主机存储器101的主机系统(例如,200)与各种存储系统(例如,存储子系统116和121,磁带库118和120)之间通信。主机存储器101包含驱动器102,其通过使用输入/输出控制区块(“IOCB”)来经由适配器106协调所有数据传送。服务器117和119也可分别通过使用SAN 115和114来存取存储子系统。请求队列103和响应队列104维持在主机存储器101中,以便使用适配器106来传送信息。如图1B中所示,主机系统通过PCI核心模块(接口)137经由PCI总线105来与适配器106通信。
HBA 106:
图1B展示适配器106的方框图。适配器106包含用于接收和发射侧的处理器(也可称为“序列发生器”)“XSEQ”112和“RSEQ”109,其分别用于处理从存储子系统接收到的数据和将数据发射到存储子系统。此情境中的发射路径表示从主机存储器101经由适配器106到存储系统的数据路径。接收路径表示从存储子系统经由适配器106的数据路径。值得注意的是,仅将一个处理器用于接收和发射路径,且本发明并不限于任何特定数目/类型的处理器。缓冲器111A和111B分别用于存储接收和发射路径中的信息。
除接收和发射路径上的专用处理器之外,适配器106还包含处理器106A,其可为用于执行适配器106中的各种功能的精简指令集计算机(reduced instruction set computer,“RISC”)。
适配器106还包含光纤信道接口(也称为光纤信道协议管理器“FPM”)113A,所述光纤信道接口在接收和发射路径中分别包含FPM 113B和FPM 113。FPM 113B和FPM113允许数据移动到存储系统/从存储系统移出。
适配器106还经由连接件116A(图1A)(在下文中可交换地参考)和本地存储器接口122而耦合到外部存储器108和110。提供存储器接口122来管理本地存储器108和110。本地DMA模块137A用于获得将数据从本地存储器(108/110)移出的存取权。适配器106还包含串行/解串行器136,其用于将数据从10位格式转换成8位格式,和进行相反的转换。
适配器106还包含请求队列DMA信道130;响应队列DMA信道131;请求队列(1)DMA信道132,其与请求队列103和响应队列104介接;和命令DMA信道133,其用于管理命令信息。这些DMA信道耦合到仲裁器107,仲裁器107从DMA信道接收多个请求,且准许对某一信道进行存取。接收和发射路径两者都具有DMA模块129和135,其用于获得对信道的存取权以在接收/发射路径中传送数据。发射路径还具有调度器134,其耦合到处理器112并对发射操作进行调度。
主机处理器(未图示)在缓冲存储器108中设置共享数据结构。将主机命令存储在缓冲器108中,且初始化适当的序列发生器(即,109或112)以执行命令。
各个DMA单元(或信道,本说明书全文中可交换地使用)(例如,129、130、131、132、133和135)将请求发送到仲裁器107。基于已建立的标准仲裁规则来分析所述请求。当请求被准许时,通知DMA单元所述准许,且准许对特定信道进行存储器存取。
DMA模式选择模块107A(“模块107A”):
在本发明的一个方面,提供DMA模式选择模块107A,其自动检测(“自动感测”)何时准许对特定DMA信道进行连续(即,紧接(back-to-back))存取持续某一时间段。模块107A可启用“单信道”模式,所述“单信道”模式规避各种标准规则,例如断开数据块分段,这减少了仲裁循环的数目和重新初始化同一DMA信道所花费的周转时间。
模块107A还感测在启用单信道模式之后何时再次使用多个信道。当这种情况发生时,禁用单信道模式,且将标准分段技术用于较大数据传送。
图1C展示功能上与模块107A耦合的仲裁器107。多个DMA信道(例如,129和135)与仲裁器107耦合。每个DMA信道都具有请求管线(例如,129B和135B)和分段模块(例如,129A和135A)。分段模块将DMA传送分段成多个片段(或区块),以满足数据传送规则和/或在DMA传送太大时的情况。序列发生器109和112将信道任务命令(129C和135C)分别发送到DMA信道129和135。所述命令用于向仲裁器107产生请求。
分段模块129A和135B还基于某些规则(例如,应何时且如何对数据块进行分段)而操作。这些规则可通过固件而开启或关闭。这些规则中的一些规则基于如PCI-Express标准协议所强加的数据块长度和地址限制。也可通过检测下文所述的单信道模式条件来启用/禁用规则。
当准许存取信道时,将信息传递到模块107A。如果准许重复地存取同一信道且不存在竞争请求,那么模块107A启用单信道模式选择信号107F。这允许分段模块停止对数据块进行分段(和/或将数据块分成较大片段),并以较大区块的形式传送数据以避免仲裁循环。启用单信道模式,仅持续有限时间,使得一旦其它信道请求存取,那么就不会存在积压。
图1D展示模块107A的方框图。可通过适配器106固件来启用或禁用模块107A的自动感测模式。仲裁器107在每次准许对信道进行存取时提供信道的标识符(“信道ID”)107J。可通过固件用持久性阈值来对阈值寄存器(展示为PST_THR)107D进行编程。通过固件使用信号/命令107H来控制寄存器107D。命令/信号107I用于加载所述阈值。
每次仲裁器107准许DMA请求时,DMA序列计数器107B(DMA_SEQ_CNT)均维持运行计数(展示为107K)。通过固件使用命令/信号107G来启用计数器107B。比较模块107N比较当前DMA请求的信道ID与信道ID 107J。如果DMA信道ID 107J对于当前信道(107P)与对于上一信道是相同的,且计数器107B值(即,107L)小于寄存器107D值(即,107M)(如由逻辑107E确定),那么计数器107B增加。如果信道ID 107J不同,那么计数器107B重设,例如为1。当107L等于或大于107M时,那么产生单模式选择信号107F,且将其发送到分段逻辑(例如,129A或135A)。
图2展示用于自动感测DMA信道使用并启用单信道模式的可执行处理步骤的流程图。
当在步骤S200中固件通过命令/信号107G启用计数器107B时,过程开始,且在步骤S201中,通过命令/信号107I而在寄存器107D中加载阈值。
在步骤S202中,所述过程确定当前DMA信道ID(107P)是否与先前请求的信道ID(107J)相同。这由比较模块107N执行。如果信道ID不同,那么在步骤S203中,重设计数器107B。
如果信道ID相同,表示正服务于同一DMA信道,那么在步骤S202A中,递增DMA计数器107B。
在步骤S204中,逻辑107E将计数器值107L与阈值107M进行比较。如果107L不等于107M,那么对DMA请求进行仲裁,且使用标准规则对数据块进行分段,且增加计数器107B。
如果107L等于107M,那么在步骤S206中,启用单DMA信道模式。当不启用单信道模式时,那么遵循某些交易规则。举例来说,
读取请求不得超过最大读取请求大小;
写入请求不得超过最大有效负载大小;
读取和写入请求不得重叠4千字节(“KB”)地址片段;和/或
写入请求必须尽可能频繁地以128字节(“B”)边界终止(即,除非是序列中的不以128B地址结束的上一个请求)。
如果107L等于107M,那么通过命令/信号107F来启用单信道模式。
当启用单信道模式时,不使用前述交易规则来确定每个DMA请求的开始部分和结束部分。这将促使仲裁频率减小,因为传送的大小将增加。
值得注意的是,单信道模式可能仅由适配器106的固件允许持续某一持续时间。在自动禁用单信道模式之后,发生正常请求长度分段/仲裁。
尽管,已经参考特定实施例描述了本发明,但这些实施例仅仅是说明性的而不是限制性的。根据本揭示案和所附权利要求书将明了本发明的许多其它应用和实施例。
Claims (25)
1.一种主机总线适配器,其耦合到网络和主机计算系统,所述主机总线适配器包括:
直接存储器存取(“DMA”)模式检测模块,其从仲裁模块接收DMA信道标识符信息,所述仲裁模块从多个DMA信道接收请求,其中所述DMA模式检测模块包含DMA计数器,所述DMA计数器对所述仲裁模块专门服务单个DMA信道的次数进行计数,且如果所述DMA计数器值等于阈值,那么所述DMA模式检测模块启用单信道模式,在所述单信道模式期间,忽略标准交易规则来确定用于传送数据的DMA请求长度。
2.根据权利要求1所述的主机总线适配器,其中所述DMA模式检测模块包含寄存器,所述寄存器存储所述阈值,且所述阈值是可编程的。
3.根据权利要求1所述的主机总线适配器,其中所述多个DMA信道包含位于所述主机总线适配器的接收路径中的DMA信道。
4.根据权利要求1所述的主机总线适配器,其中所述多个DMA信道包含位于所述主机总线适配器的发射路径中的DMA信道。
5.根据权利要求1所述的主机总线适配器,其中启用所述单信道模式达某一持续时间。
6.根据权利要求1所述的主机总线适配器,其进一步包括:
基于规则的分段逻辑,其可通过主机总线适配器固件和/或单信道模式条件的检测而被启用和/或禁用。
7.一种允许主机计算系统通过网络与多个装置通信的系统,其包括:
主机总线适配器,其包含直接存储器存取(“DMA”)模式检测模块,所述DMA模式检测模块从仲裁模块接收DMA信道标识符信息,所述仲裁模块从多个DMA信道接收请求,其中所述DMA模式检测模块包含DMA计数器,所述DMA计数器对所述仲裁模块专门服务单个DMA信道的次数进行计数,且如果所述DMA计数器值等于阈值,那么所述DMA模式检测模块启用单信道模式,在所述单信道模式期间,忽略标准交易规则来确定用于传送数据的DMA请求长度。
8.根据权利要求7所述的系统,其中所述DMA模式检测模块包含寄存器,所述寄存器存储所述阈值,且所述阈值是可编程的。
9.根据权利要求7所述的系统,其中所述多个DMA信道包含位于所述主机总线适配器的接收路径中的DMA信道。
10.根据权利要求7所述的系统,其中所述多个DMA信道包含位于所述主机总线适配器的发射路径中的DMA信道。
11.根据权利要求7所述的系统,其中启用所述单信道模式达某一持续时间。
12.根据权利要求7所述的系统,其中所述多个装置包含存储装置。
13.根据权利要求7所述的系统,其中所述网络是基于光纤信道的。
14.根据权利要求7所述的系统,其中所述主机总线适配器包含基于规则的分段逻辑,其可通过主机总线适配器固件和/或单信道模式条件的检测而被启用和/或禁用。
15.一种可通过网络与多个装置通信的主机计算系统,其包括:
主机总线适配器,其在操作上耦合到所述主机计算系统,所述主机总线适配器包含直接存储器存取(“DMA”)模式检测模块,所述DMA模式检测模块从仲裁模块接收DMA信道标识符信息,所述仲裁模块从多个DMA信道接收请求,其中所述DMA模式检测模块包含DMA计数器,所述DMA计数器对所述仲裁模块专门服务单个DMA信道的次数进行计数,且如果所述DMA计数器值等于阈值,那么所述DMA模式检测模块启用单信道模式,在所述单信道模式期间,忽略标准交易规则来确定用于传送数据的DMA请求长度。
16.根据权利要求15所述的主机计算系统,其中所述DMA模式检测模块包含寄存器,所述寄存器存储所述阈值,且所述阈值是可编程的。
17.根据权利要求15所述的主机计算系统,其中所述多个DMA信道包含位于所述主机总线适配器的接收路径中的DMA信道。
18.根据权利要求15所述的主机计算系统,其中所述多个DMA信道包含位于所述主机总线适配器的发射路径中的DMA信道。
19.根据权利要求15所述的主机计算系统,其中启用所述单信道模式达某一持续时间。
20.根据权利要求15所述的主机计算系统,其中所述主机总线适配器包含基于规则的分段逻辑,其可通过主机总线适配器固件和/或单信道模式条件的检测而被启用和/或禁用。
21.一种使用耦合到网络的主机总线适配器(“HBA”)在主机计算系统与多个装置之间传送数据的方法,其包括:
确定是否已专门服务所述HBA中的同一直接存储器存取(“DMA”)信道达某一持续时间;和
启用单信道模式,在所述单信道模式期间,忽略标准交易规则来确定用于在所述主机计算系统与所述多个装置之间传送数据的DMA请求长度。
22.根据权利要求21所述的方法,其中DMA序列计数器保存仲裁模块已服务所述同一DMA信道多少次的计数。
23.根据权利要求22所述的方法,其中所述仲裁模块从多个DMA信道接收请求。
24.根据权利要求22所述的方法,其中将所述DMA序列计数器值与可编程阈值进行比较,以确定是否应启用所述单信道模式。
25.根据权利要求24所述的方法,其中所述可编程阈值存储在DMA模式检测模块中的寄存器中。
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CN107430758A (zh) * | 2015-03-25 | 2017-12-01 | 赛灵思公司 | 自适应视频直接存储器存取模块 |
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US20060053236A1 (en) | 2006-03-09 |
ATE425497T1 (de) | 2009-03-15 |
US7577772B2 (en) | 2009-08-18 |
WO2006029133A3 (en) | 2006-06-29 |
WO2006029133A2 (en) | 2006-03-16 |
EP1787205A2 (en) | 2007-05-23 |
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