CN101034342A

CN101034342A - Virtual LCD

Info

Publication number: CN101034342A
Application number: CN 200710097420
Authority: CN
Inventors: 朱曼平
Original assignee: 朱曼平
Current assignee: Beijing Tai Ge Technology Co. Ltd.
Priority date: 2007-05-09
Filing date: 2007-05-09
Publication date: 2007-09-12
Anticipated expiration: 2027-05-09
Also published as: CN100451947C

Abstract

The invention is a virtual LCD, in use, only needing a circuit board and software operating on PC to be able to virtually generate on PC LCDs of various resolutions. And the invention can replace the costly and inconvenient LCDs as making electronic experiment or developing electronic products, thus reducing the cost and improving the flexibility.

Description

A kind of virtual LCD

Technical field

The aid that uses when the invention belongs to the exploitation electronic product or carrying out electronic experiment can replace the LCD as circuit board demonstration output device in exploitation or experimentation.

Background technology

Along with coming of Digital Media epoch, a lot of electronic multimedia products all use LCD (hereinafter being abbreviated as LCD) as display device, as palm PC, use the 3.5 inch LCDs of resolution as 240*320, portable electronic device often uses 4.3 inches LCD of 480*272, the then 2.0 inches LCD that use 176*220 of smart mobile phone more.

For complying with this Digital Media trend, a lot of universities and vocational school have all set up the novel electronic laboratory gradually.Experimental facilities comprises various development boards, and with the supporting LCD of development board (this LCD links to each other with development board, and the demonstration output as development board is different from the LCD as computer monitor).The student can carry out the experiment of multimedia equipment software development on these equipment.

Adopt real LCD as follows as the shortcoming of development board output device: compare with the development board cost, LCD is expensive; Laboratory equipment use-pattern complexity, LCD is more fragile, brings more spendings to the laboratory; The student can only experimentize at the resolution of breadboard LCD, and for example breadboard LCD resolution is 240*320, and then the student can't carry out the widescreen multimedia player software design experiment of 480*272 resolution.(annotate: the small LCD that multimedia equipment uses is different with the PC display, and its resolution can't change)

Except that the laboratory, a lot of individuals also buy development board at one's own expense and supporting LCD experimentizes, and they also can run into same problem.

On the other hand, the enterprise of much doing multimedia equipment also will use LCD on stream naturally.For example some mp4 manufacturer can to release inner structure identical, but the LCD size multiple type product different with resolution.They just need to prepare multiple LCD in the process of exploitation, and change different LCD at any time and test on model machine, and are pretty troublesome like this, and damage model machine or LCD (as static) easily.

Summary of the invention

Carrying out electronic experiment or exploitation during electronic product, if use real LCD, have the cost height, fragile, resolution can't change, use shortcoming such as inconvenience.

Generally all can use PC when carrying out electronic experiment or exploitation electronic product.And PC itself has had giant-screen, high-resolution display.The present invention proposes a kind of virtual LCD, can be on PC the LCD of virtual various resolution.Needed only is a circuit board and the software that operates on the PC cheaply, has but improved reliability and dirigibility.

Below, " host computer " refers to PC, and " objective circuit plate " need to refer to development board or the electronic product model machine of LCD as display.

As shown in Figure 1, the present invention is made up of main circuit board and host computer software; Main circuit board comprises LCD interface simulation circuit and host computer interface circuit; Main circuit board is connected with host computer by the host computer interface circuit; LCD interface simulation circuit receives the LCD digital scanning signal from the objective circuit plate, be converted into video data after, issue host computer software by the host computer interface circuit; Host computer operation figure interface operation system, host computer software is opened a window on the display of host computer, and, imitating the scanning process of true LCD according to the video data of receiving, the picture that the objective circuit plate is exported shows in this window.

At first introduce LCD digital scanning interface.

Many LCD provide the digital scanning interface, and that the present invention will be virtual is exactly this class LCD.The digital scanning interface comprises pixel clock signal, line synchronizing signal, frame synchronizing signal, color signal.A typical LCD digital scanning signal as shown in Figure 2.These signals all are the input signals of LCD, and they control the epideictic behaviour of LCD jointly.Need LCD as the circuit board of display terminal as long as correctly provide these signals to LCD, can on LCD, demonstrate correct image.

Scanning be one frame by frame, in the frame line by line, in the row by the process of pixel, as shown in Figure 2.The LCD that with resolution is 320*240 is example (horizontal direction 320 pixels, vertical direction 240 pixels).If have on the LCD pixel coordinate (x, y), the pixel coordinate in the LCD upper left corner is (0,0), the lower right corner is (319,239).When pixel clock arrived, LCD just drew a pixel according to current color signal.LCD begins to draw from (0,0), then (1,0), (2,0) ... draw at the 0th row like this (being plotted to (319,0) has certainly just no longer drawn afterwards because surpassed the screen scope) always.When line synchronizing signal arrived, LCD will begin to draw from next line, i.e. (0,1), (1,1), (2,1) ...When frame synchronizing signal arrived, LCD will begin to draw from (0,0) again.Repeat for such one time one everywhere,, just reached the effect of dynamic demonstration when frame rate during greater than 24fps (frame per second).

Color signal is divided into 3 groups, respectively corresponding red, green, blue.The figure place of every group of signal is according to the number of colors of actual LCD and difference.For example 24 very color LCD red, green, blues all are 8; 5 of 16 very color LCD danger signals, 6 of greens, 5 of blue signals.

Above " clock arrival ", " synchronizing signal arrival " refer to that rising edge or negative edge appear in this signal.Some LCD adopts negative edge, and some LCD adopts rising edge, and what the signal among Fig. 2 adopted is rising edge.

The LCD digital scanning signal is produced by the chip on the objective circuit plate.The frame rate of sweep signal, number of colours, Horizontal number of pixels, Vertical number of pixels, rising edge still are parameters such as negative edge, generally are can be by the chip programming on the objective circuit plate is controlled.

Therefore, the function that the present invention will realize is exactly, and obtains from the objective circuit plate and receives the LCD digital scanning signal, is translated into video data, is sent on the PC.On the PC display, open a window (for example 320*240 size) that is used to simulate LCD then, again in the mode of software, according to the video data that receives, in this window, reappear above-mentioned scanning process, thus the sensation that to give a kind of this window of user be exactly a true LCD.

Because scanning is finished by software, therefore LCD that in theory can virtual arbitrary resolution, and can change resolution at any time.Consider that actual multimedia equipment mostly uses the LCD of resolution far below the PC display, the present invention can satisfy most of demand well.

The function that LCD interface simulation circuit is realized is presented as a LCD who has the digital scanning interface to the objective circuit plate just.The objective circuit plate does not also know that it is virtual LCD, and it is used as a real LCD, and provides digital scanning signal to it.

Therefore the interface of LCD interface simulation circuit and objective circuit plate is the set of number signal.This group signal comprises: pixel clock signal, line synchronizing signal, frame synchronizing signal, color signal.Color signal comprises 3 groups of signals, respectively corresponding red, green, blue color component.

LCD interface simulation circuit receives the digital scanning signal from the objective circuit plate, and it is mail to host computer by the host computer interface circuit.The host computer interface circuit has mainly played data has been collected effect on the PC from main circuit board.Typical interface has USB, IEEE1394, PCI, PCI-EXPRESS etc.

The transmission bandwidth difference that adopts different interfaces to reach, for example the USB high-speed transfer can reach 60MB/s (byte per second) in theory, and USB transmits at full speed and can reach 1.5MB/s, and IEEE1394 can reach 100MB/s, and PCI-EXPRESS*1 can reach 312.5MB/s.The bandwidth that the present invention needs depends on frame rate, the number of colors of wanting virtual how high-resolution LCD and digital scanning signal.For example the LCD digital scanning signal of 320*240,24 looks, 24fps needs the bandwidth of 320*240*24/8*24=5.53MB/s; 800*600,24 looks, 24fps then need 34.6MB/s.Therefore, adopt different interfaces, because the bandwidth difference, the performance of made virtual LCD is different.The higher resolution of interface support faster, frame rate faster.And can see, even adopt slower interface, also can be by reducing the purpose that frame rate reaches virtual High Resolution LCD.

The host computer interface circuit can adopt the special purpose interface chip, and these interface chips provide the corresponding interface link to PC on the one hand, provides data read and write interface to LCD interface simulation circuit on the one hand.This data read and write interface generally is the fifo interface of standard, comprises data-signal and control signal, and data-signal mostly is 8 or 16, and control signal comprises that read-write enables, does etc.

LCD interface simulation circuit is generally realized with programmable logic device (PLD).It is connected to LCD digital scanning signal interface on the one hand, is connected to the data read and write interface of host computer interface circuit on the one hand, and the data width of these two interfaces, read-write speed, read-write mode be difference all, therefore needs an inner FIFO.

The LCD interface simulation circuit data of pixel one by one writes inner FIFO sequentially, produces a byte stream.The byte number of each pixel correspondence becomes with the difference of embodiment.For the embodiment of superior performance, can support 24 very coloured silks, thus corresponding 3 bytes of every pixel; For embodiment cheaply, every pixel can only corresponding 1 byte, thereby only supports 256 kinds of colors.Attention: 24 very color LCD digital scanning signals also can be connected to the virtual LCD that only supports 256 looks, and method is a high position that only connects red, green, blue, and low level is left in the basket.

When row (frame) synchronizing signal arrived, (frame) synchrodata of will going write inner FIFO.Host computer software must correctly extract frame synchronization and row synchronizing information in byte stream.For example use 0xff (sexadecimal), 0x0f, three successive bytes of 0x0f to represent the row synchrodata, if occurred 0xff (for example representing green color data in 24 looks is 0x00,0xff, 0x00) in the color data, then obviously can obscure with synchrodata.Usually, solving the method for obscuring problem is to insert a 0xff again, obtain 2 0xff, and behind 2 continuous 0xff of host computer software discovery, will know that this is not a synchrodata, but a 0xff color data.

For the present invention, the way that another kind of solution is obscured is when certain color data is identical with synchrodata, revises its lowest order.The benefit of this method is to have reduced hardware complexity, reduced bandwidth demand, because need not to insert new byte, only need revise existing byte.For general data communication, revising raw data does not obviously allow, but it is then different for video data, for example for 24 looks, if red data just is 0xff, after changing it into 0xfe, though data have become, drawing descendant's eye is (the differentiating two kinds of adjacent colors in 1,600 ten thousand kinds of colors) that almost can't differentiate.

The work clock of LCD interface simulation circuit is asynchronous to pixel clock, and should just can fully sample faster than the several times of pixel clock.Its inner FIFO is actual to be realized with register file, like this can a plurality of data of write-once.For example, when pixel clock arrives, can in a work clock, write 3 bytes to inner FIFO for 24 looks.If the data read and write interface of host computer interface circuit is 16, then can be internally in a work clock FIFO read 2 byte datas, and be written in the host computer interface circuit.

When the host computer interface bandwidth is not enough, the host computer interface circuit can be provided with busy signal, can cause the inside FIFO of LCD interface simulation circuit only to write this moment and not read, therefore can overflow, the data that LCD interface simulation circuit will write when abandoning all and overflowing at once.

The process flow diagram of host computer software as shown in Figure 3.

The specific implementation of program, relevant with the mode of avoiding confusion with the synchrodata that main circuit board adopts, therefore " embodiment " part is later done description again.

Description of drawings

Fig. 1 is an entire block diagram of the present invention.

Fig. 2 is typical LCD digital scanning signal figure.

Fig. 3 is the host computer software flow pattern.

Fig. 4 is the USB implementation of main circuit board.

Fig. 5 is the PCI and the PCI-EXPRESS implementation of main circuit board.

Fig. 6 is the IEEE1394 implementation of main circuit board.

Embodiment

Embodiment one: hi-speed USB interface

Main circuit board hardware

The USB interface of high-speed transfer is adopted in this enforcement, supports 24 very coloured silks.Adopted the synchronous transfer module (Isochronous pattern) in four kinds of transmission modes of USB, and " high bandwidth " pattern of employing, promptly a little frame (microframe) lining can be carried out 3 transmission at most, can transmit 1024 bytes at every turn.Because per second has 8000 little frames, therefore transmission bandwidth can reach 23.4MB/s in theory.

The main circuit board structure mainly is made up of CY7C68013A, XC9572XL as shown in Figure 4.Other accessory circuit comprises 5V to the LDO voltage stabilizer of 3.3V, the EEPROM that is used to store USB device information, Resistor-Capacitor Unit etc., and the design of these circuit can be finished by the design of professional's reference chip handbook, repeats no more herein.

Select for use CY7C68013A as USB interface chip (being the host computer interface circuit).This chip internal is integrated USB transceiver, FIFO and high speed 8051.CY7C68013A provides a plurality of USB Transport endpoints.The byte stream that LCD interface simulation circuit generates transmits to host computer by the end points 2 of CY7C68013A.

CY7C68013A provides fifo interface so that FIFO in its sheet is read and write.Writing in the sheet data of FIFO will pack automatically and mail to host computer.The input of fifo interface data can be 8 bit wides or 16 bit wides, selects 8 bit wides herein.

As shown in Figure 4, LCD interface simulation circuit realizes that with programmable logic device (PLD) XC9572XL-VQ64 its IO interface definition is as follows:

I/O mouth title	Direction	Figure place	Effect
I/O mouth title	Direction	Figure place	Effect	Nreset	Input
	1	System reset		Nreset	Input
	1	System reset	Ifclk	Input	1	The system works clock is connected to the IFCLK pin of cy7c68013a, also is the FIFO work clock of cy7c68013a
Flagb	Input		Ifclk	Input	1
Flagb	Input		1	Host computer interface busy signal.Be connected to the FLAGB pin of cy7c68013a, when the inner FIFO of cy7c68013a is full, can be 0 (being that low level is effective) with this position
Vdr_i[7:0]	Input		1		8	The danger signal input
Vdr_i[7:0]	Input	Vdg_i[7:0]	Input	8	8	The danger signal input	The green input
Vdb_i[7:0]	Input	Vdg_i[7:0]	Input	8	8	The blue signal input	The green input
Vdb_i[7:0]	Input	Vframe	Input		8	The blue signal input
	1	Vframe	Input	Frame synchronizing signal
	1	Vline	Input	Frame synchronizing signal
	1	Vline	Input	Line synchronizing signal
	1	Vclk	Input	Line synchronizing signal
	1	Vclk	Input	Pixel clock signal
	1	Pktend_o	Output	Pixel clock signal
	1	Pktend_o	Output	End-of-packet.Be connected to the PKTEND pin of cy7c68013a, low level is effective, actual not use.
	1	Slwr	Output			1	FIFO writes and enables, and is connected to the SLWR pin of cy7c68013a, and low level is effective
Fifoaddr[1:0]	Output	Slwr	Output	2		1		Fifo address is connected to the FIFOADDR[1:0 of cy7c68013a] pin, be used to select one of 2,4,6,8 end points.
Fifoaddr[1:0]	Output	Fdata_o[7:0]	Output	2	8	Data fifo is connected to the FD[7:0 of cy7c68013a] pin

In the inside of XC9572XL following register is set:

Register name	Figure place	Effect
Register name	Figure place	Effect	vclk_s
	1	The pixel clock state	vclk_s
	1	The pixel clock state	vline_s
	1	The line synchronizing signal state	vline_s
	1	The line synchronizing signal state	vframe_s
	1	The frame synchronizing signal state	vframe_s
	1	The frame synchronizing signal state	vclk_trig
	1	Pixel clock arrives and indicates	vclk_trig
	1	Pixel clock arrives and indicates	vline_trig	1	Line synchronizing signal arrives and indicates
vframe_trig	1	Frame synchronizing signal arrives and indicates	vline_trig	1	Line synchronizing signal arrives and indicates
vframe_trig	1	Frame synchronizing signal arrives and indicates	slwr_i	1	FIFO writes and enables output latch
fdata[7:0]	8	The FIFO output latch	slwr_i	1	FIFO writes and enables output latch
fdata[7:0]	8	The FIFO output latch	stm[3:0]	4	Finite state machine (only having used low 2) with 4 states
vdr[7:0]	8	Red buffer memory	stm[3:0]	4	Finite state machine (only having used low 2) with 4 states
vdr[7:0]	8	Red buffer memory	vdg[7:0]	8	Green buffer memory
vdb[7:0]	8	Blue buffer memory	vdg[7:0]	8	Green buffer memory

The internal logic of XC9572XL is described below with VHDL language: (IO pin name wherein and register name are shown in preceding table)

Begin process (nreset, ifclk) begin if nreset='0'then--the vdr that resets＜=" 00000000 "; Vdg＜=" 00000000 "; Vdb＜=" 00000000 "; Fdata＜=" 00000000 "; Vclk_trig＜=' 0'; Vline_trig＜=' 0'; Vframe_trig＜=' 0'; Vclk_s＜=' 0'; Vline_s＜=' 0'; Vframe_s＜=' 0'; Stm＜=" 0000 "; Slwr_i＜=' 1';

Elsif ifclk'event and ifclk='1'then--system clock arrival vclk_s＜=vclk; Vline_s＜=vline; Vframe_s＜=vframe; If vclk_s='1'and vclk='0'and vclk_trig='0'then vclk_trig＜=' 1'; End if; If vline_s='1'and vline='0'and vline_trig='0'then vline_trig＜=' 1'; End if; If vframe_s='1'and vframe='0'and vframe_trig='0'then vframe_trig＜=' 1'; End if; If vclk_trig='1'then vclk_trig＜=' 0'; Stm＜=" 0001 "; Slwr_i＜=' 1'; If vframe_trig='1'then--write frame synchronization data vframe_trig＜=' 0'; Vdr＜=" 00000001 "; Vdg＜=" 00001111 "; Vdb＜=" 00001111 "; Elsif vline_trig='1'then--writing line synchrodata vline_trig＜=' 0'; Vdr＜=" 00000001 "; Vdg＜=" 11110000 "; Vdb＜=" 11110000 "; Else if vdr_i/=" 00000001 " then--do not obscure vdr＜=vdr_i; Else vdr＜=vdr_i (7 downto, 1) ﹠amp; Amp; ' 0';--obscure lower position 0 end if; If vdg_i/=" 00000001 " then vdg＜=vdg_i; Else vdg＜=vdg_i (7 downto, 1) ﹠amp; Amp; ' 0'; End if;

If vdb_i/=" 00000001 " then vdb＜=vdb_i; Else vdb＜=vdb_i (7 downto, 1) ﹠amp; Amp; ' 0'; End if; End if; Else if stm=" 0000 " then slwr_i＜=' 1'; Else if (flagb='1') then slwr_i＜=' 0'; Else--host computer interface hurry slwr_i＜=' 1'; End if; If stm=" 0001 " then fdata＜=vdr; Stm＜=" 0010 "; Elsif stm=" 0010 " then fdata＜=vdg; Stm＜=" 0011 "; Elsif stm=" 0011 " then fdata＜=vdb; Stm＜=" 0000 "; End if; End if; End if; End if; End process; Fdata_o＜=fdata;--data fifo output slwr＜=slwr_i;--FIFO writes and enables output, the effective fifoaddr of low level＜=" 00 ";--fifo address, selection end points 2 pktend_o＜=' 1';--low level is effective, and this place makes this invalidating signal end Behavioral;

The specific explanations of above-mentioned VHDL code is as follows.

The system works clock of XC9572XL is ifclk, and this clock is exported by cy7c68013a.Can be chosen as 30MHz or 48MHz by programming, adopt 48MHz in this enforcement.Ifclk also is the work clock of the FIFO of cy7c68013a, and when slwr was low level, the arrival of ifclk rising edge, the data of fdata_o were written in the FIFO of cy7c68013a.

It all is negative edge effectively (it is effective that simple modification promptly can be changed into rising edge) that this enforcement requires pixel clock, line synchronizing signal, the frame synchronizing signal of the output of objective circuit plate.When system clock arrived, vclk_s, vline_s, vframe_s latched the level of pixel clock, line synchronizing signal, frame synchronizing signal respectively.With the pixel clock is example, if the pixel clock state in the last moment that vclk_s latchs is 1, and the input of current pixel clock is that vclk is 0, and then the decline of pixels illustrated clock has arrived, and at this moment just vclk_trig is put 1, shows " pixel clock arrival ".Vline_trig and vframe_trig and inferior similar.

Therefore, for fully sample vclk, vline, vframe, system clock ifclk must be enough high, otherwise can lose some negative edge.General ifclk gets final product greater than 6 times of vclk.Ifclk is 48MHz in this enforcement, so vclk should be greater than 8MHz.This can satisfy the requirement of most small LCD, is 320*240*24=1.84MHz as 320*240,24 looks, the corresponding vclk of 24fps.

In the reality, input signal vclk, vline, vframe may have noise, false triggering therefore occurs, and promptly original signal does not arrive, and but is judged as signal and arrives.This can solve by general " going shake " circuit.Promptly have only certain signal continuously sampling several times all with the state of last registration not simultaneously, think that just this signal overturns.For example, can followingly go shake for vclk:

　　          if vclk=vclk_s then　　             vclk_f＜="0000";　　          else　　             if vclk_f="0001"then　　                vclk_s＜=not vclk_s;　　                vclk_f＜=″0000″;　　                if vclk_s='1'and vclk_trig='0'then　　                   vclk_trig＜='1';　　                end if;　　             else　　                vclk_f＜=vclk_f+1;　　             end if;　　          end if;

As above-mentioned code, vclk_s keeps the state of last registration, has introduced a counter vclk_f (being initialized as 0 when resetting).The input different with vclk_s that the vclk_f record occurs continuously if found 2 (also can be made as more a plurality of) continuously, just thinks that input signal has really overturn, the sign of signalization arrival simultaneously vclk_trig.

Can do similar processing for vline and vframe.

" the inside FIFO of LCD interface simulation circuit " in this enforcement is actual to be realized by vdr, vdg, three eight bit registers of vdb and state machine stm.All be to write whole 3 registers at every turn.When frame synchronizing signal arrives, " 0x01,0x0f, 0x0f " write this 3 registers; When line synchronizing signal arrives, " 0x01,0xf0,0xf0 " write this 3 registers; When pixel clock arrives, 24 current color inputs are write this 3 registers.If comprise 0x01 in the color data, then obscure with synchrodata, therefore will obscure the extreme lower position 0 (its effect changes 0x00 exactly into) of data.

If original data also are not read out among the FIFO, then directly cover legacy data (3 byte).

The implication of state machine stm is as shown in the table:

stm[3:0]	The state implication
stm[3:0]	The state implication	0000	The FIFO sky
0001	FIFO is full, and vdr is to cy7c68013a in output	0000	The FIFO sky
0001	FIFO is full, and vdr is to cy7c68013a in output	0010	FIFO is full, and vdg is to cy7c68013a in output
0011	FIFO is full, and vdb is to cy7c68013a in output	0010	FIFO is full, and vdg is to cy7c68013a in output

If FIFO has data and host computer interface not to be in a hurry, when then ifclk arrives, a byte is write host computer interface circuit (being the FIFO of cy7c68013a), write which byte and depend on stm, as above shown in the table.

Main circuit board software

Cy7c68013a is built-in 8051 single-chip microcomputers.Because cy7c68013a has handled most of usb communication work automatically, for this enforcement, only need get final product back being configured that reset to the single-chip microcomputer register, data transmission is afterwards finished fully automatically, need not software control.Concrete configuration is as follows:

Register	Implication
Register	Implication	IFCONFIG=0xe3	Enable fifo interface, be set to the synchronous working pattern, and work clock is set to 48MHz
EP2CFG=0xdb	Enable end points 2, be set to synchronous transfer module, 3 1024 bytes bufferings.	IFCONFIG=0xe3
EP2CFG=0xdb		EP2AUTOINLENH=0x04 EP2AUTOINLENL=0x00 EP2FIFOCFG=0x08	End points 2 is set to automatic IN pattern, and the length of IN is made as 1024 bytes automatically.
EP2ISOINPKTS=3;	Adopt the high bandwidth synchronous transfer module	EP2AUTOINLENH=0x04 EP2AUTOINLENL=0x00 EP2FIFOCFG=0x08
EP2ISOINPKTS=3;	Adopt the high bandwidth synchronous transfer module	PINFLAGSAB=0xcc; PINFLAGSCD=0xcc;	All FIFO sign outputs all are configured to " end points 2 is full " sign

Simultaneously, endpoint descriptor that should end points 2 is set to the maximum transfer size of synchronous IN end points and 3072 bytes.

The literary style of complete routine is existing elaborating in the application manual of cy7c68013a, repeats no more herein.

Host computer software

The process flow diagram of host computer software as shown in Figure 3.

Main circuit board needs the corresponding apparatus driver as a kind of USB device on host computer.The realization of this driver belongs to the category of general USB device exploitation, and is irrelevant with the art of this patent, therefore repeats no more.The application manual of cy7c68013a has provided the identifying code and the design guidelines of driver.

Being implemented as follows of plotter program:

x=0,y=0;

t0=0;t1=0;t2=0;m=0;

Initialization apparatus; Open window; Set up image buffer;

If continue to show

The access means driver obtains a blocks of data;

Analyze successively this time obtain each byte of data

t0=t1;

t1=t2;

The byte of t2=present analysis;

If t0=0x01{ // synchronizing information

If t1=0x0f and t2=0x0f{ // frame synchronization

x=0;y=0;

m=0;

With the copying image in the image buffer in window;

T1=0xf0 and t2=0xf0{ // row are synchronous else if

x=0;

y=y+1;

m=0;

}

Otherwise

m=m+1;

If m=3{ // gather enough 3 bytes is equivalent to receive a pixel

If coordinate (x, y) do not exceed image buffer scope

Image buffer (x, y) locate to draw red for t0, green for t1,

Blueness is the pixel of t2;

}

x=x+1;

m=0;

}

Otherwise { withdrawing from }

In the said procedure, the reason of setting up image buffer is for most graphical interfaces operating systems, and as windows or linux, directly the speed of painting on screen a little is slower, if each point all is drawn directly into screen and gets on, then generally can't reach the effect that real time scan shows.Therefore earlier image buffer inside-paint point (speed is very fast), draws and to put in order frame behind the full frame again and copy in the window on the screen (this speed is also slower, but per second only need carry out tens times).

Other embodiment: pci interface, PCI-EXPRESS interface, IEEE1394 interface

Other implements with embodiment one basic identical, and core of the present invention is the scanning reproducing technology of LCD interface simulation and host computer, and the host computer interface mainly plays the effect of data channel, promptly a kind of current techique.

If the employing pci interface then uses PCI9054 as the pci interface circuit, use IDT71V2101 as buffering FIFO, as shown in Figure 5.

If adopt the PCI-EXPRESS interface, then use PEX8311 as the PCI-EXPRESS interface circuit, use IDT71V2101 as buffering FIFO, as shown in Figure 5.

If adopt the IEEE1394 interface, then use TSB12LV32 (built-in FIFO) as the IEEE1394 link layer controller, use TSB41AB1 as the IEEE1394 phy controller, as shown in Figure 6.

For above-mentioned three kinds of embodiments, finally all offered LCD interface simulation circuit fifo interface.

The host computer interface circuit realizes with programmable logic device (PLD) that still its internal logic and embodiment one are basic identical, and required modification all is the different requirements of the chip that adopted at the host computer interface circuit.

The concrete circuit of above-mentioned embodiment connects and can finish according to the document of description in the embodiment one and respective chip and the standard of interface.

For host computer software, mainly be to write the corresponding driving program, and plotter program is all identical with embodiment one.Driver Design is a current techique, and relevant speciality personnel can realize.

Claims

1, a kind of virtual LCD is characterized in that being made up of main circuit board and host computer software; Main circuit board comprises LCD interface simulation circuit and host computer interface circuit; Main circuit board is connected with host computer by the host computer interface circuit; LCD interface simulation circuit receives the LCD digital scanning signal from the objective circuit plate, be converted into video data after, issue host computer software by the host computer interface circuit; Host computer operation figure interface operation system, host computer software is opened a window on the display of host computer, and, imitating the scanning process of true LCD according to the video data of receiving, the picture that the objective circuit plate is exported shows in this window.

2, virtual LCD according to claim 1 is characterized in that: the interface of LCD interface simulation circuit and objective circuit plate is one group of LCD digital scanning signal; This group signal comprises: pixel clock signal, line synchronizing signal, frame synchronizing signal, color signal; Color signal comprises 3 groups of signals, respectively corresponding red, green, blue color component.

3, virtual LCD according to claim 1 is characterized in that: LCD interface simulation circuit has an inner FIFO; When frame synchronizing signal arrived, LCD interface simulation circuit write inner FIFO with the frame synchronization data; When line synchronizing signal arrives, LCD interface simulation circuit will be gone synchrodata and be write inner FIFO; When pixel clock arrived, LCD interface simulation circuit generated color data according to color signal, and it is write inner FIFO; If color data and frame synchronization data or row synchrodata are obscured, then color data is filled or revised, write FIFO again, obscure thereby eliminate.

4, virtual LCD according to claim 1 is characterized in that: the host computer interface is one of USB, IEEE1394, PCI, PCI-EXPRESS; The host computer interface circuit is used to realize the interface that adopted.

5, virtual LCD according to claim 1 is characterized in that: the interface of LCD interface simulation circuit and host computer interface circuit is the set of number signal; This group signal comprises; Data-signal, write enable signal, busy signal; When busy signal was invalid, LCD interface simulation circuit was written into the host computer interface circuit from its inner FIFO sense data (if data are arranged).

6, virtual LCD according to claim 1, it is characterized in that: host computer software is opened up an image buffer with its identical size of opening of window, and safeguard a two-dimensional coordinate (x, y), the position of the current scanning element of this coordinate representation; When host computer software is received color of pixel data, just its image buffer (x, (if (x y) drops on buffer zone and then do not draw outward), the color of drafting is by the decision of this color data, and x is increased 1 y) to locate to draw this pixel; When receiving capable synchrodata, x is put 0, y is increased 1; When receiving the frame synchronization data, x is put 0, y is put 0, and with the copying image in the image buffer in window.