[summary of the invention]
Purpose of the present invention will overcome above-mentioned deficiency exactly, and a kind of TD-SCDMA path-measuring receiver that adapts to third generation communication protocol is provided;
Another object of the present invention is to provide a kind of method for processing baseband signal of path-measuring receiver.
The objective of the invention is to be achieved through the following technical solutions:
The present invention is applied to the path-measuring receiver of TD-SCDMA, comprising:
Radio-frequency (RF) Receiving Device from aerial coupling TD-SCDMA downstream signal, is exported the baseband signal of I, Q difference by antenna;
Band signal processor is measured the diverse network performance parameter based on above-mentioned IQ baseband signal;
The parameter display unit shows the diverse network performance parameter in real time.
Wherein, described band signal processor comprises:
Analog to digital converter is converted to number format with I, the Q baseband signal of radio-frequency (RF) Receiving Device;
Filtration module carries out matched filtering to the downstream signal of number format;
The searching carrier module, it is the strongest to seek in the special frequency channel signal energy in filtered downstream signal, and the frequency on can be synchronously;
Phase-locked loop module is locked in radio-frequency (RF) Receiving Device on the frequency of being determined by the searching carrier module;
Synchronization module carries out synchronous detecting to filtered downstream signal, carries out synchronously the Midamble data and the broadcast channel of the time slot 0 after the output synchronously;
Channel estimation module, the characteristic of the wireless channel of the signal after going out synchronously with described Midamble data estimation;
The joint-detection module, utilize characteristics of radio channels and synchronously after signal carry out multipath merging and despreading, scramble process, the formation broadcast channel data;
Channel decoding module is decoded to broadcast channel data, solves the Bit data of broadcast channel;
The parameter testing module is carried out the measurement of performance parameter to broadcast channel data;
Main control module is used for control and coordinates whole band signal processor, and provides the interface that electrically connects with the parameter display unit to realize data interaction.
It is 2010 to 2025MHz radiofrequency signal that the needs that be to adapt to the TD-SCDMA agreement, described radio-frequency (RF) Receiving Device only receive frequency range.
In the specific implementation of hardware, described phase-locked loop module, searching carrier module, synchronization module, channel estimation module and joint-detection module realize by being integrated in the fpga chip; Described channel decoding module is integrated in the dsp chip and realizes; Described main control module is integrated in the ARM chip and realizes; Described parameter testing module is realized jointly by fpga chip and dsp chip.
In addition, this path-measuring receiver also comprises the GPS module, and the main control module electric connection with described Base-band Processing System receives global positioning information by main control module by the GPS module.
Generally speaking, described parameter display unit is the computer system that has disposed special-purpose software.
Second purpose of the present invention provides the method for processing baseband signal that a kind of TD-SCDMA of being used for path-measuring receiver is handled the performance parameter of I, Q baseband signal final output signal, comprises the steps:
A, downstream signal is sampled, the IQ baseband signal of simulation is converted into number format;
B, digital baseband signal is carried out synchronous detecting, signal is carried out finding the original position of the frame of TD-SCDMA signal, and finding out optimum sampling point synchronously;
The Midamble data of C, taking-up time slot 0 are carried out channel estimating, estimate characteristics of radio channels;
D, utilize characteristics of radio channels, and the Midamble data of the time slot 0 after taking out synchronously, carry out the merging of multipath and despreading, scramble process, the data of outgoing broadcast channel;
E, broadcast channel is carried out channel-decoding, solve the Bit data of broadcast channel;
F, each network performance parameter is measured.
Particularly, the described network performance parameter of step F comprise following any one or a few: the received signal code power of descending synchronous code, P-CCPCH channel, Interference Signal Code Power, signal power interfering signal power are than the interference than, received signal intensity indication and descending synchronous code of, sign indicating number power and interfering signal power.
Compared with prior art, the present invention possesses following advantage: cooperate with base station simulating transmitting machine, for 3-G (Generation Three mobile communication system) provides a kind of brand-new drive test receiving instrument, realize new network performance parameter metering system by new structure, solved the problem that the TD-SCDMA network coverage is optimized; In addition,, realized high integration, made machine volume less, the convenient application because path-measuring receiver of the present invention adopts chips such as FPGA, DSP, ARM to realize.
[embodiment]
The present invention is further illustrated below in conjunction with drawings and Examples:
See also Fig. 1 path-measuring receiver of the present invention mainly by band signal processor 2, parameter display unit 3, radio-frequency (RF) Receiving Device 1, GPS module 4 and antenna are formed, be connected by the SMA head between antenna and the radio-frequency (RF) Receiving Device 1, radio-frequency (RF) Receiving Device 1 is by the TD-SCDMA downstream signal of antenna from aerial coupling base station or base station simulating transmitting machine, after carrying out Filtering Processing, socket interface by 20 pins is transferred to band signal processor 2 and carries out a series of signal processing, finally obtain the diverse network performance parameter of the signal that obtains in this physical location, export parameter display unit 3 to and show.Usually, described parameter display unit 3 adopts the computer system that has been equipped with special-purpose software to realize, mainly be to realize that the graphical of measurement parameter shows in real time, for the user provides an in real time direct parameter estimator platform, functions such as graphically demonstration of data in real time, playback, electronic chart, data analysis, report generation are provided, about the specific implementation of software, at this not all right enumeration.GPS module 4 then can provide global positioning information for band signal processor 2 by the RS232 interface.
Be synergistic relation between band signal processor 2 and the radio-frequency (RF) Receiving Device 1: the signal that radio-frequency (RF) Receiving Device 1 is transferred to band signal processor 2 mainly is the baseband I Q signal of simulation and the stable index signal of phase-locked loop, and band signal processor 2 to be transferred to the signal of radio-frequency (RF) Receiving Device 1 mainly be power supply so that support radio-frequency (RF) Receiving Device 1 work; The digital gain control signal, and control its gain; Frequency deviation control analog voltage signal is with the VCXO of control radio-frequency (RF) Receiving Device 1, with the frequency departure of control radio-frequency (RF) Receiving Device 1 with the base station; The configuration signal of phase-locked loop, with the phase-locked-loop configuration of control radio-frequency (RF) Receiving Device 1, the frequency of configuration phase-locked loop.
See also Fig. 4, the hardware that has disclosed described radio-frequency (RF) Receiving Device 1 constitutes.Radio-frequency (RF) Receiving Device 1 adopts the superhet design, receives the radiofrequency signal of TD-SCDMA frequency range 2010~2025MHz, exports the baseband signal of IQ difference, has the input dynamic range of 75dB.
Radio-frequency (RF) Receiving Device 1 comprises formations such as radio-frequency filter chip, intermediate-frequency filter chip, LNA chip, mixer chip, demodulator chip, gain controlling chip.Wherein antenna electrically connects by SMA head and first radio-frequency filter, realizes the rf filtering of the first order; First radio-frequency filter and a low noise amplifier electrically connect, and realize the amplification of radiofrequency signal; Low noise amplifier and second radio-frequency filter electrically connect, and realize partial rf filtering processing; Partial radio-frequency filter and frequency mixer electrically connect, and realize radiofrequency signal is converted into intermediate-freuqncy signal; Frequency mixer and intermediate-frequency filter electrically connect, and realize the Filtering Processing of intermediate-freuqncy signal; Intermediate-frequency filter and gain controlling chip electrically connect, and realize the gain controlling of signal; Gain controlling chip and demodulation chip electrically connect, and realize intermediate-freuqncy signal is demodulated into the baseband I Q signal, output to band signal processor 2 then and carry out the data sampling processing.
See also Fig. 3, band signal processor 2 adopts the mode of modularization pipeline processes to design, and each module is relatively independent, and related few between the module, data interaction is few.Specifically comprise:
The analog-digital commutator 20 of two-way carries out 4 samplings to I, the Q baseband signal of the difference of radio-frequency (RF) Receiving Device 1 output, and I, the Q baseband signal of simulation is converted to number format;
Filtration module 21 adopts the FIR filter that I, the Q signal of number format are carried out matched filter processing;
Searching carrier module 22, use new searching method, revise yield value, search for all frequencies, and signal energy is sorted, preceding 8 frequencies the strongest to energy carry out synchronous searching, if on not synchronous under some gains, the increasing that then will gain continues synchronous searching, up to searching for successfully.Frequency on having guaranteed synchronously like this is the strongest frequency of energy.
Phase-locked loop module, the frequency of searching carrier module 22 just can send the phase-locked-loop configuration signal to radio-frequency (RF) Receiving Device 1 by this phase-locked loop module once determining, radio-frequency (RF) Receiving Device 1 is locked on the frequency of being determined by searching carrier module 22;
Synchronization module 23, carry out synchronous detecting after searching carrier wave, comprise sampled point synchronously, frame synchronization, multiframe synchronously, sampled point selection etc., find out the original position of the frame of TD-SCDMA signal, the Midamble data and the broadcast channel of the time slot 0 after the final output synchronously;
Channel estimation module 24 takes out the Midamble data of described time slot 0 and carries out channel estimating, and the characteristic of the wireless channel of the signal after estimating is synchronously given results estimated the joint-detection module then;
Joint-detection module 25 adopts the Rake receiver, and the result who utilizes channel estimation module 24 is the data of characteristics of radio channels with the synchronous time slot 0 afterwards of radio-frequency (RF) Receiving Device 1, carries out multipath merging and despreading, scramble process, last outgoing broadcast channel data;
Channel decoding module 26 is decoded to broadcast channel data, solves the Bit data of broadcast channel;
Parameter testing module 28, be distributed in each module of band signal processor 2, perhaps independent the existence, particularly, parameter testing module 28 is mainly carried out the test of performance parameter to broadcast channel data, comprises the parameters such as jamming rate of RSSI (indication of acknowledge(ment) signal intensity), RSCP (the received signal error rate), ISCP (the interference signal error rate), SIR (signal power interfering signal power ratio), Ec/Io (sign indicating number power and interfering signal power ratio), DwPTS (descending synchronous code) and DwPTS;
Main control module 27 is used for control and coordinates whole band signal processor 2, and provides the interface that electrically connects with parameter display unit 3 to realize data interaction.Main control module 27 can be connected with parameter display unit 3 by USB, RS232 and/or 485 monitor-interfaces, and the RS232 interface that is connected with described GPS module 4 also is provided, and depends on the circumstances.
See also Fig. 4, the main particular hardware that discloses band signal processor 2 realizes, is made of the analog-digital commutator 20 of a two-way, serial digital to analog converter, fpga chip, dsp chip, ARM chip, FLASH flash chip, sdram memory chip, RS232 interface chip, USB interface chip, 485 monitor-interface chips etc.
The phase-locked loop of FPFA chip and ADC chip, serial D AC chip, dsp chip, ARM chip, FLASH chip, SDRAM chip, radio-frequency (RF) Receiving Device 1, gain controlling chip electrically connect.Wherein the ADC of FPGA and two-way uses 12 IO mouths to electrically connect, and receives the IQ sampled data of ADC; FPGA and serial D AC use 3 IO mouths to electrically connect, and use the SPI agreement to be used for the DAC configuration; FPGA and dsp chip use 16 IO mouths and DSP data/address bus, 8 IO mouths and the electric connection of DSP address bus, are used for carrying out data interaction with dsp chip; FPGA and ARM chip use 16 data/address bus, 8 address bus to electrically connect, and are used for realizing data interaction with the ARM chip; FPGA uses the data/address bus of 16 IO mouths and FLASH chip, and 8 IO mouths electrically connect with the address bus of FLASH, is used for FPGA from FLASH chip reading of data and store data; FPGA uses the data/address bus of 32 IO mouths and SDRAM, and the address bus electric connection of 21 IO mouths and SDRAM is used for interaction data between FPGA and the SDRAM.Fpga chip uses the SPI interface of the phase-locked loop of 3 IO mouths and radio-frequency (RF) Receiving Device 1 to electrically connect, and is used for phase-locked-loop configuration; FPGA uses the digital gain control chip of 9 IO mouths and radio-frequency (RF) Receiving Device 1 to electrically connect, and is used for the gain controlling of radio-frequency (RF) Receiving Device 1; FPGA also uses the stabilized index signal of 1 IO mouth and radio-frequency (RF) Receiving Device 1 to electrically connect, and is used to detect the stabilized state of radio-frequency (RF) Receiving Device 1.
The ARM chip electrically connects with fpga chip, dsp chip, FLASH chip, SDRAM chip, USB chip, RS232 chip, 485 chips respectively.Wherein ARM uses 16 bit data bus, 8 bit address buses and fpga chip to electrically connect, and realizes the data interaction with FPGA; The ARM chip uses 8 bit data bus and dsp chip to use the HPI interface to be connected, and is used for ARM chip and dsp chip and carries out data interaction; The ARM chip uses 32 bit data bus and SDRAM to electrically connect, and the program, the data that are used for the operation of ARM chip are carried out on SDRAM alternately.The ARM chip uses 16 data/address bus and FLASH chip to electrically connect, and realizes the storage of program; ARM chip and RS232, USB and/or 485 chips electrically connect, and realize the data interaction with computer.
Dsp chip and ARM chip, fpga chip electrically connect.Wherein dsp chip uses the data/address bus of HPI mouth and ARM chip to electrically connect, and realizes the data interaction with the ARM chip; Dsp chip uses 16 bit data bus and FPGA to electrically connect, and realizes the data interaction with FPGA.
Band signal processor 2 also comprises power management, Clock management module, and wherein power management module is realized whole system, comprises the power supply supply and the management of band signal processor 2, radio-frequency (RF) Receiving Device 1, and realizes the Charge Management to battery.The Clock management module realizes the Clock management of whole system, provides ADC, FPGA, DSP, ARM that clock signal is provided.
In the specific implementation of hardware, described phase-locked loop module, searching carrier module 22, synchronization module 23, channel estimation module 24 and joint-detection module 25 realize by being integrated in the fpga chip; Described channel decoding module 26 is integrated in the dsp chip and realizes; Described main control module 27 is integrated in the ARM chip to be realized; Described parameter testing module 28 is realized jointly by fpga chip and dsp chip.
Concrete, the parsing of concrete parameter in the parameter testing module 28:
1, the parameter measurement of RSCP
Receive the data of DwPTS data or P-CCPCH channel, calculate the energy of its each code element then, the average RSCP parameter that is afterwards.
2, the parameter measurement of ISCP
Receive the data of DwPTS data or P-CCPCH channel, use relevant mode to calculate the irrelevant energy of DwPTS or P-CCPCH, be the ISCP parameter.
3, the parameter measurement of SIR
SIR=RSCP/ISCP * SF, wherein SF is a spreading factor.
4, the parameter measurement of Ec/Io
Ec/Io at first calculates the symbol power that receives the P-CCPCH channel only at the P-CCPCH channel, is calculating interference power, and symbol power is than interference power: RSCP/ISCP.
Wherein, RSSI can be incorporated in the searching carrier module 22 of fpga chip and realize that RSCP, ISCP, SIR, Ec/Io can be incorporated in the dsp chip and realize.
The purpose of searching carrier module 22 is that (2010~2025MHz) to seek signal energies the strongest, and the frequency on can be synchronously in the TD-SCDMA frequency range.Its concrete workflow is:
1. configuration radio-frequency (RF) Receiving Device 1 gain, configuration mode disposes from low to high.The initial configuration value configuration decay of rf gain is maximum.
2. under the situation of radio-frequency (RF) Receiving Device 1 configuration fixed gain, the energy of all frequencies is calculated once, and will carry out energy ordering above the energy of energy threshold.Find out the strongest preceding 8 frequencies of signal energy.
3. the strongest preceding 8 frequencies of energy are carried out synchronous searching by order from high to low.
4. judge whether can be synchronously on.
5. all frequencies synchronization failure is all revised the gain of radio-frequency transmitter, and pad value reduces, repeating step 1~3.On synchronously, if pad value has been minimum, or synchronization failure, represent synchronization failure so.
Synchronization module 23 is realized the search of descending synchronous code, finds the strongest descending synchronous code of signal, and realizes following the tracks of synchronously, makes path-measuring receiver can carry out parameter measurement in real time.Its concrete workflow is:
1, down-going synchronous code searching
A. use the data of descending synchronous code sign indicating number number 0 and a complete frame received signal to carry out related operation.
B. correlated results is asked mould square.
C. maximizing in mould square.
D. revise descending synchronous code, circulation step A~C, up to all descending synchronous code sign indicating numbers number all computing finish.
E. find out 32 maximums in the maximum.
F. judge whether this maximum crosses thresholding.
If thresholding only G., the synchronous searching failure.
H. cross thresholding, this peaked sequence number is exactly a descending synchronous code sign indicating number number.Synchronous searching finishes.
2, follow the tracks of synchronously
A) descending synchronous code on using synchronously carries out relevant with the signal that receives.
B) correlated results is asked mould square.
C) to the mould of frame maximizing square as a result, the position of maximizing.
D) peaked position is exactly the position of DwPTS.
E) position according to position and present descending synchronous code compares, and revises the frame synchronization index signal.
F) every frame all carries out synchronous track-while-scan.
The present invention adapts to third generation TD-SCDMA communication protocol, by using new method for processing baseband signal, a kind of new path-measuring receiver is provided, have characteristics such as high speed, real-time, can realize the real-time measurement of parameter, can carry out parameter measurement to the TD-SCDMA signal of each frame, speed reached for 200 point/seconds.TD-SCDMA agreement regulation, TD-SCDMA frame time length is 5ms, measures if can realize real-time parameter, then needs every frame to carry out primary parameter and measures, speed was 200 point/seconds.Be the highest measurement speed of TD-SCDMA road detector.
Path-measuring receiver of the present invention can carry out parameter to 32 descending synchronous codes simultaneously to be followed the tracks of.TD-SCDMA agreement regulation descending synchronous code has 32 kinds, is used to distinguish the base station, and different descending synchronous codes is used in different base stations.Descending synchronous code is used for down-going synchronous.The TD-SCDMA road detector can realize all descending the measurement of heart synchronous code to follow the tracks of at present, is the measuring limit of TD-SCDMA road detector to descending synchronous code.
The present invention also has high synchronous detecting sensitivity.The TD-SCDMA road detector utilizes the algorithm of synchronous detecting under the situation of locking frequency point, realized very high synchronozing sensitivity.
The present invention is by seeking the TD-SCDMA signal of in-band signal the best automatically.Searching carrier uses new searching method, revises yield value, searches for all frequencies, and signal energy is sorted, and preceding 8 frequencies the strongest to energy carry out synchronous searching, if on not having synchronously under some gains, the increasing that then will gain continues synchronous searching, up to searching for successfully.Frequency on having guaranteed synchronously like this is the strongest frequency of energy.Other searching carriers are to carry out the search of frequency one by one, and what search is in front the frequency of sorting, and is not the frequency of signal strength signal intensity maximum.
As mentioned above, although represented and described the present invention with reference to specific preferred embodiment, but it shall not be construed as the restriction to the present invention self, those skilled in the art should be understood that, under the prerequisite of the spirit and scope of the present invention that do not break away from the claims definition, can make various variations in the form and details to it.Appending claims has covered all such changes and modifications in the spirit and scope of the invention.