CN101027620A - Systems and methods for minimizing static leakage of an integrated circuit - Google Patents
Systems and methods for minimizing static leakage of an integrated circuit Download PDFInfo
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Abstract
To minimize static leakage of an integrated circuit, a charge pump generates a negative voltage to be applied to a 'sleep' transistor cascaded to a logic gate of the integrated circuit. An adaptive leakage controller determines continuously or periodically whether to adjust the negative voltage to minimize the static leakage. A negative voltage regulator adjusts the negative voltage depending on the determination. Some embodiments determine whether to adjust the negative voltage by monitoring one or more parameters of the sleep transistor. Some embodiments determine whether to adjust the negative voltage by monitoring one or more parameters of an emulated sleep transistor.
Description
The cross reference of related application
The application requires the U.S. Provisional Patent Application No.60/586 that is entitled as " Systems and Methods for I/O andPower Island Management and Leakage Control on Integrated Circuits (system and method for I/O, power island management and electric leakage control on the integrated circuit) " of submission on July 9th, 2004,565 right of priority, this application is incorporated herein by reference.The application also relates to the U.S. Patent application No.10/840 that is entitled as " Managing Power on Integrated Circuits Using Power Islands (utilizing power island management integrated circuit power) " of submission on May 7th, 2004,893, this application is incorporated herein by reference.
Technical field
The present invention relates generally to integrated circuit, and the system and method for negative voltage particularly is provided in integrated circuit.
Background technology
A purpose of design of integrated circuit is to reduce power consumption.Device with battery, for example mobile phone and notebook computer need to reduce power consumption in the integrated circuit especially to extend the life of a cell.In addition, reduction in power consumption has prevented that integrated circuit is overheated, and has reduced the heat exhaustion of integrated circuit, and in some cases, this can eliminate or simplify required heat radiator of cooling integrated circuit and/or fan.And the minimizing of IC power consumption has also reduced the AC power consumption of the device that comprises integrated circuit.
For integrated circuit, challenging design object is to improve performance.A kind of mode that improves performance is by increasing the maximum operation frequency of circuit.In order to increase the maximum operation frequency of circuit, or in littler zone integrated more function, ic manufacturing technology has dwindled the device size of discrete component (for example transistor) on the integrated circuit.
But, since the device size scope of element be 250 nanometers to 130 nanometers or following, therefore, the current drain (again be called static leakage) of device under standby mode become in the integrated circuit power budget ever-increasing most.For example, emulation illustrates, and for the integrated circuit of 50 watts of the consumption of using 130 nano-devices to make up, the power consumption above 20% is owing to static leakage causes.For littler device, the static leakage that emulation illustrates the integrated circuit that uses 50 nanometer feature sizes has comprised about 50% of total power budget.
The a solution that reduces static leakage comprises the one or more sleep transistors that are connected to the logic gate of integrated circuit of use.Provide control signal can reduce the static leakage of logic gate to sleep transistor.
Summary of the invention
A kind of system that is used to minimize the static leakage of integrated circuit comprises: charge pump, self-adaptation leakaging controller and negative voltage regulator.This charge pump produces the negative voltage that will offer sleep transistor.This sleep transistor is configured to the static leakage of the logic gate of control integrated circuit.In certain embodiments, logic gate can be arranged in the power island of integrated circuit.This adaptive controller determines whether to regulate negative voltage to minimize described static leakage.This adaptive controller can be continuously or is periodically determined whether to regulate described negative voltage.Described negative voltage regulator is according to determining that the result regulates described negative voltage.
A kind of method that is used to minimize the static leakage of integrated circuit comprises: produce negative voltage; Provide negative voltage to sleep transistor; Determine whether to regulate negative voltage with minimum static leakage; And regulate negative voltage according to definite result.This method can comprise the static leakage of the logic gate of controlling the integrated circuit with sleep transistor.This method can comprise the transistorized one or more parameters of monitoring sleep.
An advantage of the invention is: because the self-adaptation leakaging controller determines whether to regulate negative voltage, therefore along with the variation of the working temperature of integrated circuit, or along with the fluctuation of voltage or the variation of manufacturing, and minimum static leakage.Not to regulate fixing negative voltage, offer the negative voltage of sleep transistor with minimum static leakage but regulate.Another advantage is to use the single threshold transistor circuit in integrated circuit, has reduced the complexity of integrated circuit fabrication process.An advantage is to produce negative voltage in integrated circuit again, and the element of having avoided producing negative voltage is positioned at the outside of integrated circuit.
Description of drawings
Fig. 1 is for according to one embodiment of present invention, implements to be used for the block scheme of integrated circuit of the system of minimum static leakage;
Fig. 2 is for according to one embodiment of present invention, is used for minimizing the synoptic diagram of sleep transistor of static leakage of the logic gate of Fig. 1;
Fig. 3 is for according to one embodiment of present invention, in the negative voltage range of the grid of sleep transistor, and the curve synoptic diagram of the static leakage of the logic gate among Fig. 2;
Fig. 4 is for according to one embodiment of present invention, is used for minimizing by the sleep transistor that negative voltage is offered Fig. 2 the block scheme of leakage manager systems of the static leakage of logic gate;
Fig. 5 is for according to one embodiment of present invention, minimizes the synoptic diagram of method of the static leakage of the logic gate among Fig. 2;
Fig. 6 is for according to one embodiment of present invention, the synoptic diagram of the self-adaptation leakaging controller (ALC) among Fig. 4;
Fig. 7 is according to the embodiment that selects of the present invention, the synoptic diagram of the ALC among Fig. 4;
Fig. 8 is the embodiment according to the ALC among Fig. 7, is used for minimizing the synoptic diagram of method of static leakage of the logic gate of Fig. 2;
Fig. 9 is for according to one embodiment of present invention, is used for minimizing the synoptic diagram of negative voltage regulator of Fig. 4 of the static leakage of logic gate; And
Figure 10 is for according to one embodiment of present invention, is used for minimizing the synoptic diagram of charge pump of Fig. 4 of the static leakage of logic gate.
Embodiment
Shown in exemplary accompanying drawing (similar or corresponding element in the wherein identical Reference numeral presentation graphs), below describe the exemplary embodiment of system and a method according to the invention in detail.Yet, should be understood that the present invention can implement with various forms.For example, though explanation herein is that static leakage with integrated circuit minimizes, the solution of the present invention also can be implemented on the circuit that is not contained in the integrated circuit.Therefore, disclosed herein specify be not be interpreted as restrictive, but as the basis of claim, and the present invention is applied to the representative basis of any system, structure, method, technology or mode of suitably specializing as instruction those skilled in the art.
Fig. 1 is for according to one embodiment of present invention, implements to be used for the block scheme of integrated circuit 100 of the system of minimum static leakage.Integrated circuit 100 is the electron device of any for example silicon and/or similar manufactured materials.An example of integrated circuit 100 is a System on Chip/SoC.Integrated circuit 100 comprises a plurality of intellecture properties (IP) unit, and these blocks are for realizing the circuit block of specific function.The function that should be appreciated that integrated circuit 100 described herein can realize by single integrated circuit 100, perhaps can separately realize in some integrated circuit 100.The example integrated circuit 100 of Fig. 1 comprises CPU (central processing unit) (CPU) 105, one or more power island 110, one or more power island manager 120, and one or more leakage manager systems 130.
Though for asking easy, only described a power island 110 and a power island manager 120 among Fig. 1, other embodiment of integrated circuit 100 also can comprise an arbitrary number power island 110, power island manager 120 and leakage manager systems 130.In these embodiments, some power island can comprise the circuit different with other power island 110.The common unsettled U.S. Patent application No.10/840 that is entitled as " ManagingPower on Integrated Circuits Using Power Islands (utilizing power island management integrated circuit power) " that submits on May 7th, 2004 further illustrates power island 110 and power island manager 120 in 893.
Power island 110 for the arbitrary portion of integrated circuit 100, describe, divide or cut apart, wherein in these integrated circuit 100 inner control power consumptions.In certain embodiments, a plurality of power island are described based on the positional factor of integrated circuit 100.In certain embodiments, power island 110 is described based on the functional IP unit of integrated circuit 100.In certain embodiments, power island 110 comprises that sub-power island is to provide further feature when the power of control integrated circuit 100.In certain embodiments, each power island of a plurality of power island 110 comprises that power control circuit is with the power in the power controlling island 110.
Though for asking easy, Fig. 1 has only described a leakage manager systems 130 that is connected with a power island manager 120, some embodiment comprise a plurality of leakage manager systems 130.Comprise among the embodiment of a plurality of leakage manager systems 130 that at some each leakage manager systems 130 is connected in a plurality of power island manager 120.In certain embodiments, the function of leakage manager systems 130 is disperseed.In certain embodiments, single leakage manager systems 130 is connected to one or more power island manager 120.Should be appreciated that and on the circuit that does not have power island 110 or power island manager 120, to use principle of the present invention.
Power island 110 comprises one or more logic gates 115.In the embodiment that does not have power island 110, logic gate 115 can comprise any logic gate of integrated circuit 100.The logic gate 115 of exemplary embodiment comprises: logical circuit arbitrarily, for example phase inverter, Sheffer stroke gate, rejection gate, XOR gate and with or door; And storage unit, for example trigger and latch.Logic gate 115 can comprise higher-level boolean logic, and it comprises the combination of single logic gate.
As described further herein, the power of logic gate 115 can be reduced to " sleep pattern " in conjunction with the sleep transistor (not shown).For the static leakage with logic gate 115 minimizes, leakage manager systems 130 produces the negative voltage 150 that will offer sleep transistor.Negative voltage 150 is offered the grid of the NMOS sleep transistor that is connected between logic gate 115 and the ground, can reduce the static leakage of logic gate 115.Leakage manager systems 130 receives negative voltage enable signal 140, then produces negative voltage 150, and negative voltage 150 is transferred to power island 110.Except that negative voltage enable signal 140, negative voltage enable signal 140 can also comprise other signal.Leakage manager systems 130 determines whether to regulate negative voltage 150.As described further herein, determine the result based on this, leakage manager systems 130 is regulated negative voltage 150.
The negative voltage 150 that adjusting offers sleep transistor minimizes the static leakage of logic gate 115.For example, static leakage is based on following parameter, and for example working temperature, voltage fluctuation and making changes and change.Therefore, provide fixing negative voltage can not be well the static leakage of logic gate 115 to be minimized to sleep transistor.In addition, " on chip " generation negative voltage 150 has reduced the needs that element placed integrated circuit 100 outsides.
The selectable device that reduces the static leakage of logic gate 115 comprises multi-Vt CMOS, and one or more high-threshold transistors of connecting with low Threshold Logic Gate 115 are inserted multi-Vt CMOS.High-threshold transistors " shutoff " has been reduced the static leakage of logic gate 115.But high-threshold transistors need be used for the additional manufacturing technology steps of integrated circuit 100, and compared to the nominal threshold value transistor, it has reduced the speed of logic gate 115.Negative voltage 150 is offered low threshold value NMOS sleep transistor, advantageously eliminated the demand that high threshold sleep transistor is provided, make the required processing step of integrated circuit 100 thereby reduced.
Fig. 2 is for according to one embodiment of present invention, is used for the synoptic diagram with the minimized sleep transistor 210 of static leakage of the logic gate 115 of Fig. 1.In certain embodiments, sleep transistor 210 comprises the nmos pass transistor with logic gate (for example phase inverter) 115 cascades.The static leakage of logic gate 115 (is expressed as I as drain-source current
d) and/or drain-gate current (be expressed as I
g) by sleep transistor 210.The static leakage of logic gate 115 equals the I by sleep transistor 210
d+ I
gCan utilize the negative voltage (SLPB) 150 that offers sleep transistor 210, by the drain-source current of regulating sleep transistor 210 and the static leakage that drain-gate current is come steering logic door 115.
Fig. 3 is for according to one embodiment of present invention, in the negative voltage range of sleep transistor 210 grids, and the curve synoptic diagram of the static leakage of the logic gate 115 among Fig. 2.When the negative voltage that offers sleep transistor 210 grids (SLPB) 150 negative sense growth constantly, the drain-source current I of sleep transistor 210
dReduce.But, when the size increases of negative voltage 150 to surpassing minimum leakage point A, for example when some B, the drain-gate current I of sleep transistor 210
gSurpass drain-source current I
dAs a result, the static leakage of logic gate 115 increases.Therefore, negative voltage 150 is adjusted near V (A) (corresponding to drain-source current I
dWith drain-gate current I
gBasically the minimum leakage point A of Xiang Denging), the static leakage in the logic gate 115 is minimized.
Fig. 4 is for according to one embodiment of present invention, is used for minimizing by the sleep transistor 210 that negative voltage is offered Fig. 2 the block scheme of leakage manager systems 130 of the static leakage of logic gate 115.Leakage manager systems 130 comprises: self-adaptation leakaging controller (ALC) 410, negative voltage regulator 420 and charge pump 430.Charge pump 430 produces negative voltage 150 (SLPB).ALC 410 determines whether to regulate negative voltage 150.ALC410 is according to determining that the result produces signal (being expressed as CTRL).According to the CTRL signal, negative voltage regulator 420 is regulated negative voltage 150.
As described further herein, the negative voltage regulator 420 of an embodiment produces to charge pump 430 and enables (EN) signal, so that charge pump increases the size (negative voltage 150 negative senses are increased) of negative voltage 150.If the EN signal is low, then will be from oscillator 425 to charge pump 430 alternating signal forbidden energy, thereby stop charge pump to increase the size of negative voltage 150.Selectively, if the EN signal is high, then the alternating signal of the device of self-oscillation in the future 425 enables, thereby makes charge pump increase the size of negative voltage 150.Because negative voltage regulator 420 determines whether to regulate negative voltage 150 according to ALC410 and triggers the logical and disconnected of (toggle) EN signal, therefore leakage manager systems 130 maintains specific negative voltage place with negative voltage 150, to minimize the static leakage of logic gate 115.
Fig. 5 is for according to one embodiment of present invention, minimizes the synoptic diagram of method of the static leakage of the logic gate 115 among Fig. 2.In step 500, CPU105 (Fig. 1) enters sleep pattern.In step 510, charge pump 430 (Fig. 4) produces negative voltage 150.In step 515, charge pump 430 offers sleep transistor 210 (Fig. 2) with negative voltage 150.In step 520, ALC410 (Fig. 4) can monitor the one or more parameters corresponding to the sleep transistor 210 of logic gate 115 static leakages.Fig. 6-Fig. 8 further specifies as reference, and ALC410 is monitoring sleep transistor 210 directly, perhaps can monitor one or more emulated sleep.
In step 530, ALC410 determines whether to regulate negative voltage 150 and comes minimum static leakage.If ALC410 determines to regulate negative voltage 150, then ALC410 produces the CTRL signal to negative voltage regulator 420 (Fig. 4).In step 540, negative voltage regulator 420 is regulated negative voltage 150 based on the CTRL signal.
In one embodiment, negative voltage regulator 420 is regulated negative voltage 150 continuously.In another embodiment, negative voltage regulator 420 is periodically regulated negative voltage 150.
The influence of temperature variation, voltage fluctuation or manufacturing process variations changes even static leakage is owing to for example being subjected to, and leakage manager systems 130 also can be regulated negative voltage 150 to minimize the static leakage of logic gate 115.Leakage manager systems 130 preferably can all be integrated on the integrated circuit 100, avoids being positioned at integrated circuit 100 component external and produces negative voltage 150.In addition, preferably in the integrated circuit 100 that comprises the single threshold transilog, use leakage manager systems 130, thus the manufacturing of simplifying integrated circuit 100.
Fig. 6-Figure 10 further illustrates the details of the embodiment of the leakage manager systems 130 among Fig. 4.
Fig. 6 is for according to one embodiment of present invention, the synoptic diagram of the self-adaptation leakaging controller (ALC) 410 among Fig. 4.The ALC410 of this embodiment comprises: first emulated sleep 610, second emulated sleep 620, difference (computing) amplifier 630, bias transistor 640 and voltage offset transistor 650.The ALC410 that should be appreciated that this embodiment comprises mimic channel, to determine whether to regulate the negative voltage 150 among Fig. 4 continuously.
Though it is also understood that Fig. 6 bias transistor 640 is depicted as such PMOS transistor: grid is connected to drain electrode, and so that the resistive pressure drop that is added on the bias transistor 640 to be provided, bias transistor 640 can comprise resistance.In the exemplary embodiment with pmos bias transistor 640, the coupling between some bias transistors 640 guarantees that the operation of bias transistor 640 is substantially the same.The voltage offset transistor 650 of exemplary embodiment comprises such PMOS transistor similarly: grid is connected to drain electrode, so that the resistive pressure drop that is added on the voltage offset transistor 650 to be provided.Selectively, voltage offset transistor 650 can comprise resistance.
In Fig. 6, negative voltage 150 (SLPB) offers the grid of first emulated sleep 610.Negative voltage 150 correspondingly produces first electric current by first emulated sleep 610.First electric current can comprise drain-gate current and/or drain-source current.First electric current by first emulated sleep 610 and the static leakage of logic gate 115 are proportional.First electric current produces first pressure drop that is added on the bias transistor (resistor) 640 in drain electrode place of first emulated sleep 610.Inverting input at differential amplifier 630 senses first pressure drop.
For second emulated sleep 620, the resistance of voltage offset transistor 650 makes the size of negative voltage 150 (SLPB) reduce a voltage deviation.The grid of second emulated sleep 620 receives negative voltage 150 and adds voltage deviation.Negative voltage 150 adds that voltage deviation produces second electric current by second emulated sleep 620.Second electric current can comprise drain-gate current and/or drain-source current.Second electric current produces second pressure drop that is added on the bias transistor (resistor) 640 in drain electrode place of second emulated sleep 620.Non-inverting input at differential amplifier 630 senses second pressure drop.
Be in operation, because the grid of voltage offset transistor 650, the second emulated sleep 620 has a small voltage deviation with the grid than first emulated sleep 610 and moves.With reference to Fig. 3, variation can be by the voltage deviation between an A and the B, or V (B)-V (A) represents.As the result of variation, can monitor minimum leakage point A by regulating negative voltage 150, thereby make I (B) be substantially equal to I (A).Should be appreciated that the operational factor of voltage offset transistor 650 influences the size of variation.Operational factor can be based on for example such consideration: the noise on the negative voltage 150 for example.
In principle of work corresponding to Fig. 3, if the size of negative voltage 150 produces first electric current I (B) corresponding to a B in first sleep transistor 610, and negative voltage 150 adds that voltage deviation produces second electric current I (A) corresponding to an A in second sleep transistor 620, then differential amplifier 630 produces the CTRL signals, thus the size adjustment that makes negative voltage 1 50 to I (A) basically with till I (B) equates.Selectively, if negative voltage 150 makes win emulated sleep 610 and the equal basically electric current of second emulated sleep, 620 generations, thus I (A)=I (B), then differential amplifier 630 is kept the currency of CTRL signal.The negative voltage of resulting working point is for being offset such value from ideal operation point: this value equals half by the variation that electric current produced by voltage offset transistor 650.If electric leakage of the grid can be ignored, then to compare with the gate voltage curve of Fig. 3, electric leakage does not change.In the case, the CTRL signal is reduced to its minimum value, makes charge pump 430 (Fig. 4) be operated in maximum negative voltage.
In conjunction with the negative voltage regulator 420 of Fig. 9, by with negative voltage 150 stepless controls at minimum leakage point A place near Fig. 3, the ALC410 of this embodiment advantageously minimizes the static leakage of logic gate 115.
Fig. 7 is according to the embodiment that selects of the present invention, the synoptic diagram of the ALC410 of Fig. 4.The ALC410 of this embodiment comprises: charging transistor 710, capacitor 715, emulated sleep 720, comparer 730, counter 740 and register 750.Switch charging transistor 710 by the controller (not shown), capacitor 715 is charged to positive supply voltage (being VDD).Controller also can switch charging transistor 710, thereby makes capacitor 715 in case charging can be discharged by emulated sleep 720.Comparer 730, counter 740 and register 750 comprise control circuit, to measure capacitor 715 are discharged to the required time of preset value VREF.Fig. 8 is illustrated as reference, and state logic machine (the state logic machine) (not shown) that is connected to register 750 can compare the value that is stored in the register 750.
In this embodiment of ALC410, utilize maximum discharge time corresponding to the capacitor 715 of static leakage minimum value, come to produce the digital value of CTRL signal to negative voltage regulator 420 (Fig. 4).If ALC410 determines to regulate negative voltage 150, then ALC410 is updated periodically the CTRL signal.The work of the ALC410 of this embodiment is described with reference to Fig. 8.
Fig. 8 is the embodiment according to the ALC410 among Fig. 7, is used for minimizing the synoptic diagram of method of static leakage of the logic gate 115 of Fig. 2.In general, this method comprises: capacitor 715 is charged to positive supply voltage VDD; Via emulated sleep 720, capacitor is discharged with the proportional speed of the static leakage of logic gate 115; And adjusting negative voltage 150 is with the velocity of discharge of minimum capacitance device 715.Minimize corresponding to the negative voltage 150 of the minimum current (being minimal static leakage) by emulated sleep 720 the velocity of discharge electric capacity 715, and with maximization discharge time of capacitor 715.
In step 805, the CTRL signal is initialized as its minimum value.With the CTRL signal sets is its minimum value, and indication negative voltage regulator 420 makes that the size of sleep signal SLPB150 is its minimum value.In step 810, capacitor 715 is charged to VDD thereby controller switches charging transistor 710.In step 815, capacitor 715 can be discharged by emulated sleep 720 thereby turn-off charging transistor 710.In step 820, reference voltage V REF is set at a constant voltage less than VDD (for example VDD/2).In step 825, comparer 730 produces output to counter 740 after capacitor 715 is discharged to VREF.Counter 740 is determined capacitor 715 is discharged to the required time of VREF.The counting of register 750 memory counters 740 (being the time).
In step 827, the CTRL signal is increased by one.In step 830, capacitor 715 is charged to VDD once more thereby controller switches charging transistor 710.In step 840, turn-off charging transistor 710.In step 860, comparer 730 produces output to counter 740 after capacitor 715 is discharged to VREF.Counter 740 is determined under the SLPB signal value of new CTRL signal value and correspondence, with the capacitor required time of 715 discharges.
In step 870, the state logic machine will be through step 830-860, the value that is used for the register 750 of active procedure is (promptly for new CTRL signal value and corresponding SLPB signal value, capacitor is discharged the required time) and through step 830-860, the value that is used for the register 750 of previous process compares.Do not reduce with respect to the value of the register 750 that is used for previous process if be used for the value of the register 750 of active procedure, then new CTRL signal value is corresponding than low value with static leakage by emulated sleep 720.In the case, this method turns back to step 827, with further increase CTRL signal and measurement capacitor 715 is discharged the required time.Selectively, in step 870, if high value corresponding to the static leakage that passes through emulated sleep 720, in active procedure capacitor 715 has been discharged required time decreased, the value of then previously stored register 750 is corresponding with the minimum of the static leakage that passes through emulated sleep 720.Use is used for the suitable setting of negative voltage 150 corresponding to the value control negative voltage regulator 420 of the CTRL signal of minimal static leakage with generation.
The advantage of the embodiment of the digital ALC410 of Fig. 7-Fig. 8 comprises digital signal for the CTRL signal.Can digital CTRL signal be sent to a plurality of leakage managers 130 among Fig. 1 by control signal.For example, because silicon is good heat conductor, it is favourable therefore using the individual digit ALC410 with leakage managers 130 and power island manager 120.Therefore in a plurality of power island manager 120 of this embodiment each all comprises negative voltage regulator 420 and charge pump 430, can be as required the function of electric leakage control system 130 be dispersed on the integrated circuit 100.
Fig. 9 is for according to one embodiment of present invention, is used for minimizing the synoptic diagram of negative voltage regulator 420 of Fig. 4 of the static leakage of logic gate 115.Negative voltage regulator 420 comprises: the interface, first voltage divider 905, second voltage divider 915 and the comparer 920 that are used to receive negative voltage 150.In one embodiment, first voltage divider 905 comprises that one group of main body (bulk) is connected to the stacked PMOS transistor (not shown) of source electrode.For example should be appreciated that in first voltage divider 905 three equivalent stacked PMOS transistors that one group of main body is connected to source electrode provide three dividing potential drops (divide-by-3) voltage divider.It is also understood that first voltage divider 905 can comprise the division of arbitrary proportion.First voltage divider 905 provides about the fixed voltage reference point of positive voltage source (for example VDD) (for example C point).The fixed voltage reference point of this embodiment is connected to the negative terminal of comparer 920.
Similarly, in the fixed resistance of second voltage divider 915, three equivalent stacked PMOS transistors that one group of main body is connected to source electrode provide three voltage divider.Should be appreciated that second voltage divider 915 can comprise the division of arbitrary proportion.Second voltage divider 915 of this embodiment is connected to the anode of comparer 920.
In embodiment in conjunction with the simulation CTRL signal that produces by the ALC410 among Fig. 6, according to negative voltage 150 and the signal (CTRL) that is produced by ALC410 that receives, the variohm 910 of second voltage divider 915 allows second voltage divider 915 to produce variable voltage benchmark (for example putting D).Variohm 910 can comprise transistor circuit.According to the CTRL signal, variohm 910 changes between high impedance and Low ESR.
In conjunction with the digital ALC410 among Fig. 7-Fig. 8, the variohm 910 of second voltage divider 915 comprises the switched resistor network by digital CTRL signal controlling.The variohm 910 of this embodiment can comprise two or more switch resistances.Variohm 910 can comprise that also main body is connected to two or more PMOS transistors of source electrode.
At work, negative voltage regulator 420 is regulated negative voltage 150 according to the comparative result between fixed voltage benchmark (C point) and the variable voltage benchmark (D point).Comparer 920 can produce and enable (EN) signal and enable charge pump 430 (Fig. 4), to increase the size of negative voltage 150.If the EN signal is low, alternating signal forbidden energy that then will be from oscillator 425 (Fig. 4) to charge pump 430 stops charge pump 430 to increase the size of negative voltages 150.If the EN signal is high, then the alternating signal of the device of self-oscillation in the future 425 enables, thereby makes charge pump 430 increase the size of negative voltage 150.Therefore, according to the CTRL signal from ALC410, comparer 920 control charge pumps 430 are to increase the big or small of negative voltage or to make its reduction.
Figure 10 is for according to one embodiment of present invention, is used for the synoptic diagram of charge pump 430 of Fig. 4 of minimum static leakage.Charge pump 430 comprises: interface receives positive voltage (for example VDD); Pump capacitor 1010; The other grid 1030 of other grid (pass gate) 1020 of positive cross-couplings and negative cross-couplings.Pump electric capacity 1010 is connected with positive voltage VDD at first end of pump electric capacity 1010.
The positive cross-couplings side grid 1020 of this embodiment capacitively are coupled with the alternating signal from oscillator 425 (Fig. 4).The other grid 1020 of positive cross-couplings are connected with virtual earth 1040 via second end of a PMOS switch 1050 with pump electric capacity 1010, based on alternating signal pump electric capacity 1010 is charged.The other grid 1030 of negative cross-couplings capacitively are coupled with complementary signal from the alternating signal of oscillator 425.The other grid 1030 of negative cross-couplings are connected to negative output terminal (for example negative voltage 150) by second end with pump electric capacity 1010 via the 2nd PMOS switch 1050, based on the complementary signal of alternating signal pump electric capacity 1010 are discharged.Negative output terminal provides negative voltage 150 to sleep transistor 210, with the static leakage of the logic gate in the control chart 2 115.
Should be appreciated that the other grid 1020 and 1030 of cross-couplings comprise the PMOS transistor that the transistorized trap of PMOS is linked together with Ohmic contact.The interface configuration of SLP signal is that substrate is switched between positive reference voltage (for example VDD) and virtual earth 1040.When withdrawing from sleep pattern, activate the SLP signal usually and pass through PMOS switch 1050 and ground short circuit, and guarantee that any PN junction in the well region can forward bias to prevent the power supply that produces VDD.Because the voltage of substrate always is equal to or greater than the voltage of transistorized source electrode of PMOS and drain electrode, therefore there is not electric current to flow to substrate from transistor.The SLP signal can also be forbidden charge pump 430.
Even the variation of static leakage comprise that the leakage manager systems 130 of self-adaptation leakaging controller 410, negative voltage regulator 420 and charge pump among Fig. 4-Figure 10 also can minimize the static leakage of logic gate 115 owing to the influence of for example variation of temperature variation, voltage fluctuation, manufacturing process causes.Leakage manager systems 130 can all be integrated on the integrated circuit 100, has avoided element to be positioned at the outside of integrated circuit 100.In addition, can in the integrated circuit 100 that comprises the single threshold transilog, advantageously use leakage manager systems 130, thus the manufacturing of simplifying integrated circuit 100.
More than be illustrated as exemplary and nonrestrictive.After checking present disclosure, many variations of the present invention it will be apparent to those skilled in the art that.Therefore, scope of the present invention is determined by above explanation, but should be determined with reference to claims and whole equivalency range thereof.
Claims (44)
1. one kind is used for the minimized leakage manager systems of the static leakage of integrated circuit, and described electric leakage control system comprises:
Generator is configured to produce the control signal that will offer sleep transistor;
Monitor is configured to determine whether to regulate described control signal so that described static leakage is minimized; And
Regulator is configured to according to determining that the result regulates described control signal.
2. leakage manager systems as claimed in claim 1, wherein said control signal comprises negative voltage.
3. leakage manager systems as claimed in claim 1, wherein said monitor are configured to determine whether regulate continuously described negative voltage.
4. leakage manager systems as claimed in claim 1, wherein said monitor are configured to determine whether periodically regulate described negative voltage.
5. leakage manager systems as claimed in claim 1, wherein said sleep transistor are configured to control the static leakage of the logic gate of described integrated circuit.
6. leakage manager systems as claimed in claim 5, wherein said logic gate is arranged in the power island of described integrated circuit.
7. one kind is used for the minimized system of the static leakage of integrated circuit, and described system comprises:
Charge pump is configured to produce the negative voltage that will offer sleep transistor;
Leakaging controller is configured to determine whether to regulate described negative voltage so that described static leakage is minimized; And
Negative voltage regulator is configured to according to determining that the result regulates described negative voltage.
8. system as claimed in claim 7, wherein said leakaging controller comprises emulated sleep.
9. system as claimed in claim 7, wherein said leakaging controller is configured to determine whether to regulate described negative voltage according to the electric current by emulated sleep, and the static leakage of the logic gate of wherein said electric current and described integrated circuit is proportional.
10. system as claimed in claim 7, wherein said leakaging controller further is configured to determine whether to regulate continuously described negative voltage.
11. system as claimed in claim 7, wherein said leakaging controller further is configured to determine whether periodically to regulate described negative voltage.
12. system as claimed in claim 7, wherein said leakaging controller further is configured to by relatively the drain-source current and the drain-gate current of emulated sleep determine whether to regulate described negative voltage.
13. system as claimed in claim 12, wherein said drain-source current is substantially equal to described drain-gate current.
14. system as claimed in claim 7, wherein said leakaging controller further is configured to determine whether to regulate described negative voltage based on the comparative result of first electric current by first emulated sleep and second electric current by second emulated sleep, described negative voltage offers the grid of described first emulated sleep, and described negative voltage adds that offset voltage offers the grid of described second emulated sleep.
15. system as claimed in claim 14, wherein described first electric current by described first emulated sleep is substantially equal to described second electric current by described second emulated sleep.
16. system as claimed in claim 7, wherein said sleep transistor is configured to control the static leakage of the logic gate of described integrated circuit.
17. system as claimed in claim 16, wherein said logic gate is arranged in the power island of described integrated circuit.
18. one kind is used for the minimized method of the static leakage of integrated circuit, described method comprises:
Generation will offer the negative voltage of sleep transistor;
Determine whether to regulate described negative voltage to minimize described static leakage; And
Regulate described negative voltage according to definite result.
19. method as claimed in claim 18 wherein determines whether to regulate described negative voltage and regulate described negative voltage continuously.
20. method as claimed in claim 18 wherein periodically determines whether to regulate described negative voltage and regulate described negative voltage.
21. method as claimed in claim 18 also comprises one or more parameters of monitoring described sleep transistor.
22. method as claimed in claim 21, wherein said one or more parameters comprise drain-source current.
23. method as claimed in claim 18 wherein determines whether to regulate described negative voltage and comprises that drain-source current and drain-gate current with described sleep transistor compare.
24. method as claimed in claim 18 wherein determines whether to regulate described negative voltage and comprises:
Described negative voltage is offered emulated sleep;
Cause by described emulated sleep with the proportional electric current of described static leakage; And
Determine whether to regulate described negative voltage according to the magnitude of current.
25. method as claimed in claim 18 wherein determines whether to regulate described negative voltage and comprises:
Described negative voltage is offered first emulated sleep to cause first electric current;
Described negative voltage is added that offset voltage offers second emulated sleep to cause second electric current; And
Described first electric current and described second electric current are compared.
26. one kind is used for the minimized self-adaptation leakaging controller of the static leakage of integrated circuit is comprised:
Capacitor is configured to charge to positive supply voltage;
Transistor is configured to the proportional speed of described static leakage described capacitor is discharged; And
Control circuit is configured to determine whether to regulate the negative voltage that offers sleep transistor, and described sleep transistor is configured to control described static leakage based on the minimum velocity of discharge of described capacitor.
27. self-adaptation leakaging controller as claimed in claim 26, wherein said control circuit comprises:
Variable reference voltage; And
Metering circuit is configured to measure capacitor is discharged to the described required time of variable reference voltage that is substantially equal to.
28. self-adaptation leakaging controller as claimed in claim 26, wherein said metering circuit comprises counter.
29. one kind is used for the minimized method of the static leakage of integrated circuit is comprised:
Capacitor is charged to positive supply voltage;
Described capacitor is discharged with the proportional speed of described static leakage; And
The negative voltage that adjusting offers the sleep transistor grid minimizes with the velocity of discharge with described capacitor.
30. method as claimed in claim 29 comprises that also measurement is discharged to capacitor the time of preset value.
31. method as claimed in claim 29 also comprises:
Measurement is discharged to the required very first time of first preset value with described capacitor;
Measurement is discharged to the second required time of second preset value with described capacitor; And
Comparative result according to the described very first time and described second time is regulated described negative voltage.
32. a self-adaptation leakaging controller that is used to minimize the static leakage of integrated circuit comprises:
First emulated sleep is configured to receive negative voltage and generation and proportional first voltage of described static leakage;
Second emulated sleep is configured to receive the skew of described negative voltage and proportional second voltage of difference of generation and described static leakage.
Control circuit is configured to determine whether to regulate the described negative voltage that offers sleep transistor based on the comparative result between described first voltage and described second voltage, and described sleep transistor is configured to control described static leakage.
33. self-adaptation leakaging controller as claimed in claim 32, wherein said control circuit also are configured to based on equating to determine whether to regulate the described negative voltage that offers described sleep transistor basically between described first voltage and described second voltage.
34. self-adaptation leakaging controller as claimed in claim 32, wherein said first emulated sleep comprises the nmos pass transistor that is configured to receive at the grid of described first emulated sleep described negative voltage, and described second emulated sleep comprises the nmos pass transistor that is configured to receive at the grid of described second emulated sleep skew of described negative voltage; And described control circuit comprises the differential operational amplifier that is connected with the drain electrode of the drain electrode of described first emulated sleep and described second emulated sleep.
35. a negative voltage regulator that is used to minimize the static leakage of integrated circuit comprises:
Interface is configured to receive the negative voltage that offers sleep transistor, and described sleep transistor is configured to control described static leakage;
First voltage divider is configured to provide the fixed voltage benchmark about positive voltage;
Second voltage divider is configured to produce the variable voltage benchmark according to described negative voltage and the signal that receives; And
Comparer is configured to the comparative result according to described fixed voltage benchmark and described variable voltage benchmark, regulates described negative voltage.
36. negative voltage regulator as claimed in claim 35, wherein said first voltage divider comprise that one group of a plurality of terminal is connected to the stacked PMOS transistor of drain electrode.
37. negative voltage regulator as claimed in claim 35, wherein said second voltage divider comprise that one group of a plurality of terminal is connected to the stacked PMOS transistor of drain electrode.
38. negative voltage regulator as claimed in claim 35, wherein said second voltage divider comprises switched resistor network, and the described signal that receives comprises digital signal.
39. negative voltage regulator as claimed in claim 35, wherein said second voltage divider comprises variohm, and the described signal that receives comprises simulating signal.
40. negative voltage regulator as claimed in claim 35, wherein said second voltage divider comprises switched resistor network, and described switched resistor network comprises that one group of a plurality of terminal is connected to the stacked PMOS transistor of drain electrode.
41. a charge pump that is used to minimize the static leakage of logic gate comprises:
Interface is configured to receive positive voltage;
Pump electric capacity is connected to described positive voltage at first end of described pump electric capacity;
The other grid of positive cross-couplings capacitively are coupled with alternating signal, and the other grid of described positive cross-couplings are configured to second end of described pump electric capacity is connected with virtual earth, based on described alternating signal described pump electric capacity is charged; And
The other grid of negative cross-couplings, capacitively be coupled with the complementary signal of described alternating signal, the other grid of described negative cross-couplings are configured to by the complementary signal based on described alternating signal described second end is connected to come with negative output terminal pump electric capacity is discharged, described negative output terminal is configured to provide negative voltage to sleep transistor, and described sleep transistor is configured to control the static leakage of described logic gate.
42. charge pump as claimed in claim 41, other grid of wherein said positive cross-couplings and the other grid of described negative cross-couplings comprise the PMOS transistor.
43. charge pump as claimed in claim 41 also comprises the phase inverter that is connected with described virtual earth, wherein said inverter configuration is for to offer described virtual earth with described positive voltage, to forbid described charge pump.
44. charge pump as claimed in claim 41, wherein said virtual earth comprises the substrate of integrated circuit, other grid of described positive cross-couplings and the other grid of described negative cross-couplings comprise the PMOS transistor, and described substrate switches between the earth potential of described positive voltage and reality.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US58656504P | 2004-07-09 | 2004-07-09 | |
| US60/586,565 | 2004-07-09 | ||
| US10/996,739 | 2004-11-24 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN200910166638.1A Division CN101662276B (en) | 2004-07-09 | 2005-07-05 | Integrated circuit and method for managing power supply thereof |
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| CN101027620A true CN101027620A (en) | 2007-08-29 |
| CN100552592C CN100552592C (en) | 2009-10-21 |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102156502A (en) * | 2010-12-24 | 2011-08-17 | 无锡更芯集成科技有限公司 | Zero static power consumption circuit device for different voltage domains of analogue integrated circuit |
| US8258861B2 (en) | 2010-01-08 | 2012-09-04 | Analog Devices, Inc. | Systems and methods for minimizing power consumption |
-
2005
- 2005-07-05 CN CNB2005800268724A patent/CN100552592C/en not_active Expired - Fee Related
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8258861B2 (en) | 2010-01-08 | 2012-09-04 | Analog Devices, Inc. | Systems and methods for minimizing power consumption |
| CN102156502A (en) * | 2010-12-24 | 2011-08-17 | 无锡更芯集成科技有限公司 | Zero static power consumption circuit device for different voltage domains of analogue integrated circuit |
| CN102156502B (en) * | 2010-12-24 | 2013-04-10 | 常州博拓电子科技有限公司 | Zero static power consumption circuit device for different voltage domains of analogue integrated circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| CN101662276A (en) | 2010-03-03 |
| CN100552592C (en) | 2009-10-21 |
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