CN101018048A - Oscillation circuit - Google Patents
Oscillation circuit Download PDFInfo
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- CN101018048A CN101018048A CN 200710006226 CN200710006226A CN101018048A CN 101018048 A CN101018048 A CN 101018048A CN 200710006226 CN200710006226 CN 200710006226 CN 200710006226 A CN200710006226 A CN 200710006226A CN 101018048 A CN101018048 A CN 101018048A
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Abstract
A first comparator outputs a first signal indicative that a voltage determined according to the amount of charge stored in a first capacitor has reached a first reference voltage. A second comparator outputs a second signal indicative that a voltage determined according to the amount of charge stored in a second capacitor has reached a second reference voltage. An RS flip flop circuit is shifted to a set state by one of the first signal and the second signal and shifted to a reset state by the other signal. When the RS flip flop circuit is in the set state, the first capacitor is in a charge state, and the second capacitor is in a discharge state. When the RS flip flop circuit is in the reset state, the first capacitor is in a discharge state, and the second capacitor is in a charge state.
Description
Technical field
The present invention relates to a kind of oscillating circuit that stable signal is provided to semiconductor integrated circuit etc.
Background technology
In recent years, semiconductor integrated circuit is because becoming more meticulous of production process caused the operating voltage reduction, so because interference causes misoperation easily.Therefore, just require to make private semiconductor integrated circuit not to be subject to the influence of disturbing with microcomputer etc.
On the other hand, as former oscillating circuit, known to the oscillating circuit that can access triangular wave oscillation output of usage count trigger (toggle flip-flop) has been.(with reference to the flat 5-226984 communique of patent disclosure)
At this, the triangular wave oscillating circuit that constitutes like that shown in the flat 5-226984 communique (flat 5=1993) is described.
Capacitor 105a is when switch 102a is in closed condition, by the current charges of fixed power source 101a generation.
Switch 102a is in the output signal of trigger flip-flop 23
Close during for high level, when low level, open.
Comparator 21 compares reference voltage V when the output voltage V o of capacitor 105 becomes
R1When high, and the output voltage of working as capacitor 105a
Become and compare reference voltage V
R1When high, the output signal CM of output high level.
To trigger flip-flop 23 output high level output signal CM, output signal Q and output signals
Be inverted respectively.
By above-mentioned formation, when switch 22 is in the closed condition of contact point f side, output signal CM, output signal Q, output signal
Output voltage
And the waveform of output voltage V o, shown in Figure 3 as the flat 5-226984 communique of figure patent disclosure.(flat 5=1993)
(inventing problem to be solved)
Yet in the above-mentioned oscillating circuit in the past, owing to disturb, the cycle of output signal Q is very easy to unstability.For example, when electric capacity 105 was recharged, output voltage V o was owing to disturb at normal voltage V
R1Under the situation of front and back change, make output signal CM rise for many times thus, and the output signal Q of trigger flip-flop 23 is inverted during this.In the example of Fig. 9, at the interval of moment A till the B constantly, output signal Q always can be in low level under the situation that not have interference, yet has but become high level halfway.Its result, output signal Q and output signal
Waveform phase, from the stable nearly half period of periodic waveform phase deviation.
Summary of the invention
The present invention is to put invention in view of the above problems.Even if its purpose is to provide the oscillating circuit that the signal in stable cycle is provided under a kind of situation that takes place to disturb.
(for solving the method for problem)
For solving above-mentioned problem, first oscillating circuit of embodiments of the present invention comprises:
By the current charges that power supply produces, also have first and second electric capacity of discharge,
Relatively corresponding to first voltage and first normal voltage of the quantity of electric charge that stores in above-mentioned first electric capacity, above-mentioned first voltage of output expression arrives first comparison circuit of first signal of first normal voltage,
Relatively corresponding to second voltage and second normal voltage of the quantity of electric charge that stores in above-mentioned second electric capacity, above-mentioned second voltage of output expression arrives second comparison circuit of the secondary signal of second normal voltage,
In above-mentioned first signal and the above-mentioned secondary signal by they one of become stationary state, by their one of the other rest-set flip-flop circuit that returns to form that becomes,
Making above-mentioned first electric capacity, be in charged state during for stationary state at above-mentioned rest-set flip-flop circuit, is first charge-discharge control circuit that is in discharge condition when returning to form at above-mentioned rest-set flip-flop circuit,
Make above-mentioned second electric capacity, be in charged state when returning to form, be in second charge-discharge control circuit of discharge condition during for stationary state, be feature at above-mentioned rest-set flip-flop circuit at above-mentioned rest-set flip-flop circuit.
According to first oscillating circuit, one of first voltage and second voltage, even if because disturb change before and after normal voltage, the counter-rotating number of times of the output of rest-set flip-flop circuit becomes the same with the situation that does not have to disturb.Therefore, the rest-set flip-flop circuit can be exported stable periodic signal.
Second oscillating circuit of embodiments of the present invention comprises:
By the current charges that power supply produces, also have first and second electric capacity of discharge,
Relatively corresponding to first voltage and first normal voltage of the quantity of electric charge that stores in above-mentioned first electric capacity, above-mentioned first voltage of output expression arrives first comparison circuit of first signal of first normal voltage,
Relatively corresponding to second voltage and second normal voltage of the quantity of electric charge that stores in above-mentioned second electric capacity, above-mentioned second voltage of output expression arrives second comparison circuit of the secondary signal of second normal voltage,
Become stationary state by above-mentioned first signal of above-mentioned first comparison circuit output, when stationary state, become the first rest-set flip-flop circuit that returns to form by the above-mentioned secondary signal of above-mentioned second comparison circuit output,
Become stationary state by the above-mentioned secondary signal of above-mentioned second comparison circuit output, when stationary state, become the second rest-set flip-flop circuit that returns to form by above-mentioned first signal of above-mentioned first comparison circuit output,
When the above-mentioned first rest-set flip-flop circuit changes stationary state into from returning to form, and the toggle flipflop circuit of the above-mentioned second rest-set flip-flop circuit change stationary state into from returning to form time counter-rotating output,
Selectively conversion: corresponding to the output of above-mentioned toggle flipflop circuit, when making the charging of above-mentioned first electric capacity, when also making the state of above-mentioned second capacitor discharge and making above-mentioned first capacitor discharge, also make the charge-discharge control circuit of the state of above-mentioned second electric capacity charging, be feature.
According to second oscillating circuit, even if first voltage is because disturb change before and after normal voltage, the rising number of times of the output of the first rest-set flip-flop circuit becomes the same with the situation that does not have to disturb.Equally, even if second voltage is because disturb change before and after normal voltage, the rising number of times of the output of the second rest-set flip-flop circuit becomes the same with the situation that does not have to disturb.Therefore, the toggle flipflop circuit can be exported stable periodic signal.
The 3rd oscillating circuit of embodiments of the present invention,
Be in second oscillating circuit,
The said fixing state, for output is the state of high level,
Above-mentioned returning to form, for output is low level state,
Also comprise:
When the output of the above-mentioned first rest-set flip-flop circuit is risen, first single-shot trigger circuit of first pulse signal of output high level,
When the output of the above-mentioned second rest-set flip-flop circuit is risen, second single-shot trigger circuit of second pulse signal of output high level,
Export above-mentioned first pulse signal and above-mentioned second pulse signal " or " OR circuit, in addition
Above-mentioned toggle flipflop circuit constitutes the rising edge at above-mentioned OR circuit, or drop edge counter-rotating output, is feature.
The 4th oscillating circuit of embodiments of the present invention is comprising:
First electric capacity of the current charges that produces by power supply,
Corresponding to the voltage of the quantity of electric charge that stores in above-mentioned first electric capacity, after rising to first normal voltage, drop in the interval till second normal voltage of forcing down than above-mentioned first standard electric by above-mentioned charging, export first comparison circuit of first signal, or
First electric capacity of the current discharge that produces by power supply,
Voltage corresponding to the quantity of electric charge that stores in above-mentioned first electric capacity, after dropping to first normal voltage, rise to than in the interval till the second high normal voltage of above-mentioned first normal voltage by above-mentioned charging, export first comparison circuit of first signal, in one the time, also comprise:
Second electric capacity of the current charges that produces by power supply,
Corresponding to the voltage of the quantity of electric charge that stores in above-mentioned second electric capacity, after rising to the 3rd normal voltage, drop in the interval till the 4th normal voltage of forcing down than above-mentioned the 3rd standard electric by above-mentioned charging, second comparison circuit of output secondary signal, or
Second electric capacity of the current discharge that produces by power supply,
Voltage corresponding to the quantity of electric charge that stores in above-mentioned second electric capacity, after dropping to the 3rd normal voltage, rise to than in the interval till the high fast normal voltage of above-mentioned the 3rd normal voltage by above-mentioned charging, output secondary signal second comparison circuit, in one the time, also comprise:
When above-mentioned first signal of output or secondary signal, the toggle flipflop circuit of counter-rotating output,
Selectively above-mentioned first electric capacity of convert charging the time, the state of above-mentioned second electric capacity that discharges and when discharging above-mentioned first electric capacity, the charge-discharge control circuit of the state of above-mentioned second electric capacity that charges is feature.
According to the 4th oscillating circuit, even if disturb, the voltage that needs only the quantity of electric charge that stores corresponding to first electric capacity arrives second normal voltage, or the voltage of the quantity of electric charge that stores corresponding to second electric capacity does not arrive the 4th normal voltage, the influence that just can not occur disturbing in the output of toggle flipflop circuit.Therefore, the toggle flipflop circuit can be exported the signal in stable cycle.
The 5th oscillating circuit of embodiments of the present invention, be first, second, and any one oscillating circuit of the 4th in, with
Above-mentioned first and second electric capacity, the current charges or the discharge that are produced by same power supply are feature.
According to the 5th oscillating circuit, first and second electric capacity is by the current charges or the discharge that equate, so can to obtain repeating than (Duty than) be 50% oscillator signal.
The 6th oscillating circuit of embodiments of the present invention,
Be in first oscillating circuit, with
Above-mentioned first and second charge-discharge control circuit constitutes: when charging, an end separately of above-mentioned first and second electric capacity is connected on the power supply, when discharge, the two ends separately of above-mentioned first and second electric capacity is separated, be feature.
The 7th oscillating circuit of embodiments of the present invention,
Be in any one oscillating circuit of the second and the 4th, with
Above-mentioned charge-discharge control circuit makes above-mentioned first and second electric capacity, and an end is connected on the power supply and charges, and makes above-mentioned first and second electric capacity, and discharge is separated at two ends, is feature.
Description of drawings
Fig. 1 is the block diagram that expression execution mode 1 related oscillating circuit constitutes.
Fig. 2 is the block diagram of the formation of first related charge-discharge control circuit 109 of expression execution mode 1 and charge-discharge control circuit 110.
Fig. 3 is the pulse diagram of the related oscillating circuit work of expression execution mode 1.
Fig. 4 is the block diagram that expression execution mode 2 related oscillating circuits constitute.
Fig. 5 is the block diagram of the formation of the related single-shot trigger circuit 204,205 of expression execution mode 2.
Fig. 6 is the pulse diagram of the related oscillating circuit work of expression execution mode 2.
Fig. 7 is the block diagram that expression execution mode 3 related oscillating circuits constitute.
Fig. 8 is the pulse diagram of the related oscillating circuit work of expression execution mode 3.
Fig. 9 is the block diagram that the oscillating circuit before the expression constitutes.
Embodiment
Below, with reference to the description of drawings embodiments of the present invention.Still, in each following execution mode, the inscape that has identical functions with other execution modes marks identical symbol and omits explanation.
" working of an invention mode 1 "
The oscillating circuit of execution mode 1, as shown in Figure 1, comprising: power circuit 101, the first electric capacity 102, second electric capacity 103, reference power supply 104, comparison circuit 105, negative circuit 106, comparison circuit 107, rest-set flip-flop circuit 108, the first charge-discharge control circuits 109, and second charge-discharge control circuit 110.The oscillating circuit of present embodiment is arranged in the semiconductor integrated circuit.
Rest-set flip-flop circuit 108 becomes stationary state by the high level of negative circuit 106 output (first signal), is become by the low level output (secondary signal) of comparison circuit 107 to return to form.And, the counter-rotating output signal QB of the reverse signal of output signal output Q and output signal Q.
First charge-discharge control circuit 109 as shown in Figure 2, comprises PMOS transistor 109a and nmos pass transistor 109b.On their grid, the output signal Q of input rest-set flip-flop circuit 108.By such formation, first charge-discharge control circuit 109, control is supplied with to the electric charge of first electric capacity 102 from power circuit 101.In more detail, first charge-discharge control circuit 109, make first electric capacity 102, (when rest-set flip-flop circuit 108 becomes stationary state) becomes discharge condition when output signal Q is high level, and (rest-set flip-flop circuit 108 becomes when returning to form) became charged state when output signal Q was low level.
Second charge-discharge control circuit 110 as shown in Figure 2, comprises PMOS transistor 110a and nmos pass transistor 110b.On their grid, the counter-rotating output signal QB of input rest-set flip-flop circuit 108.By such formation, second charge-discharge control circuit 110, control is supplied with to the electric charge of second electric capacity 103 from power circuit 101.In more detail, second charge-discharge control circuit 110, make second electric capacity 103, (rest-set flip-flop circuit 108 becomes when returning to form) becomes discharge condition when counter-rotating output signal QB is high level, and (when rest-set flip-flop circuit 108 becomes stationary state) became charged state when counter-rotating output signal QB was low level.
Next, with regard to the work of the oscillating circuit of above-mentioned formation, describe with reference to the pulse diagram of Fig. 3.The pulse diagram of Fig. 3 is illustrated in moment B between the moment C, the waveform of each signal of the situation of voltage Vst because interference voltage V2 is above standard.
The moment A of Fig. 3, the signal of input high level on the S of rest-set flip-flop circuit 108 terminal, output signal Q becomes high level from low level, and counter-rotating output signal QB becomes low level from high level.Q becomes high level by output signal, and first charge-discharge control circuit 109 carries out the action that discharges to ground connection one side from the electric charge that first electric capacity 102 stores.Thus, the voltage V1 of first electric capacity 102 drops to low level from high level.On the other hand, QB becomes low level by the counter-rotating output signal, and second charge-discharge control circuit 110 makes the action of second electric capacity, 103 chargings.Thus, the voltage V2 of second electric capacity 103 rises corresponding to the Charge Storage of charging.
The voltage V2 of second electric capacity 103 is the moment B from moment A to the voltage Vst that is above standard, because charging continues to rise.A is input to the signal of R terminal between the moment B constantly, and just the output of comparison circuit 107 becomes high level.In the meantime, the output signal Q of rest-set flip-flop circuit 108 keeps high level, and counter-rotating output signal QB keeps low level.Also have, the voltage V1 of first electric capacity 102, moment A begin down will, in case arrive low level, till B constantly, be low level always.
At the voltage V2 of the moment B second electric capacity 103 voltage Vst that is above standard, the output of comparison circuit 107, just comparative result becomes low level, on the R terminal of rest-set flip-flop circuit 108, the signal of input low level.Thus, the output signal Q of rest-set flip-flop circuit 108 becomes low level from high level, and counter-rotating output signal QB becomes high level from low level.QB becomes high level by the counter-rotating output signal, second charge-discharge control circuit 110, the action that the electric charge that second electric capacity 103 is stored discharges to ground connection one side.Thus, the voltage V2 of second electric capacity 103 drops to low level from high level.On the other hand, Q becomes low level by output signal, and first charge-discharge control circuit 109 makes the action of first electric capacity, 102 chargings.Thus, the voltage V1 of first electric capacity 102 is corresponding to the storage of charging charge and rise.
The voltage V1 of first electric capacity 102 is the moment C from moment B to the voltage Vst that is above standard, because charging continues to rise.B is between the moment C constantly, and the output signal Q of rest-set flip-flop circuit 108 keeps low level, and counter-rotating output signal QB keeps high level.Also have, the voltage V2 of second electric capacity 103, moment B begin down will, in case arrive low level, till C constantly, be low level always.
At this, in a single day rest-set flip-flop circuit 108 keeps low level signal by the signal at R terminal input low level, till the input high level signal, this output is changed to the S terminal.Therefore, as shown in Figure 3, to the moment C, voltage V2 is owing to disturb the voltage Vst that is above standard from moment B, even if the signal of input low level on the R terminal of rest-set flip-flop circuit 108, the output signal Q of rest-set flip-flop circuit 108 and counter-rotating output signal QB do not change.
At the voltage V1 of the moment C first electric capacity 102 voltage Vst that is above standard, the output of comparison circuit 105, just comparative result becomes low level, on the S terminal of rest-set flip-flop circuit 108, the signal of input low level.
As mentioned above, by the action in the interval till repeating from moment A to moment C, obtain the output signal Q and the counter-rotating output signal QB of oscillator signal.
As, the oscillating circuit of present embodiment, interference-free influence can provide the output signal Q and the counter-rotating output signal QB in stable cycle.
Also have, only utilized the comparison circuit of hysteresis device to prevent the situation of interference effect by use, the scope that can prevent the interference that influences also obtain increasing to.
Also have, present embodiment gets oscillating circuit, because be simple formation, by a spot of parts number and little circuit area, just can be easy to be assembled in the semiconductor integrated circuit.
" working of an invention mode 2 "
The oscillating circuit of execution mode 2, as shown in Figure 4, comprise: power supply 101, first electric capacity 102, second electric capacity 103, reference power supply 104, comparison circuit 105, negative circuit 106, comparison circuit 107, the first charge-discharge control circuits 109, the second charge-discharge control circuits 110, negative circuit 201, rest-set flip-flop circuit 202,203 (the first and second rest-set flip-flop circuit), single-shot trigger circuit 204,205 (first and second single-shot trigger circuits), NAND circuit 206,207, OR circuit 208 (OR circuit), and toggle flipflop circuit 209.
Single-shot trigger circuit 204,205 is respectively the pulse of the words output defined width that the signal of input rises.Specifically, as shown in Figure 5, comprise negative circuit 204a to 204c respectively, NAND circuit 204d, and negative circuit 204e.Negative circuit 204a to 204c is for NAND circuit 204d exports the sufficient retardation of the pulse of necessary width, delay input signal.In order to increase retardation, use the low inverter of driving force also can.
Still, the formation of single-shot trigger circuit 204,205 has more than and is limited to formation shown in Figure 5.For example, in the present embodiment, the transducer number before the NAND circuit 204d is limited to three by three but have more than, and also can use the combination of buffer and inverter.
Also have, in first charge-discharge control circuit 109, on the grid of PMOS transistor 109a and nmos pass transistor 109b, the counter-rotating output signal QB of input toggle flipflop circuit 209.Have again, in second charge-discharge control circuit 110, on the grid of PMOS transistor 110a and nmos pass transistor 110b, the output signal Q of input toggle flipflop circuit 209.
Next, with regard to the action of the oscillating circuit of above-mentioned such formation, describe with reference to the pulse diagram of Fig. 6.The pulse diagram of Fig. 6, between expression moment B and the moment C, the waveform of each signal of the situation of voltage Vst because interference voltage V2 is above standard.
The moment A of Fig. 6, when the signal CK from OR circuit 208 output reaches high level, the output signal Q of toggle flipflop circuit 209 changes to high level from low level, and the counter-rotating output signal QB of toggle flipflop circuit 209 changes to low level from high level.Q becomes high level by output signal, second charge-discharge control circuit 110, the action that the electric charge that second electric capacity 103 is stored discharges to ground connection one side.Thus, the voltage V2 of second electric capacity 103 drops to low level from high level.On the other hand, QB becomes low level by the counter-rotating output signal, and first charge-discharge control circuit 109 makes the action of first electric capacity, 102 chargings.Thus, the voltage V1 of first electric capacity 102 rises corresponding to the Charge Storage of charging.
The voltage V1 of first electric capacity 102 is the moment B from moment A to the voltage Vst that is above standard, because charging continues to rise.Between this, the output signal Q1 of rest-set flip-flop circuit 202 becomes low level.Also have, the output signal Q2 of rest-set flip-flop circuit 203 becomes high level.And to the moment B, the output signal Q of toggle flipflop circuit 209 keeps high level from moment A, and counter-rotating output signal QB keeps low level.Also have, the voltage V2 of second electric capacity 103 begins to descend at moment A, in case reach low level, is low level till moment B always.
At the voltage V1 of the moment B first electric capacity 102 voltage Vst that is above standard, the output of comparison circuit 105, just comparative result becomes low level.And, the low level output of negative circuit 106 counter-rotating comparison circuits 105, input high level signal on the S1 terminal of rest-set flip-flop circuit 202.Thus, the output signal Q1 of rest-set flip-flop circuit 202 becomes high level.Q1 becomes high level by output signal, the pulse signal of single-shot trigger circuit 204 output high level.And from OR circuit 208, the pulse signal of high level inputs to the triggering input of toggle flipflop circuit 209 as signal CK.Also have, at this moment the output signal Q2 of rest-set flip-flop circuit 203 becomes high level, so when single-shot trigger circuit 204 was exported the pulse signal of high level, the output of NAND circuit 207 became low level.And, being input to the R2 terminal of rest-set flip-flop circuit 203 by the low level of NAND circuit 207, output signal Q2 is reversed to low level.
At moment B, the pulse signal of high level is input to the triggering input of toggle flipflop circuit 209, and the output signal Q of toggle flipflop circuit 209 is reversed to low level from high level, and counter-rotating output signal QB is reversed to high level from low level.Because counter-rotating output signal QB becomes high level, first charge-discharge control circuit 109 carries out the action that discharges to ground connection one side from the electric charge that first electric capacity stores.Thus, the voltage V1 of first electric capacity 102 drops to low level from high level.On the other hand, because output signal Q becomes low level, second charge-discharge control circuit 110 makes the action of second electric capacity, 103 chargings.Thus, the voltage V2 of second electric capacity 103 rises corresponding to the Charge Storage of charging.
The voltage V2 of second electric capacity 103 is the moment C from moment B to the voltage Vst that is above standard, owing to charging is risen.To the moment C, the output signal Q of toggle flipflop circuit 209 keeps low level from moment B, and counter-rotating output signal QB keeps high level.Also have, the voltage V1 of first electric capacity 102 begins to descend at moment B, in case arrive low level, is low level till moment C always.
At this, rest-set flip-flop circuit 202, on moment BS1 terminal owing to imported high level signal in case keep high level, till the signal of input low level, do not change its output to the R1 terminal.Therefore, as shown in Figure 6, between B and the moment C, voltage V1 is owing to disturb the voltage Vst that is above standard constantly, even if the signal of input high level on the S1 terminal of rest-set flip-flop circuit 202, the output signal Q1 of rest-set flip-flop circuit 202 does not change yet.Therefore, in this case, the output signal Q of toggle flipflop circuit 209 and counter-rotating output signal QB do not change yet.
At the voltage V2 of the moment C second electric capacity 103 voltage Vst that is above standard, the output of comparison circuit 107, just comparative result becomes low level.And, the low level output of negative circuit 201 counter-rotating comparison circuits 107, on the S2 of rest-set flip-flop circuit 203 terminal, the input high level signal.Thus, the output signal Q2 of rest-set flip-flop circuit 203 becomes high level.Because output signal Q2 becomes high level, single-shot trigger circuit 205 output high level pulse signals.And from OR circuit 208, the pulse signal of high level inputs to the triggering input of toggle flipflop circuit 209 as signal CK.Also have, because the output signal Q1 of rest-set flip-flop circuit 202 at this moment is a high level, when single-shot trigger circuit 205 was exported the pulse signal of high level, the output of NAND circuit 206 became low level.And, being input to the R1 terminal of rest-set flip-flop circuit 202 by the low level output of NAND circuit 206, output signal Q1 is reversed to low level.
At moment C, the pulse signal of high level, the triggering that is input to toggle flipflop circuit 209 as signal CK is imported, and the output signal Q of toggle flipflop circuit 209 is reversed to high level from low level, and counter-rotating output signal QB is reversed to low level from high level.
As mentioned above, repeat from moment A, just can obtain the output signal Q and the counter-rotating output signal QB of oscillator signal to the action the moment C.
Like this, the oscillating circuit of present embodiment, interference-free influence can provide the output signal Q in stable cycle and the output signal QB that reverses.
" working of an invention mode 3 "
The oscillating circuit of execution mode 3, as shown in Figure 7, comprise: power circuit 101, the first electric capacity 102, the second electric capacity 103, reference power supply 104, first charge-discharge control circuit, 109, the second charge-discharge control circuits 110, comparison circuit 301,302 (Schmidt circuit), NAND circuit 303, and toggle flipflop circuit 209.
Comparison circuit 301 (first comparison circuit), voltage V1 when first electric capacity 102, from surpassing the voltage Vsc (Schmidt's voltage) that exceeds the amplitude (Schmidt's amplitude) of defined owing to charge ratio normal voltage Vst, to becoming between the normal voltage Vst owing to discharging, the signal of output low level, the time output high level signal beyond during this.
Comparison circuit 302 (second comparison circuit), voltage V2 when second electric capacity 103, from surpassing the voltage Vsc (Schmidt's voltage) that exceeds the amplitude (Schmidt's amplitude) of defined owing to charge ratio normal voltage Vst, to becoming between the normal voltage Vst owing to discharging, the signal of output low level, the time output high level signal beyond during this.
Next, with regard to the action of the oscillating circuit of above-mentioned such formation, describe with reference to the pulse diagram of Fig. 8.The pulse diagram of Fig. 8, between expression moment A and the moment B, the waveform of each signal of the situation of voltage Vst because interference voltage V1 is above standard.
The moment A of Fig. 8, when the signal CK from NAND circuit 303 output reaches high level, the output signal Q of toggle flipflop circuit 209 changes to high level from low level, and the counter-rotating output signal QB of toggle flipflop circuit 209 changes to low level from high level.Q becomes high level by output signal, second charge-discharge control circuit 110, the action that the electric charge that second electric capacity 103 is stored discharges to ground connection one side.Thus, the voltage V2 of second electric capacity 103 drops to low level from high level.On the other hand, QB becomes low level by the counter-rotating output signal, and first charge-discharge control circuit 109 makes the action of first electric capacity, 102 chargings.Thus, the voltage V1 of first electric capacity 102 rises corresponding to the Charge Storage of charging.
The voltage V1 of first electric capacity 102 is the moment B from moment A to the voltage Vst that is above standard, because charging continues to rise.Between this, the output signal Q of toggle flipflop circuit 209 keeps high level, and counter-rotating output signal QB keeps low level.Also have, the voltage V2 of second electric capacity 103 begins to descend at moment A, in case reach low level, is low level till moment B always.
At the voltage V1 of moment B first electric capacity 102, surpass and to exceed defined amplitude voltage Vsc than normal voltage Vst, the output of comparison circuit 301, just comparative result becomes low level.And, become high level from the signal CK of NAND circuit 303 outputs.
The signal CK that becomes high level is input to the triggering input of toggle flipflop circuit 209, and the output signal Q of toggle flipflop circuit 209 is reversed to low level from high level, and counter-rotating output signal QB is reversed to high level from low level.Because counter-rotating output signal QB becomes high level, first charge-discharge control circuit 109 carries out the action that discharges to ground connection one side from the electric charge that first electric capacity stores.Thus, the voltage V1 of first electric capacity 102 drops to low level from high level.On the other hand, because output signal Q becomes low level, second charge-discharge control circuit 110 makes the action of second electric capacity, 103 chargings.Thus, the voltage V2 of second electric capacity 103 rises corresponding to the Charge Storage of charging.
At this, as shown in Figure 8, owing to disturb, even if voltage V1 changes before and after normal voltage Vst near the B constantly, when the voltage of comparison circuit 301 rises, voltage V1 and the voltage Vsc that exceeds defined amplitude (Vsc-Vst) than normal voltage Vst are compared, so in output signal Q, can not show this influence.Just, even if because the interference voltage V1 voltage Vst that is above standard, as long as be no more than Vsc, pulse signal that just can input high level in the triggering input of toggle flipflop circuit 209.
The voltage V2 of second electric capacity 103 exceeds from moment B to the voltage Vst that is above standard the moment C of amplitude voltage Vsc of defined, owing to charging continues rising.To the moment C, the output signal Q of toggle flipflop circuit 209 keeps low level from moment B, and counter-rotating output signal QB keeps high level.Also have, the voltage V1 of first electric capacity 102 begins to descend at moment B, in case arrive low level, is low level till moment C always.
At the be above standard amplitude Vsc of voltage Vst defined of the voltage V2 of moment C second electric capacity 103, the output of comparison circuit 302, just comparative result becomes low level.And, become high level from the signal CK of NAND circuit 303 outputs.
Become the signal CK of high level, be input to the triggering input of toggle flipflop circuit 209, the output signal Q of toggle flipflop circuit 209 is reversed to high level from low level, and counter-rotating output signal QB is reversed to low level from high level.
As mentioned above, repeat from moment A, just can obtain the output signal Q and the counter-rotating output signal QB of oscillator signal to the action the moment C.
Like this, the oscillating circuit of present embodiment even if produce to disturb, as long as be no more than voltage Vsc because the voltage V1 of this interference or voltage V2 exceed the amplitude that normal voltage Vst exceeds defined, just can not influence output signal Q and counter-rotating output signal QB.Therefore, the oscillating circuit of present embodiment was compared with former oscillating circuit, and the output signal Q and the counter-rotating output signal QB in stable cycle can be provided.
" other execution mode "
Still, in the oscillating circuit of the respective embodiments described above, by same power circuit 101, first electric capacity 102 and second electric capacity 103 charge.But first electric capacity 102 also can be by different power source charges with second electric capacity 103.
Also have, in the oscillating circuit of the respective embodiments described above, first electric capacity 102 and second electric capacity 103 all are that the back discharge is separated at two ends separately.But, connecting power supply during discharge, also can by the source current discharge.
Also have, the oscillating circuit of the respective embodiments described above is according to the cycle of the needed time control of the charging of electric capacity output signal Q.But the cycle of controlling output signal Q according to the needed time of capacitance discharges also can.Specifically, first electric capacity 102 and second electric capacity 103, discharge by the electric current in the power circuit, the standard electric of any one voltage ratio defined of first electric capacity 102 and second electric capacity 103 is forced down and by comparison circuit 105,107 detected words, and counter-rotating output signal Q and counter-rotating output signal QB also can.Also have, in the situation according to cycle of the needed time control of capacitance discharges output signal Q,, can utilize the trigger of comparison circuit as the oscillating circuit of enforcement mode 3.Specifically, the normal voltage of comparison circuit 301,302, Gao Jike when ratio rose when the voltage of electric capacity descended.
Also have, in the oscillating circuit of above-mentioned execution mode 2,3, the output of toggle flipflop circuit 209 in the edge counter-rotating that is input to the signal rising that triggers input, but also can in the edge counter-rotating that descends.
-practicality-
Oscillating circuit involved in the present invention disturbs the stable cycle that also can provide even if having to produce The effect of signal, at the oscillating circuit that the signal in stable cycle for example is provided to semiconductor integrated circuit Deng in be useful.
Claims (7)
1. oscillating circuit is characterized by:
Comprise:
First and second electric capacity, by the current charges and the discharge of power supply generation,
First comparison circuit, relatively corresponding to first voltage and first normal voltage of the quantity of electric charge that stores in above-mentioned first electric capacity, above-mentioned first voltage of output expression arrives first signal of first normal voltage,
Second comparison circuit, relatively corresponding to second voltage and second normal voltage of the quantity of electric charge that stores in above-mentioned second electric capacity, above-mentioned second voltage of output expression arrives the secondary signal of second normal voltage,
The rest-set flip-flop circuit, in above-mentioned first signal and the above-mentioned secondary signal by they one of become stationary state, return to form by their one of other becoming,
First charge-discharge control circuit makes above-mentioned first electric capacity, is in charged state during for stationary state at above-mentioned rest-set flip-flop circuit, is in discharge condition when returning to form at above-mentioned rest-set flip-flop circuit,
Second charge-discharge control circuit makes above-mentioned second electric capacity, is in charged state when returning to form at above-mentioned rest-set flip-flop circuit, is in discharge condition during for stationary state at above-mentioned rest-set flip-flop circuit.
2. oscillating circuit is characterized by:
Comprise:
First and second electric capacity, by the current charges and the discharge of power supply generation,
First comparison circuit, relatively corresponding to first voltage and first normal voltage of the quantity of electric charge that stores in above-mentioned first electric capacity, above-mentioned first voltage of output expression arrives first signal of first normal voltage,
Second comparison circuit, relatively corresponding to second voltage and second normal voltage of the quantity of electric charge that stores in above-mentioned second electric capacity, above-mentioned second voltage of output expression arrives the secondary signal of second normal voltage,
The first rest-set flip-flop circuit becomes stationary state by above-mentioned first signal of above-mentioned first comparison circuit output, when stationary state, becomes to return to form by the above-mentioned secondary signal of above-mentioned second comparison circuit output,
The second rest-set flip-flop circuit becomes stationary state by the above-mentioned secondary signal of above-mentioned second comparison circuit output, when stationary state, becomes to return to form by above-mentioned first signal of above-mentioned first comparison circuit output,
The toggle flipflop circuit, when the above-mentioned first rest-set flip-flop circuit changes stationary state into from returning to form, and change stationary state into from the returning to form time counter-rotating output of the above-mentioned second rest-set flip-flop circuit,
Charge-discharge control circuit, selectively conversion:, when above-mentioned first electric capacity is charged, also make the state of above-mentioned second capacitor discharge corresponding to the output of above-mentioned toggle flipflop circuit, when making above-mentioned first capacitor discharge, also make the state of above-mentioned second electric capacity charging.
3. oscillating circuit according to claim 2 is characterized by:
The said fixing state, for output is the state of high level,
Above-mentioned returning to form, for output is low level state,
Also comprise:
First single-shot trigger circuit, when the output of the above-mentioned first rest-set flip-flop circuit is risen, first pulse signal of output high level,
Second single-shot trigger circuit, when the output of the above-mentioned second rest-set flip-flop circuit is risen, second pulse signal of output high level,
OR circuit, export above-mentioned first pulse signal and above-mentioned second pulse signal " or ", in addition
Above-mentioned toggle flipflop circuit constitutes the rising edge at above-mentioned OR circuit, or drop edge counter-rotating output.
4. oscillating circuit is characterized by:
Comprising:
First electric capacity, by the current charges of power supply generation,
First comparison circuit corresponding to the voltage of the quantity of electric charge that stores in above-mentioned first electric capacity, drops to after rising to first normal voltage by above-mentioned charging in the interval till second normal voltage of forcing down than above-mentioned first standard electric, exports first signal, or
First electric capacity, by the current discharge of power supply generation,
First comparison circuit, corresponding to the voltage of the quantity of electric charge that stores in above-mentioned first electric capacity, after dropping to first normal voltage, rise to than in the interval till the second high normal voltage of above-mentioned first normal voltage by above-mentioned charging, export first signal, in one the time, also comprise:
Second electric capacity, by the current charges of power supply generation,
Second comparison circuit corresponding to the voltage of the quantity of electric charge that stores in above-mentioned second electric capacity, drops to after rising to the 3rd normal voltage by above-mentioned charging in the interval till the 4th normal voltage of forcing down than above-mentioned the 3rd standard electric, the output secondary signal, or
Second electric capacity, by the current discharge of power supply generation,
Second comparison circuit, corresponding to the voltage of the quantity of electric charge that stores in above-mentioned second electric capacity, after dropping to the 3rd normal voltage, rise to than in the interval till the high fast normal voltage of above-mentioned the 3rd normal voltage the output secondary signal by above-mentioned charging, in one the time, also comprise:
The toggle flipflop circuit, when above-mentioned first signal of output or secondary signal, counter-rotating output,
Charge-discharge control circuit, selectively above-mentioned first electric capacity of convert charging the time, the state of above-mentioned second electric capacity that discharges and when discharging above-mentioned first electric capacity, the state of above-mentioned second electric capacity that charges.
5. according to claim 1,2 or 4 described any one oscillating circuit, it is characterized by:
Above-mentioned first and second electric capacity is by the current charges or the discharge of same power supply generation.
6. oscillating circuit according to claim 1 is characterized by:
Above-mentioned first and second charge-discharge control circuit constitutes: when charging, an end separately of above-mentioned first and second electric capacity is connected on the power supply, when discharge, the two ends separately of above-mentioned first and second electric capacity is separated.
7. according to claim 2 or 4 described oscillating circuits, it is characterized by:
Above-mentioned charge-discharge control circuit makes above-mentioned first and second electric capacity, and an end is connected on the power supply and charges, and makes above-mentioned first and second electric capacity, and discharge is separated at two ends.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2006032251 | 2006-02-09 | ||
| JP2006032251 | 2006-02-09 | ||
| JP2006350262 | 2006-12-26 |
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| CN101018048A true CN101018048A (en) | 2007-08-15 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 200710006226 Pending CN101018048A (en) | 2006-02-09 | 2007-02-07 | Oscillation circuit |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101806619A (en) * | 2010-03-24 | 2010-08-18 | 黄浚豪 | Optical sensing device capable of eliminating dark current |
| CN102487271A (en) * | 2010-12-06 | 2012-06-06 | 株式会社东芝 | Oscillator circuit, radio communication device and semiconductor integrated circuit |
| CN104702216A (en) * | 2013-12-10 | 2015-06-10 | 展讯通信（上海）有限公司 | Oscillating circuit |
-
2007
- 2007-02-07 CN CN 200710006226 patent/CN101018048A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101806619A (en) * | 2010-03-24 | 2010-08-18 | 黄浚豪 | Optical sensing device capable of eliminating dark current |
| CN102487271A (en) * | 2010-12-06 | 2012-06-06 | 株式会社东芝 | Oscillator circuit, radio communication device and semiconductor integrated circuit |
| CN102487271B (en) * | 2010-12-06 | 2014-10-29 | 株式会社东芝 | Oscillator circuit, radio communication device and semiconductor integrated circuit |
| CN104702216A (en) * | 2013-12-10 | 2015-06-10 | 展讯通信（上海）有限公司 | Oscillating circuit |
| CN104702216B (en) * | 2013-12-10 | 2018-04-27 | 展讯通信（上海）有限公司 | A kind of oscillating circuit |
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