CN101017813A - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
CN101017813A
CN101017813A CNA2007100028492A CN200710002849A CN101017813A CN 101017813 A CN101017813 A CN 101017813A CN A2007100028492 A CNA2007100028492 A CN A2007100028492A CN 200710002849 A CN200710002849 A CN 200710002849A CN 101017813 A CN101017813 A CN 101017813A
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CN
China
Prior art keywords
shaped member
plate
mentioned
chip
intermediary layer
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Granted
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CNA2007100028492A
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Chinese (zh)
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CN100511670C (en
Inventor
助川俊一
重并贤一
工藤守
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Sony Corp
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Sony Corp
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    • A61B17/04—Surgical instruments, devices or methods, e.g. tourniquets for suturing wounds; Holders or packages for needles or suture materials
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Abstract

A semiconductor device can be produced easily and cheaply and communicates with a low-power consumption. The producing method comprises: forming communication chip and plane on the surface of silicon medium layer; forming communication chip and plane in the silicon medium layer; configuring two silicon medium layers to be back relative type, and communicating between the communication chips by the plane electrostatic induction.

Description

Semiconductor device
Technical field
The present invention relates to a kind of semiconductor device, particularly relate to the semiconductor device of can be simply and making at an easy rate, can communicate with low-power consumption.
Background technology
Be accompanied by popularizing of electronic equipment, proposed to realize the multicore sheet encapsulation of multi-chip module (MCM) stacked or the lamination techniques of system in package (SIP), chip chamber wiring technique etc. with low cost.
Fig. 1 shows the example of structure of existing multi-chip module.In this multi-chip module, silicon intermediary layer 1 and silicon intermediary layer 21 have been made up.On the surface 2 of silicon intermediary layer 1, chip 5 is installed by projection 4.Similarly, on the surface 22 of silicon intermediary layer 21, chip 25 has been installed by projection 24.And, between the surface 2 of silicon intermediary layer 1 and the back side 3, be formed with through hole 6, between the surface 22 of silicon intermediary layer 21 and the back side 23, be formed with through hole 26.And through hole 6 and through hole 26 interconnect by projection 7.By being formed on the pattern on the silicon intermediary layer 1, through hole 6, projection 7, the through hole 26 of silicon intermediary layer 21 and the pattern on the silicon intermediary layer 21 of silicon intermediary layer 1, carry out chip 5 on the silicon intermediary layer 1 and the communication between the chip 25 on the silicon intermediary layer 21.
Yet, in order to form through hole, not only need to develop new operation, and need form electrode at the back side of silicon intermediary layer, also there is the problem that is difficult to form small through hole etc.
Therefore, shown in the A of known for example Fig. 2, utilize electrostatic capacitance to be coupled into the technology (for example non-patent literature 1) of row communication.In the example of the A of Fig. 2, go up formation electrode 41 on the surface 2 of silicon intermediary layer 1 (face of chip 5 is installed), same going up on the surface 22 of silicon intermediary layer 21 (face of chip 25 is installed) forms electrode 51, makes electrode 41 and electrode 51 relatively dispose the surface 2 of silicon intermediary layer 1 and the surface 22 of silicon intermediary layer 21.Chip 25 on the chip 5 on the surface 2 of silicon intermediary layer 1 and the surface 22 of silicon intermediary layer 21, the communication path of the electrostatic induction by having utilized electrode 41 and electrode 51 communicates respectively.
Non-patent literature 1: " day Longitude エ レ Network ト ロ ニ Network ス " distribution on October 10th, 2005, p.92-99
Summary of the invention
The problem that invention will solve
Yet, if shown in the A of Fig. 2, radio communication is carried out in electrode 41,51 relative configurations, more cheap and the easy manufacturing of then following method, promptly for example shown in the B of Fig. 2, configuration projection 61 communicates by this projection 61 between the surface 22 of the surface 2 of silicon intermediary layer 1 and silicon intermediary layer 21.
The present invention is the invention of making in view of this situation, and realization can be simply and the semiconductor device making at an easy rate, can communicate with low-power consumption.
The means that are used to deal with problems
Side of the present invention is a semiconductor device, and it possesses: the 1st plate-shaped member, and it is the plate-shaped member that is made of high-resistance raw material, is formed with circuit on a face; The 2nd plate-shaped member, it is the plate-shaped member that is made of high-resistance raw material, is formed with circuit on a face; The conduct communication of on the face that is formed with foregoing circuit of above-mentioned the 1st plate-shaped member, disposing a plurality of the 1st flat boards of antenna; The 1st Department of Communication Force, it is configured on the face that is formed with foregoing circuit of above-mentioned the 1st plate-shaped member, communicates by above-mentioned the 1st flat board; The conduct communication of on the face that is formed with foregoing circuit of above-mentioned the 2nd plate-shaped member, disposing a plurality of the 2nd flat boards of antenna; And the 2nd Department of Communication Force, it is configured on the face that is formed with foregoing circuit of above-mentioned the 2nd plate-shaped member, communicates by above-mentioned the 2nd flat board, and above-mentioned the 1st plate-shaped member is configured to make the face that does not form foregoing circuit separately relative with above-mentioned the 2nd plate-shaped member.
Above-mentioned the 1st plate-shaped member can have accepts the closing line that electric power is supplied with, and above-mentioned the 2nd plate-shaped member can have accepts the projection that electric power is supplied with.
Above-mentioned the 1st plate-shaped member and above-mentioned the 2nd plate-shaped member can be the silicon intermediary layers, and its volume resistance is more than the 1k Ω cm.
At least possess two groups of combinations that constitute by above-mentioned the 1st plate-shaped member and above-mentioned the 2nd plate-shaped member, above-mentioned the 1st plate-shaped member of a group and the face that is formed with foregoing circuit of a plate-shaped member in above-mentioned the 2nd plate-shaped member, with above-mentioned the 1st plate-shaped member of another group and the face that is formed with foregoing circuit of a plate-shaped member in above-mentioned the 2nd plate-shaped member, be configured to mutually relatively, communication can between be set with projection and electric power supply projection.
In side of the present invention, be formed with disposed on the face of circuit as communication with the 1st plate-shaped member of a plurality of the 1st flat boards of antenna, with the face that is being formed with circuit on disposed communicate by letter the 2nd plate-shaped member of a plurality of the 2nd flat boards of usefulness antenna of conduct, be configured to make the one side that does not form circuit separately relative.Under the 1st plate-shaped member and the 2nd plate-shaped member are clipped in state between the 1st dull and stereotyped and the 2nd flat board, utilize the electrostatic induction of the 1st dull and stereotyped and the 2nd flat board, between the 2nd Department of Communication Force of the 1st Department of Communication Force of the 1st plate-shaped member and the 2nd plate-shaped member, communicate.
The effect of invention
As mentioned above, according to side of the present invention, can realize semiconductor device.Particularly can realize can be simply and the semiconductor device making at an easy rate, can communicate with low-power consumption.
Description of drawings
Fig. 1 is the cutaway view of the structure of the existing multi-chip module of expression.
Fig. 2 is the figure of the communication between the existing silicon intermediary layer of explanation.
Fig. 3 is the sectional view that the structure of the silicon intermediary layer of using in using multi-chip module of the present invention is described.
Fig. 4 is the sectional view that the cross section structure of multi-chip module of the present invention is used in expression.
Fig. 5 is the plane graph of the planar structure of expression silicon intermediary layer.
Fig. 6 is the plane graph of the structure of expression communication chip.
Fig. 7 is near the sectional view of the structure the expression communication chip.
Fig. 8 is the sectional view of structure that the state of silicon intermediary layer has been made up in expression.
Fig. 9 is the figure of explanation specific insulation.
Figure 10 is the circuit diagram of the structure of expression Department of Communication Force.
Figure 11 is the sequential chart of the circuit diagram action of explanation Figure 10.
Figure 12 is the circuit diagram of the structure of other Department of Communication Forces of expression.
Figure 13 is the sequential chart of action of the Department of Communication Force of explanation Figure 12.
Figure 14 is the plane graph of the planar structure of expression silicon intermediary layer.
Figure 15 is the sectional view that the state of silicon intermediary layer has been made up in explanation.
Figure 16 is the sectional view of the internal structure of expression silicon intermediary layer.
Description of reference numerals
101: the silicon intermediary layer; 102: the surface; 103: the back side; 104: projection; 105: communication chip; 106,107,108: chip; 201: the silicon intermediary layer; 202: the surface; 203: the back side; 204: projection; 205: communication chip; 206,207,208: chip; 301: the silicon intermediary layer; 302: the surface; 303: the back side; 304: projection; 305: communication chip; 306,307: chip; 401: the silicon intermediary layer; 402: the surface; 403: the back side; 404: projection; 405: communication chip; 406,407: chip.
Embodiment
Below, embodiments of the present invention are described, illustrate the corresponding relation of the execution mode of putting down in writing in constitutive requirements of the present invention and specification or the accompanying drawing below.This record is to support embodiments of the present invention to be documented in specification or the accompanying drawing in order to confirm.Therefore, even, do not have to be documented in the execution mode here, do not mean that this execution mode is not corresponding with these constitutive requirements as the execution mode corresponding with constitutive requirements of the present invention though be documented in specification or the accompanying drawing yet.On the contrary, even execution mode is recorded in this as the part corresponding with constitutive requirements, do not mean that this execution mode is not corresponding with the constitutive requirements beyond these constitutive requirements yet.
Side of the present invention is a semiconductor device, and it possesses: the 1st plate-shaped member (for example, the silicon intermediary layer 101 of Fig. 4), and it is the plate-shaped member that is made of high-resistance raw material, is formed with circuit (for example, the chip 106,107 of Fig. 4) on a face; The 2nd plate-shaped member (for example, the silicon intermediary layer 201 of Fig. 4), it is the plate-shaped member that is made of high-resistance raw material, is formed with circuit (for example, the chip 206,207 of Fig. 4) on a face; Go up a plurality of 1st flat boards (for example, the dull and stereotyped 121-1 of Fig. 8) of the conduct communication of configuration at the face that is formed with foregoing circuit (for example, the surface 102 of Fig. 4) of above-mentioned the 1st plate-shaped member with antenna; The 1st Department of Communication Force (for example, the sending part 1001-1-1 of Figure 10), it is configured on the face that is formed with foregoing circuit of above-mentioned the 1st plate-shaped member, communicates by above-mentioned the 1st flat board; The conduct communication of on the face that is formed with foregoing circuit of above-mentioned the 2nd plate-shaped member, disposing a plurality of the 2nd flat boards (for example, the dull and stereotyped 221-1 of Fig. 8) of antenna; And the 2nd Department of Communication Force (for example, the acceptance division 2002-1-1 of Figure 10), it is configured on the face that is formed with foregoing circuit of above-mentioned the 2nd plate-shaped member, communicate by above-mentioned the 2nd flat board, above-mentioned the 1st plate-shaped member and above-mentioned the 2nd plate-shaped member are configured to make the face that does not form foregoing circuit (for example, the back side 103,203 of Fig. 4) separately relative.
Above-mentioned the 1st plate-shaped member can have accepts the closing line (for example, the closing line 504 of Fig. 4) that electric power is supplied with, and above-mentioned the 2nd plate-shaped member can have accepts the projection (for example, the projection 505 of Fig. 4) that electric power is supplied with.
At least (for example possess two groups, the silicon intermediary layer 101 of Fig. 4,201 group, with silicon intermediary layer 301,401 group) combination that constitutes by above-mentioned the 1st plate-shaped member and above-mentioned the 2nd plate-shaped member, a group (for example, the silicon intermediary layer 101 of Fig. 4,201 group) above-mentioned the 1st plate-shaped member and the face that is formed with foregoing circuit of a plate-shaped member in above-mentioned the 2nd plate-shaped member are (for example, the surface 202 of the silicon intermediary layer 201 of Fig. 4), with another group (for example, the silicon intermediary layer 301 of Fig. 4,401 group) above-mentioned the 1st plate-shaped member and the face that is formed with foregoing circuit of a plate-shaped member in above-mentioned the 2nd plate-shaped member are (for example, the surface 302 of the silicon intermediary layer 301 of Fig. 4), be configured to mutually relatively, can communication projection and electric power supply projection (for example, the projection 505 of Fig. 4) be set between.
Below, with reference to the description of drawings embodiments of the present invention.
Fig. 3 shows the structure of the silicon intermediary layer that is encased in the plate-shaped member that the conduct of using in the multi-chip module of the present invention is made of the high resistance raw material.In silicon intermediary layer 101, on its surface 102, dispose communication chip 105, and dispose chip 106,107 by a plurality of projections 104.The detailed content of communication chip 105 is narrated in the back with reference to Fig. 6 to Fig. 8, and itself and other silicon intermediary layer communicates.CPU) or formation such as memory chip 106,107 is for example by CPU (Central Processing Unit:, carry out the processing relevant with the predetermined function that is predetermined respectively.On the surface 102 of silicon intermediary layer 101, though not shown, be formed with wiring pattern.Relative therewith, configuring chip on the back side 103 of the opposition side on surface 102 not.
Silicon intermediary layer 201 has been installed communication chip 205, chip 206,207 by a plurality of projections 204 too on surface 202.On the back side 203 of silicon intermediary layer 201, chip is not installed.
On the surface 302 of silicon intermediary layer 301, dispose communication chip 305, chip 306,307 by a plurality of projections 304.There is not configuring chip on the back side 303 of silicon intermediary layer 301.
Similarly, on the surface 402 of silicon intermediary layer 401, communication chip 405, chip 406,407 have been installed by a plurality of projections 404.On the back side 403 of silicon intermediary layer 401, chip is not installed.
Chip 206,207,306,307,406,407 is also identical with chip 106,107, is the chip of the predetermined function beyond the executive communication.
Fig. 4 shows the structure of the multi-chip module that 101 to 401 combinations of silicon intermediary layer are made.In this multi-chip module 501, silicon intermediary layer 101 and silicon intermediary layer 201 are made as one group, silicon intermediary layer 301 and silicon intermediary layer 401 are made as one group.
That is, silicon intermediary layer 101 and silicon intermediary layer 201 are configured to make respectively flat board (narrating in the back with reference to Fig. 6) as the communication chip 105 and the antenna of communication chip 205 relative respectively and make the back side 103 separately relative with the back side 203.Similarly, silicon intermediary layer 301 and silicon intermediary layer 401 are configured to make each back side 303 and the back side 403 relative and make the flat board of the flat board of communication chip 305 and communication chip 405 relative respectively.
On the surface 503 of substrate 502, be formed with wiring pattern, and as required various chips be installed also (all not having diagram).In addition, surface 503 is connected with the surface 302 of silicon intermediary layer 301 by closing line 506.The surface 102 of silicon intermediary layer 101 also is connected with the surface 503 of substrate 502 by closing line 504.The surface 402 of silicon intermediary layer 401 is connected with the surface 503 of substrate 502 by a plurality of projections 404.In addition, the surface 202 of the surface 302 of silicon intermediary layer 301 and silicon intermediary layer 201 is connected by a plurality of projections 505.
By such formation, the wiring pattern from the surface 503 at substrate 502 forms provides required electric power by communication chip 405, the chip 406,407 of the established part in the projection 404 on the surface 402 that is configured in silicon intermediary layer 401.In addition similarly, by other projections 404 of regulation, between the regulation wiring pattern that forms on the surface 503 of substrate 502 and the communication chip 405 on the silicon intermediary layer 401, chip 406,407, carry out the exchange of signal.
Provide required electric power from the wiring pattern on the surface 503 of substrate 502 by communication chip 305, the chip 306,307 of closing line 506 on silicon intermediary layer 301.Chip 306,307 on the silicon intermediary layer 301 is by communication chip 305 and communication chip 405, communicates with chip 406,407 on the silicon intermediary layer 401.
Wiring pattern from the surface 503 of substrate 502, the wiring pattern on the projection 505 by the wiring pattern on closing line 506, the silicon intermediary layer 301, regulation, the surface 202 of silicon intermediary layer 201, the projection 204 of regulation, the communication chip 205 on silicon intermediary layer 201, chip 206,207 provide electric power.The projection 304 of the projection 505 of projection 204 by regulation of chip 206,207, the wiring pattern on the silicon intermediary layer 201, regulation, the wiring pattern on the silicon intermediary layer 301, regulation communicates with chip 306,307 on the silicon intermediary layer 301.
Wiring pattern from the surface 503 of substrate 502 by the projection 104 of the wiring pattern on closing line 504, the silicon intermediary layer 101, regulation, provides required electric power to communication chip 105, the chip 106,107 of silicon intermediary layer 101.Carry out communicating by letter between chip 106,107 and the chip 206,207 by communication chip 105,205.
Via the communication between the silicon intermediary layer of direct neighbor, there is not the communication between the silicon intermediary layer of direct neighbor by successively.For example, by communication chip 105, communication chip 205, projection 505, carry out the communication between chip 106,107 and the chip 306,307.And, by communication chip 105, communication chip 205, projection 505, communication chip 305, communication chip 405, carry out the communication between chip 106,107 and the chip 406,407.By communication chip 105, communication chip 205, projection 505, communication chip 305, communication chip 405, projection 404, carry out communicating by letter between the not shown chip on the surface 503 of chip 106,107 and substrate 502.
Fig. 5 shows the planar structure of silicon intermediary layer 101 and silicon intermediary layer 201.Silicon intermediary layer 101 is shown in the A of Fig. 5, and at the upper left chip 108 that disposes of chip 106, side disposes chip 107 in the lower-left of chip 106.In the right side area Q of chip 106, be formed with communication zone 111.In this communication zone 111, also dispose communication chip 105-1 to 105-4.
Similarly, be shown on the silicon intermediary layer 201 as Fig. 5 B, side disposes chip 207 in the lower-left of chip 206, disposes chip 208 in the upper left side.Be formed with communication zone 211 among the right side area Q of chip 206, in communication zone 211, also dispose communication chip 205-1 to 205-4.
Though omitted diagram, silicon intermediary layer 301,401 constitutes similarly.
Fig. 6 amplifies the planar structure that shows communication chip 105-1 to 105-4.Communication chip 105-1 side thereon is formed with dull and stereotyped 121-1-1, the 122-1-1 as antenna that is made of metals such as aluminium.The communication that dull and stereotyped 121-1-1,122-1-1 send in groups or receive.Similarly, communication chip 105-1 also has dull and stereotyped 121-1-2,122-1-2 to 121-1-8,122-1-8 from the right side of dull and stereotyped 121-1-1,122-1-1 left in order.In addition similarly, have dull and stereotyped 121-1-9,122-1-9 to 121-1-16,122-1-16 (omitting the diagram of a part of number) from right to left in order at downside.
Similarly, communication chip 105-2 has dull and stereotyped 121-2-1,122-2-1 to 121-2-16,122-2-16, communication chip 105-3 has dull and stereotyped 121-3-1,122-3-1 to 121-3-16,122-3-16, and communication chip 105-4 has dull and stereotyped 121-4-1,122-4-1 to 121-4-16,122-4-16.
Fig. 7 amplifies the cross-section structure that shows communication chip 105-1.As shown in the drawing, right side and left side in the figure of communication chip 105-1 dispose dull and stereotyped 121-1,121-9 by projection 104.In addition, communication chip 105-1 is connected with pad (pad) 131 on the silicon intermediary layer 101 by projection 104.This pad 131 further is connected with not shown wiring pattern.
As shown in Figure 8, the dull and stereotyped 121-1 (121-1-1 to 121-1-16) of silicon intermediary layer 101, be configured to make that with the dull and stereotyped 221-1 (221-1-1 to 221-1-16) of silicon intermediary layer 201 pairing part is relative.Between the dull and stereotyped 121-1 and dull and stereotyped 221-1 of configuration relatively, there is the silicon intermediary layer 101,201 that is made of high-resistance material in its result.Silicon intermediary layer 101,201 is owing to be the high resistance silicon substrate, so the dielectric constant height, the capacitor volume that constitutes by dull and stereotyped 121-1,221-1 with shown in the A of Fig. 2, electrode 41,51 is only compared by the situation of the relative configuration of air, can be made as great value.Its result even dull and stereotyped 121-1,221-1 area are set as less, also can realize enough big Electrostatic Coupling.
The specific insulation of silicon intermediary layer 101 to 401 is made as the above value of 1k Ω cm specifically.Specific insulation when being that W, thickness are that t, length are when flowing through electric current I in the material of L at width, by being determined at distance for the potential difference V that the two ends of L produce, can be obtained from following formula for example as shown in Figure 9.
Specific insulation=(V/I) * (W/L) * t ... (1)
Silicon is non-conductive component originally, therefore can by not with doping impurity in silicon, thereby realize high-resistance silicon intermediary layer.
Communication chip 105,205,305,405 has Department of Communication Force respectively, and this Department of Communication Force is by constituting corresponding at least one side in each dull and stereotyped sending part and the acceptance division.That is, be provided with sending part, be provided with acceptance division for the flat board that receives usefulness for the flat board that sends usefulness.Send and receive at pairing flat board under both situations, be provided with sending part and acceptance division.Communication chip 105 and communication chip 205 are configured to make respectively the dull and stereotyped relative of the flat board that receives usefulness and transmission usefulness.For example, be configured to make under the dull and stereotyped 221-1-1, the 222-1-1 that the receive usefulness situation relative with dull and stereotyped 121-1-1, the 122-1-1 of transmission usefulness, connect as shown in figure 10 the sending part 1001-1-1 corresponding with dull and stereotyped 121-1-1, the 122-1-1 of transmission usefulness and with the corresponding acceptance division 2002-1-1 of dull and stereotyped 221-1-1,222-1-1 of reception usefulness.
Sending part 1001-1-1 is made of inverter 1011 to 1014.By inverter 1011,1012,1013, offer dull and stereotyped 121-1-1 from the signal of terminal IN input, and offer dull and stereotyped 122-1-1 from terminal N2 by inverter 1011,1014 from terminal N1.
On input terminal N3, the N4 of acceptance division 2002-1-1, be connected with dull and stereotyped 221-1-1,222-1-1 respectively.Input terminal N3, N4 are connected on the input terminal of amplifier 2013.Between input terminal N3 and N4, be connected with resistance 2011,2012.Between resistance 2011 and resistance 2012, provide reference voltage V REF.The output of amplifier 2013 is provided for the non-upset input terminal of hysteresis comparator (Hysteresis Comparator) 2014, the upset input terminal of hysteresis comparator 2016.On the upset input terminal of comparator 2014, be provided reference voltage V R1, in the non-upset input terminal of comparator 2016, be provided reference voltage V R2.
The output of comparator 2014 (node N5) is by inverter 2015, is connected with NAND circuit 2019 to constitute in the input of NAND circuit 2018 of cross lock circuit (Network ロ ス ラ Star チ loop).The output of comparator 2016 (node N6) is connected by inverter 2017 in the input of NAND circuit 2019.The output of NAND circuit 2018 is connected in another input of NAND circuit 2019, and the output of NAND circuit 2019 is connected in another input of NAND circuit 2018.
When signal (A of Figure 11) is input to the terminal IN of sending part 1001-1-1, by inverter 1011,1012,1013 in terminal N1 (dull and stereotyped 121-1-1) and by inverter 1011,1014 in terminal N2 (dull and stereotyped 122-1-1), produce the opposite voltage of phase place (voltage that is illustrated by the broken lines of the B of Figure 11 and the voltage of representing by solid line) respectively.Because electrostatic induction produces the opposite voltage (voltage that is illustrated by the broken lines of the C of Figure 11 and the voltage of being represented by solid line) of phase place in dull and stereotyped 221-1-1, the 222-1-1 of receiver side (input terminal N3, N4).The signal that provides by this electrostatic induction is provided amplifier 2013, outputs to node VA (D of Figure 11).
Comparator 2014 will compare from the signal level and the reference voltage V R1 of amplifier 2013 inputs, under the situation greater than reference voltage V R1, to node N5 output positive pulse (E of Figure 11).Similarly, comparator 2016 will compare from the signal level and the reference voltage V R2 of amplifier 2013 outputs, under the situation less than reference voltage V R2, exports positive pulse (F of Figure 11) in node N6.The output of node N5, N6 locks and exports (G of Figure 11) by the cross lock circuit that output is overturn respectively by inverter 2015,2017 upsets when the input negative pulse.
More than be made as by two groups of dull and stereotyped switching signals, but under the situation of the signal that can access enough levels, as shown in figure 12, also can be by one group of dull and stereotyped 121-1-1,221-1-1 switching signal.In this case, sending part 1001-1-1 is made of inverter 1031,1032, and the signal that is input to terminal IN offers the dull and stereotyped 121-1-1 that is connected with terminal N1 by inverter 1031,1032.
Acceptance division 2002-1-1 is made of inverter 2031,2032,2033, by inverter 2031,2033 from terminal OUT output signal from the dull and stereotyped 221-1-1 that is connected with terminal N2.In addition, the output of inverter 2031 is fed back to the input of inverter 2031 by inverter 2032.
When signal (A of Figure 13) is imported into the terminal IN of sending part 1001-1-1, in terminal N1 (dull and stereotyped 121-1-1), produce voltage (B of Figure 13) by inverter 1031,1032.Because electrostatic induction also produces voltage (C of Figure 13) on the dull and stereotyped 221-1-1 of receiver side (input terminal N2).When the voltage of terminal N2 during greater than the threshold value Vth of inverter 2031, the output of inverter 2031 is overturn, and the output of inverter 2032 is also overturn, and the input of quickening inverter 2031 changes.The output of inverter 2031 is further overturn by inverter 2033, from terminal OUT output (D of Figure 13).
More than, by on silicon intermediary layer 101 to 401, carrying communication chip 105 to 405, chip 106 to 406,107 to 407 respectively, thereby form pairing circuit, but also can form pairing circuit by directly being contained on each silicon intermediary layer 101 to 401.
In execution mode shown in Figure 14, formed telecommunication circuit 151-1 to 151-4 on the silicon intermediary layer 101 by directly being contained in.Similarly, formed telecommunication circuit 251-1 to 251-4 on the silicon intermediary layer 201 by directly being contained in.
In this case, when combination silicon intermediary layer 101 and silicon intermediary layer 201, become as shown in figure 15.In this case, (Cosplementary Mental-Oxide Semiconductor: complementary metal oxide semiconductors (CMOS)) circuit 161 to have formed the CMOS corresponding with telecommunication circuit 151-1 to 151-4 on the surface 102 of silicon intermediary layer 101.Even but in this case, also with Fig. 8 in situation be identically formed dull and stereotyped 121-1.
In addition, on the surface on the silicon intermediary layer 201 202, also formed the cmos circuit corresponding 261 with telecommunication circuit 251-1 to 251-4.In this case, also identical with situation among Fig. 8, dull and stereotyped 221-1 is formed on the surface 202 of silicon intermediary layer 201.
Thereby, also can communicate processing in the same manner in this case with the situation among Fig. 8.
Figure 16 shows the inner section example of structure (the CMOS structure in Figure 14, the execution mode shown in Figure 15 is diagram not) of the communication zone 111 of silicon intermediary layer.On P type silicon substrate 1511, be formed with field oxide film 1512.On field oxide film 1512, be formed with polysilicon-metal silicide (polycide) 1513 and be separated with the polysilicon-metal silicide 1514 of predetermined distance from polysilicon-metal silicide 1513.The electric capacity that polysilicon-metal silicide is 1513,1514 is used for stabilized power supply.Polysilicon-metal silicide 1513 is connected on the metal level 1516 by contact 1515.
By through hole 1517, the metal level 1519 that connects metal level 1516 and form across oxide-film 1518 thereon.By through hole 1522, the metal level 1521 that connects metal level 1519 and form across oxide-film 1520 thereon.On metal level 1521, be formed with oxide-film 1523, further be formed with diaphragm 1524 thereon.In diaphragm 1524 and oxide-film 1523, be formed with bonding pad opening 1525.
More than, be that example is illustrated with the situation that applies the present invention to multi-chip module, but the present invention also can be applied to other semiconductor device.
In addition, embodiments of the present invention are not limited to above-mentioned execution mode, can carry out various changes in the scope that does not exceed main points of the present invention.

Claims (4)

1. semiconductor device is characterized in that possessing:
The 1st plate-shaped member, it is the plate-shaped member that is made of high-resistance raw material, is formed with circuit on a face;
The 2nd plate-shaped member, it is the plate-shaped member that is made of high-resistance raw material, is formed with circuit on a face;
The conduct communication of on the face that is formed with foregoing circuit of above-mentioned the 1st plate-shaped member, disposing a plurality of the 1st flat boards of antenna;
The 1st Department of Communication Force, it is configured on the face that is formed with foregoing circuit of above-mentioned the 1st plate-shaped member, communicates by above-mentioned the 1st flat board;
The conduct communication of on the face that is formed with foregoing circuit of above-mentioned the 2nd plate-shaped member, disposing a plurality of the 2nd flat boards of antenna; And
The 2nd Department of Communication Force, it is configured on the face that is formed with foregoing circuit of above-mentioned the 2nd plate-shaped member, communicates by above-mentioned the 2nd flat board,
Above-mentioned the 1st plate-shaped member is configured to make the face that does not form foregoing circuit separately relative with above-mentioned the 2nd plate-shaped member.
2. semiconductor device according to claim 1 is characterized in that,
Above-mentioned the 1st plate-shaped member has accepts the closing line that electric power is supplied with,
Above-mentioned the 2nd plate-shaped member has accepts the projection that electric power is supplied with.
3. semiconductor device according to claim 1 is characterized in that,
Above-mentioned the 1st plate-shaped member and above-mentioned the 2nd plate-shaped member are the silicon intermediary layers, and its volume resistance is more than the 1k Ω cm.
4. semiconductor device according to claim 1 is characterized in that,
At least possess two groups of combinations that constitute by above-mentioned the 1st plate-shaped member and above-mentioned the 2nd plate-shaped member,
Above-mentioned the 1st plate-shaped member of a group and the face that is formed with foregoing circuit of a plate-shaped member in above-mentioned the 2nd plate-shaped member, with above-mentioned the 1st plate-shaped member of another group and above-mentioned the 2nd plate-shaped member in the face that is formed with foregoing circuit of a plate-shaped member, be configured to mutually relatively, between is provided with communicates by letter with projection and electric power supply projection.
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US7578676B2 (en) 2009-08-25

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