CN101017429A - Method for improving first-in first-out FIFO performance and first-in first-out FIFO circuit - Google Patents

Method for improving first-in first-out FIFO performance and first-in first-out FIFO circuit Download PDF

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CN101017429A
CN101017429A CN 200710064252 CN200710064252A CN101017429A CN 101017429 A CN101017429 A CN 101017429A CN 200710064252 CN200710064252 CN 200710064252 CN 200710064252 A CN200710064252 A CN 200710064252A CN 101017429 A CN101017429 A CN 101017429A
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level register
register
data
selector
level
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CN100507828C (en
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余娜敏
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Wuxi Vimicro Corp
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Vimicro Corp
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Abstract

This invention discloses one method and to improve FIFO property and its circuit, which realizes the data press and spring out through three registers, wherein, due to the second and third register space, the said first selector output data only needs spare register. This invention can save circuit area and reduce key path time lag.

Description

Improve the method and the first-in first-out fifo circuit of first-in first-out FIFO performance
Technical field
The present invention relates to communication and computer realm, relate in particular to the technology that improves the FIFO performance.
Background technology
Along with the increase of chip integration, complexity and functional requirement, in a lot of digital circuitries, all needing provides different frequency and clock signals for each functional module of chip internal and peripherals.Between the functional module of these different clock-domains during Data transmission, need FIFO (First In First Out, first in first out) circuit to realize that data address decoding and data select.
Comprise address decoder and MUX in the at present common fifo circuit, for example as shown in Figure 1, provide a kind of fifo circuit, it comprises: 44 are selected 1 first selector; The register Cell of 4 16DW (DoubleWord, double word) is respectively Cell, Cell1, Cell2 and Cell3; Select 1 selector switch for 4 16, and 44 are selected 1 second selector.
When data were pressed into, each 4 selected 1 first selector to drive each register Cell to select a DW to write in the relevant address.Along with the increase of the FIFO degree of depth, the complexity of address decoder also increases, and needed driving force also can increase, and circuit area and time delay have all increased much like this.
Summary of the invention
The invention provides a kind of method and fifo circuit of the FIFO of raising performance, it not only can save circuit area, and can reduce the time delay of critical path.
The present invention is achieved through the following technical solutions:
The invention provides a kind of method that improves first-in first-out FIFO performance, it comprises:
When writing data, judge whether third level register is empty in the next clock period;
If described third level register is empty in the next clock period, then from described first selector, selects data, and it is transferred to described third level register;
If described third level register is not empty in the next clock period, judge then whether second level register is empty in the next clock period, if it is empty, then from described first selector, select data, and it is transferred to second level register, described second level register is pressed into data, and ejects data transmission and give described third level register; If second level register is not empty in the next clock period, then from described first selector, select data, and it is transferred to first order register, and when second level register or third level register when full, output data is given described second level register from described first order register, and described second level register output data is given described third level register;
Described third level register is pressed into data, and ejects data, and is transferred to second selector.
Wherein, the degree of depth of described first order register and third level register is less than described second level register.
The present invention also provides a kind of first-in first-out fifo circuit, and it comprises:
First selector, first order register, second level register, third level register and second selector;
Described first selector, be used for when described third level register the next clock period when empty, select data and give described third level register; And when described third level register be empty in the next clock period, and second level register is then selected data, and it is transferred to second level register when the next clock period is sky; When described third level register be empty in the next clock period, and second level register is then selected data, and it is transferred to first order register when the next clock period is not sky;
Described first order register is used for the data of described first selector transmission are pressed into, and when second level register or third level register when full, the ejection data;
Described second level register is used for described first order data that register ejects, or the data of described first selector transmission are pressed into, and does not eject data when full at third level register;
Described third level register is used for described first order data that register ejects, or the data of described first selector transmission are pressed into, and ejects data and give described second selector.
Wherein, the degree of depth of described first order register and described third level register is less than the degree of depth of described second level register.
7 wherein, and the degree of depth of described third level register is 1DW.
The present invention also provides the method for the another kind of FIFO of raising performance, and it comprises:
Judge whether third level register is empty in the next clock period;
If described third level register is empty in the next clock period, then from described first selector, selects data, and it is transferred to described third level register;
If described third level register is not empty in the next clock period, then from described first selector, selects data, and it is transferred to first order register;
Judge whether third level register is empty in the next clock period, if empty, then output data is given described third level register from described first order register; If be not empty, then output data is given described second level register from described first order register, and described second level register output data is given described third level register;
The data that described third level register is transmitted described first order register, or the data of described first selector transmission, the data that described second level register is transferred to are pressed into, and eject data and give described second selector.
Wherein, the degree of depth of described first order register and described third level register is less than the degree of depth of described second level register.
The present invention also provides another kind of fifo circuit, and it comprises:
First selector, first order register, second level register, third level register and second selector;
Described first selector, be used for when described third level register the next clock period when empty, select data, and it be transferred to described third level register; And, when described third level register when the next clock period be sky, select data, and it be transferred to first order register;
Described first order register is used for the data of described first selector transmission are pressed into; And, when third level register in next clock period when be empty, eject data, and with described data transmission to described third level register; And, when third level register in next clock period when be empty, eject data, and with described data transmission to described second level register;
Described second level register is used for described first order data that register ejects are pressed into, and, eject data, and give described third level register described data transmission;
Described third level register is used for described first order data that register ejects, or the data of described first selector transmission, and the data that described second level register is transferred to are pressed into, and ejects data and give described second selector.
Wherein, the degree of depth of described first order register and described third level register is less than the degree of depth of described second level register.
Wherein, the degree of depth of described third level register is 1DW.
The specific embodiments that is provided by the invention described above as can be seen, it is by three grades of registers, realize that data are pressed into and eject, because when the second level or the third level register during free time, the output data of described first selector only need be pressed into idle register, therefore when the described idle register of driving selects a DW to write relevant address, not only can save circuit area, and can reduce the time delay of critical path.
Description of drawings
The fifo circuit that Fig. 1 provides for prior art;
Fig. 2 is the fundamental diagram of first embodiment provided by the invention;
Fig. 3 is the process flow diagram of second embodiment provided by the invention;
Fig. 4 is the fundamental diagram of the 3rd embodiment provided by the invention;
Fig. 5 is the process flow diagram of the 4th embodiment provided by the invention.
Embodiment
First embodiment provided by the invention is a kind of fifo circuit, and its principle of work comprises as shown in Figure 2:
4 to select 1 first selector 4S1, first order register L1, the degree of depth that the degree of depth is 1DW be that 14DW second level register L2, the degree of depth are the third level register L3 of 1DW, and 4 select 1 second selector 4S1;
The input of the corresponding first order register L1 of output difference of wherein said first selector 4S1, the input of second level register L2, and the input of third level register L3; The input of the corresponding second level register L2 of the output of described first order register L1; The input of the corresponding described third level register L3 of the output of described second level register L2; The input of the corresponding second selector 4S1 of the output of third level register L3.
Data transfer relation between each components and parts is as follows:
When described third level register in next clock period when be empty, described first selector is selected data, and with it to described third level register;
When described third level register be empty in the next clock period, and second level register is when the next clock period is sky, and described first selector is selected data, and it is transferred to second level register;
When described third level register be empty in the next clock period, and second level register is not when the next clock period is sky, and described first selector is selected data, and it is transferred to first order register;
Described first order register is pressed into the data that described first selector is transferred to, and when second level register or third level register when full, eject data;
Data that described second level register is ejected described first order register, or the data that described first selector is transferred to are pressed into, and do not eject data when full at third level register;
The data that described third level register is ejected described first order register, or the data that described first selector is transferred to are pressed into, and eject data and give described second selector.
Described second selector is exported the data that are input in the described second selector successively according to the principle of first-in first-out.
Corresponding described first embodiment, second embodiment provided by the invention is a kind of method of the FIFO of raising performance, its flow process comprises as shown in Figure 3:
Step S101 when writing data, judges whether third level register is empty in the next clock period;
If described third level register is empty in the next clock period, then execution in step S102 selects data from described first selector, and it is transferred to described third level register; Execution in step S108 then.
If described third level register is not empty in the next clock period, then execution in step S103 judges whether second level register is empty in the next clock period;
If second level register is empty in the next clock period, then execution in step S104 selects data from described first selector, and it is transferred to second level register; Next execution in step S105, described second level register is pressed into data, and ejects data and be transferred to described third level register; Execution in step S108 then.
If second level register is not empty in the next clock period, then execution in step S106 selects data from described first selector, and it is transferred to first order register; Next execution in step S107, when second level register or third level register when full, from described first order register, eject data and be transferred to described second level register; When second level register or third level register when full, first order register does not just eject data.Execution in step S105 then, promptly described second level register is pressed into data, and ejects data and be transferred to described third level register; Execution in step S108 then.
Step S108, the data that described third level register is transferred to described first selector, or the data that described second level register transfer is given are pressed into, and eject data, and be transferred to second selector.
Step S109, described second selector according to the principle of first-in first-out, is exported the data that are input in the described second selector successively.
Described first order register among second embodiment and third level register are less than described second level register; Wherein, the degree of depth of described third level register can be 1DW.
The 3rd embodiment provided by the invention is a kind of fifo circuit, and its principle of work comprises as shown in Figure 4:
4 to select 1 first selector 4S1, first order register L1, the degree of depth that the degree of depth is 1DW be that 14DW second level register L2, the degree of depth are the third level register L3 of 1DW, and 4 select 1 second selector 4S1;
The output of wherein said first selector 4S1 is the input of corresponding first order register L1 respectively, and, the input of third level register L3; The input of the corresponding second level register L2 of the output of described first order register L1, and, the input of third level register L3; The input of the corresponding described third level register L3 of the output of described second level register L2; The input of the corresponding second selector 4S1 of the output of described third level register L3.
Data transfer relation between each components and parts is as follows:
First selector, first order register, second level register, third level register and second selector;
When described third level register when the next clock period be sky, described first selector is selected data, and it is transferred to described third level register; When described third level register when the next clock period be sky, described first selector is selected data, and it is transferred to first order register;
Described first order register is pressed into the data that described first selector is transferred to; And, when third level register in next clock period when be empty, eject data, and with described data transmission to described third level register; And, when third level register in next clock period when be empty, eject data, and with described data transmission to described second level register;
Described second level register, with the ejection of described first order register to data be pressed into, and, eject data, and give described third level register described data transmission;
Described third level register, the data that described first order register transfer is given, or the data that are transferred to of described first selector, or the data that described second level register is transferred to are pressed into, and eject data and give described second selector;
Described second selector is exported the data that are input in the described second selector successively according to the principle of first-in first-out.
Corresponding described the 3rd embodiment, the 4th embodiment provided by the invention is a kind of method of the FIFO of raising performance, its flow process comprises as shown in Figure 5:
Step S201 judges whether third level register is empty in the next clock period;
If described third level register is empty in the next clock period, then execution in step S202 selects data from described first selector, and it is transferred to described third level register; Execution in step S208 then.
If described third level register is not empty in the next clock period, then execution in step S203 selects data from described first selector, and it is transferred to first order register; Execution in step S204 then.
Step S204 judges whether third level register is empty in the next clock period;
If empty, then execution in step S205 ejects data and is transferred to described third level register from described first order register;
If be not empty, then execution in step S206 ejects data and is transferred to described second level register from described first order register;
Step S207, the data that described second level register will be transferred to oneself are pressed into, and eject data and be transferred to described third level register;
Step S208, the data that described third level register is transferred to described first selector, or the described first order register transfer data of giving, or the data that described second level register transfer is given are pressed into, and eject data, and be transferred to second selector.
Step S209, described second selector according to the principle of first-in first-out, is exported the data that are input in the described second selector successively.
In the foregoing description, the degree of depth of described first order register and described third level register is less than the degree of depth of described second level register.Described third level register can be 1DW.
As can be seen from the above-described embodiment, because when third level register is idle, the output data of described first selector only need be pressed into third level register, and the degree of depth of third level register is far smaller than the degree of depth of second level register, therefore the duty factor of third level register is less, thereby when the third level register that drives the described free time selects a DW to write relevant address, needed driving force is also smaller, therefore the present invention not only can save circuit area, and can reduce the time delay of critical path.
In addition, when the degree of depth of described third level register only is 1DW, need not between described third level register and described second selector 4S1, other selector switch to be set, thereby can save circuit area, and can reduce time delay.
Be to measure fifo circuit that fifo circuit that prior art provides and first embodiment provided by the invention and the 3rd embodiment provide in area and speed ability data below at following experiment condition:
Test condition:
Library： TSMC?130?1ibrary
Clock?period： 1.5
Clock?uncertainty： 0.3
Clock?transition： 0.3
Input?delay： 0.5(all?inputs)
Output?delay 0.5(all?outputs)
Driver： 0(all?inputs)
Load： 60?AND2X4/A0
The area performance data of the fifo circuit that prior art provides:
Number?of?ports： 278
Number?of?nets： 13549
Number?of?cells： 12174
Number?of?references： 171
Combinational?area： 73988.827256
Noncombinational?area：?29471.725652
Net?Interconnect?area：?undefined(Wire?load?has?zero?net?area)
Total?cell?area： 10368.750000
The area performance data of the fifo circuit that the embodiment of the invention provides:
Number?of?ports： 277
Number?of?nets： 1937
Number?of?cells： 1670
Number?of?references： 121
Combinational?area： 36509.083011
Noncombinational?area：?30149.220699
Net?Interconnect?area：?undefined(Wire?load?has?zero?net?area)
Total?cell?area： 66640.984384
The speed ability data Setup timing violation of the fifo circuit that prior art provides:
Output?violation：-0.14
Input?violation：-0.08
The speed ability data Setup timing violation of the fifo circuit that the embodiment of the invention provides:
Output?no?violation
Input?violation：-0.01
As can be seen, embodiments of the invention can reduce the area of fifo circuit, and the time delay of critical path, thereby the performance of the fifo circuit that can be is strengthened.
Obviously, those skilled in the art can carry out various changes and modification to the present invention and not break away from the spirit and scope of the present invention.Like this, if of the present invention these are revised and modification belongs within the scope of claim of the present invention and equivalent technologies thereof, then the present invention also is intended to comprise these changes and modification interior.

Claims (10)

1, a kind of method that improves first-in first-out FIFO performance is characterized in that, comprising:
When writing data, judge whether third level register is empty in the next clock period;
If described third level register is empty in the next clock period, then from described first selector, selects data, and it is transferred to described third level register;
If described third level register is not empty in the next clock period, judge then whether second level register is empty in the next clock period, if it is empty, then from described first selector, select data, and it is transferred to second level register, described second level register is pressed into data, and ejects data transmission and give described third level register; If second level register is not empty in the next clock period, then from described first selector, select data, and it is transferred to first order register, and when second level register or third level register when full, output data is given described second level register from described first order register, and described second level register output data is given described third level register;
Described third level register is pressed into data, and ejects data, and is transferred to second selector.
2, the method for claim 1 is characterized in that, the degree of depth of described first order register and third level register is less than described second level register.
3, a kind of first-in first-out fifo circuit is characterized in that, comprising:
First selector, first order register, second level register, third level register and second selector;
Described first selector, be used for when described third level register the next clock period when empty, select data and give described third level register; And when described third level register be empty in the next clock period, and second level register is then selected data, and it is transferred to second level register when the next clock period is sky; When described third level register be empty in the next clock period, and second level register is then selected data, and it is transferred to first order register when the next clock period is not sky;
Described first order register is used for the data of described first selector transmission are pressed into, and when second level register or third level register when full, the ejection data;
Described second level register is used for described first order data that register ejects, or the data of described first selector transmission are pressed into, and does not eject data when full at third level register;
Described third level register is used for described first order data that register ejects, or the data of described first selector transmission are pressed into, and ejects data and give described second selector.
4, fifo circuit as claimed in claim 3 is characterized in that, the degree of depth of described first order register and described third level register is less than the degree of depth of described second level register.
As claim 3 or 4 described fifo circuits, it is characterized in that 5, the degree of depth of described third level register is 1DW.
6, a kind of method that improves first-in first-out FIFO performance is characterized in that, comprising:
Judge whether third level register is empty in the next clock period;
If described third level register is empty in the next clock period, then from described first selector, selects data, and it is transferred to described third level register;
If described third level register is not empty in the next clock period, then from described first selector, selects data, and it is transferred to first order register;
Judge whether third level register is empty in the next clock period, if empty, then output data is given described third level register from described first order register; If be not empty, then output data is given described second level register from described first order register, and described second level register output data is given described third level register;
The data that described third level register is transmitted described first order register, or the data of described first selector transmission, the data that described second level register is transferred to are pressed into, and eject data and give described second selector.
7, method as claimed in claim 6 is characterized in that, the degree of depth of described first order register and described third level register is less than the degree of depth of described second level register.
8, a kind of first-in first-out fifo circuit is characterized in that, comprising:
First selector, first order register, second level register, third level register and second selector;
Described first selector, be used for when described third level register the next clock period when empty, select data, and it be transferred to described third level register; And, when described third level register when the next clock period be sky, select data, and it be transferred to first order register;
Described first order register is used for the data of described first selector transmission are pressed into; And, when third level register in next clock period when be empty, eject data, and with described data transmission to described third level register; And, when third level register in next clock period when be empty, eject data, and with described data transmission to described second level register;
Described second level register is used for described first order data that register ejects are pressed into, and, eject data, and give described third level register described data transmission;
Described third level register is used for described first order data that register ejects, or the data of described first selector transmission, and the data that described second level register is transferred to are pressed into, and ejects data and give described second selector.
9, fifo circuit as claimed in claim 8 is characterized in that, the degree of depth of described first order register and described third level register is less than the degree of depth of described second level register.
10, fifo circuit as claimed in claim 8 or 9 is characterized in that the degree of depth of described third level register is 1DW.
CNB2007100642520A 2007-03-07 2007-03-07 Method for improving first-in first-out FIFO performance and first-in first-out FIFO circuit Expired - Fee Related CN100507828C (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104102473A (en) * 2013-04-12 2014-10-15 杭州迪普科技有限公司 Device for realizing high-speed data distribution

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104102473A (en) * 2013-04-12 2014-10-15 杭州迪普科技有限公司 Device for realizing high-speed data distribution
CN104102473B (en) * 2013-04-12 2017-08-11 杭州迪普科技股份有限公司 A kind of device for realizing data high-speed distribution

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